PA28F002BC-T80 [INTEL]
28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY; 28F002BC 2兆位（ 256K ×8 ）， BOOT BLOCK FLASH MEMORY
| 型号： | PA28F002BC-T80 |
| 厂家： | 
INTEL |
| 描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 文件： | 总37页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
E
28F002BC 2-MBIT (256K X 8)
BOOT BLOCK FLASH MEMORY
High Performance Read
Extended Cycling Capability
80/120 ns Max Access Time
40 ns Max. Output Enable Time
100,000 Block Erase Cycles
Automated Byte Write and Block Erase
Low Power Consumption
Industry-Standard Command User
Interface
20 mA Typical Read Current
x8-Only Input/Output Architecture
Space-Constrained 8-bit
Applications
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Reset/Deep Power-Down Input
0.2 µA ICC Typical
Provides Reset for Boot Operations
Industry-Standard Surface Mount
Packaging
One 128-KB Main Block
Top Boot Location
40-Lead TSOP
44-Lead PSOP
40-Lead PDIP
Hardware Data Protection Feature
Erase/Write Lockout during Power
Transitions
ETOX™ IV Flash Technology
5V Read
Absolute Hardware Protection for
Boot Block
12V Write and Block Erase
VPP = 12V ±5% Standard
VPP = 12V ±10% Option
Software EEPROM Emulation with
Parameter Blocks
Independent Software Vendor Support
Intel’s 2-Mbit flash memory is an extension of the Boot Block architecture which includes block-selective
erasure, automated write and erase operations, and a standard microprocessor interface. The 2-Mbit flash
memory enhances the Boot Block architecture by adding more density and blocks, x8 input/output control,
very high-speed, low-power, and industry-standard ROM-compatible pinout and surface mount packaging.
The Intel 28F002BC is an 8-bit wide flash memory offering. This high-density flash memory provides user-
selectable bus operation for 8-bit applications. The 28F002BC is a 2,097,152-bit nonvolatile memory
organized as 262,144 bytes of information. It is offered in 44-lead PSOP, 40- lead PDIP and 40-lead TSOP
package, which is ideal for space-constrained portable systems or any application with board space
limitations.
This device uses an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
byte write and block erasure. The 28F002BC provides block locations compatible with Intel’s MCS®-186
family, 80286, 90860CA, and the Intel386™, Intel486™, Pentium®, and Pentium Pro microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 80 ns, this high-performance 2-Mbit flash memory interfaces at zero wait-state to a
wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total VCC power
consumption to 1 µW typical. This power savings is critical in hand-held battery powered systems. For very
low-power applications using a 3.3V supply, refer to the Intel 28F002BV-T/B 2-Mbit SmartVoltage Boot Block
Flash Memory datasheet. Manufactured on Intel’s 0.6 micron ETOX™ IV process technology, the 28F002BC
flash memory provides world-class quality, reliability, and cost-effectiveness at the 2-Mbit density.
October 1996
Order Number: 290578-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F002BC may contain design defects or errors known as errata. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
1.0 INTRODUCTION .............................................5
1.1 Designing for Density Upgradeability............5
1.2 Main Features..............................................5
1.3 Applications..................................................6
1.4 Pinouts.........................................................7
1.5 Pin Descriptions .........................................10
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
CONTENTS
PAGE
PAGE
3.4 Boot Block Locking.....................................19
3.4.1 VPP = VIL for Complete Protection........19
3.4.2 RP# = VHH for Boot Block Unlocking....19
3.5 Power Consumption...................................23
3.5.1 Active Power .......................................23
3.5.2 Standby Power ....................................23
3.5.3 Deep Power-Down...............................23
3.6 Power-Up/Down Operation.........................23
3.6.1 RP# Connected to System Reset ........23
3.6.2 VCC, VPP and RP# Transitions .............23
3.7 Power Supply Decoupling ..........................24
3.7.1 VPP Trace on Printed Circuit Boards....24
2.0 PRODUCT DESCRIPTION............................11
2.1 Memory Organization.................................12
2.1.1 Blocking...............................................12
2.1.2 28F002BC-T Block Memory Map.........12
3.0 PRINCIPLES OF OPERATION .....................12
3.1 Bus Operations ..........................................13
3.2 Read Operations........................................13
3.2.1 Read Array..........................................13
3.2.2 Intelligent Identifiers ............................14
3.3 Write Operations ........................................14
3.3.1 Command User Interface (CUI) ...........14
3.3.2 Status Register....................................17
3.3.3 Program Mode.....................................17
3.3.4 Erase Mode.........................................18
3.3.5 Extended Cycling ................................19
4.0 ELECTRICAL SPECIFICATIONS..................25
4.1 Absolute Maximum Ratings........................25
4.2 Operating Conditions..................................25
4.2.1 Capacitance.........................................26
4.2.2 Input/Output Test Conditions ...............26
4.2.3 DC Characteristics...............................27
4.2.4 AC Characteristics...............................29
APPENDIX A: Ordering Information .................35
APPENDIX B:WSM Transition Table.................36
APPENDIX C: Additional Information...............37
3
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
REVISION HISTORY
Number
-001
Item
Original version
-002
Pin 2 of 44-Lead PSOP changed from DU to NC
Alternate program command (10H) removed
WSM transition table added
-003
40-Lead PDIP package added
4
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
1.2 Main Features
1.0 INTRODUCTION
The 28F002BC Boot Block flash memory is a high-
performance, 2-Mbit (2,097,152 bit) flash memory
organized as 256 Kbytes (262,144 bytes) of 8 bits
each.
This datasheet comprises the specifications for
the 28F002BC 2-Mbit flash memory. Section 1
provides an overview of the 2-Mbit flash memory,
including
applications,
pinouts,
and
pin
descriptions. Section 2 describes the memory
organization in detail. Section defines
description of the memory’s principles of
operation. Finally, Section 4 details the memory’s
operating specifications.
The 28F002BC has separately erasable blocks,
including a hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes each)
and two main blocks (one block of 98,304 bytes
and one block of 131,072 bytes). An erase
operation typically erases one of the main blocks
in 2.4 seconds and the boot or parameter blocks in
1.0 second. Each block can be independently
erased and programmed 100,000 times.
3
a
1.1
Designing for Density
Upgradeability
The 28F002BC has been optimized to meet
market requirements. Applications currently using
the 28F001BX and 28F002BX can migrate to this
product. Of course, both the 28F001BX and the
28F002BX devices use an 8-bit wide bus. Those
applications needing a 16-bit wide bus or lower
The boot block is located at the top of the address
map to match the protocol of many systems,
including Intel’s MCS-186 family, 80960CA, i860™
microprocessors as well as Pentium and Pentium
Pro microprocessors. The hardware-lockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code
required for booting-up a system. When the RP#
pin is between 11.4V and 12.6V, the boot block is
unlocked and program and erase operations can
be performed. When the RP# pin is at or below
6.5V, the boot block is locked and program and
erase operations to the boot block are ignored.
voltage can convert to the Smart
5
or
SmartVoltage family of flash memory products.
SmartVoltage is also the natural migration path to
the 4-Mbit density. Both the 28F002BC and the
4-Mbit SmartVoltage are offered in identical
packages to make upgrade seamless. A few
simple considerations can smooth the migration
path significantly:
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
28F002BC.
1. Connect the NC pin of the 28F002BC to GND
(this will retain boot block locking when a
4-Mbit SmartVoltage is inserted).
Program and Erase Automation allows program
and erase operations to be executed using an
industry standard two-write command sequence to
the CUI. Data writes are performed in byte
increments. Each byte in the flash memory can be
programmed independently of other memory
locations but is erased simultaneously with all
other locations within the block.
2. Design a switchable VPP to take advantage of
the 5V VPP option on SmartVoltage devices.
3. If anticipating to use the 5V VPP option,
switch VPP to GND for complete write
protection.
Previous designs with Intel’s 28F002BX devices
on occasion had to use a NOR gate (or some
other scheme) to prevent issues with floating
addresses latching incorrect data. The 28F002BC
has corrected this issue and does not need the
NOR gate. When migrating a design using the
28F002BX to the 28F002BC, the NOR gate can be
removed. When considering upgrading, packaging
is of paramount importance. Current and future
market trends indicate TSOP and PSOP as the
packages that will enable designs into the next
century.
The status register (SR) indicates the status of the
internal Write State Machine (WSM), which reports
critical information on program and/or erase
sequences.
The maximum access time of 80 ns (tACC) is
guaranteed over the commercial temperature
range (0°C to +70°C), 10% VCC supply voltage
range (4.5V to 5.5V) and 100 pF output load.
5
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Host
Bus
PCI
Bus
ISA
Bus
X-Bus
A[16:0]
Main
Memory
CE#
Pentium®
Processor
100/90 MHz
7 B
4 U
S F
2 F
4 E
5 R
82430FX
PCIset
(82371FB)
82430FX
PCIset
(82437FX)
OE#
Intel
28F002BC
WE#
X
M
E
M
W
#
X
M
E
M
R
#
RP#
Cache
DQ[7:0]
PWROK
Vpp
J1
XDIRXOE#
0578_01
Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System
I
PP, the maximum program current, is 20 mA. The
automation and RP# functionality for data
protection, the device is protected against
unwanted program and/or erase cycles, even
during system reset.
VPP voltage for erase and program is 11.4V to
12.6V (VPP = 12V ± 5%) under all operating
conditions. Typical ICC active current is 20 mA.
The 28F002BC flash memory is also designed with
a standby mode to minimize system current drain
and allow for low-power designs. When the CE#
and RP# pins are at VCC, the CMOS standby mode
is enabled and ICC drops to about 50 µA.
1.3
Applications
2-Mbit Boot Block flash memory combines high
density, high performance, and cost-effective flash
memory with blocking and hardware protection
capabilities. Its flexibility and versatility reduces
cost throughout the product life cycle. Flash
memory is ideal for Just-In-Time production flow,
reducing system inventory and costs, and
eliminating component handling during the
production phase. During a product’s life cycle,
flash memory reduces costs by allowing user-
performed code updates and feature enhancements
via floppy disk or remote link.
A deep power-down mode is enabled when the RP#
pin is at ground. In addition to minimizing power
consumption, the deep power-down mode also
provides write protection during power-up
conditions. ICC current during deep power-down
mode is 0.20 µA typical. An initial maximum access
time or reset time of 300 ns is required from RP#
switching high until outputs are valid. Equivalently,
the device has a maximum wake-up time of 215 ns
until writes to the CUI are recognized.
The 28F002BC is a full-function blocked flash
product suitable for a wide range of applications,
including extended PC BIOS, digital cellular phone
program and data storage, telecommunication
boot/firmware, and various embedded applications
where both program and data storage are required.
When RP# is at ground, the WSM is reset, the
status register is cleared, and the entire device is
write-protected. This feature prevents data
corruption and protects the code stored in the
device during system reset. The system Reset pin
can be tied to RP# to reset the memory to read
mode at power-up. With on-chip program/erase
6
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Reprogrammable systems, such as personal
computers, are ideal applications for the
28F002BC. Portable and hand-held personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor
technology, the availability of ROM-based
application software, pen tablet code for electronic
handwriting, and diagnostic code. Figure 1 shows
an example 28F002BC application.
The 28F002BC is also an excellent design solution
for analog and digital cellular phone and
telecommunication switching applications requiring
high-performance, high-density storage in a small
form factor package (x8-only bus). The blocking
structure allows for easy segmentation of
embedded code for modular software designs. For
example, the parameter block can be used for
frequently updated data storage and diagnostic
messages (e.g., phone numbers and authorization
codes).
The increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 28F002BC provides a
safe and inexpensive update solution for desktop,
notebook, and hand-held personal computers while
extending the product lifetime. Furthermore, the
deep power-down mode provides added flexibility
for those battery-operated portable designs that
require low power.
1.4
Pinouts
The 28F002BC in the 44-lead PSOP pinout follows
the industry-standard ROM/EPROM pinout, as
shown in Figure 4. The 2-Mbit SmartVoltage pinout,
indicating the WP# input, is also shown in the same
diagram. The 40-lead TSOP package (shown in
Figure 2) offers the smallest form factor possible in
addition to being compatible with its SmartVoltage
upgrade in the same package. The low-cost 40-lead
PDIP package diagram is shown in Figure 3.
28F002BV
28F002BV
A
A
17
A
A
A
A
A
A
A
A
WE#
A
A
A
A
A
A
A
A
WE#
RP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
17
GND GND
16
15
14
16
15
14
13
12
11
NC
NC
NC
NC
13
12
11
A
A
10
10
DQ
DQ
DQ
DQ
DQ
DQ
7
6
5
4
7
6
5
4
E28F002BC
BOOT BLOCK
40-LEAD TSOP
10 mm x 20 mm
TOP VIEW
9
8
9
8
DQ
V
DQ
V
RP#
CC
CC
V
V
NC
NC
V
CC
V
CC
PP
PP
WP#
NC
A
A
6
A
A
4
A
A
2
A
NC
NC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
3
2
1
0
3
2
1
0
A
A
6
A
A
4
A
A
2
A
7
7
5
5
OE#
GND GND
CE#
OE#
3
3
CE#
A
A
1
0
0
1
0578_02
Figure 2. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
7
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
NC
NC
1
2
40
39
NC
A1
A0
A2
3
38
A3
A4
A5
CE#
GND
OE#
DQ0
DQ1
DQ2
4
5
6
7
8
9
37
36
35
34
33
32
P28F002BC
BOOT BLOCK
40-LEAD PDIP
A6
A7
VPP
DQ3
VCC
VCC
10
11
12
31
30
29
RP#
WE#
A8
A9
DQ 4
DQ 5
DQ 6
DQ 7
13
14
15
16
28
27
26
25
A 11
A12
A13
A10
GND
A17
A14
A15
A16
17
18
19
20
24
23
22
21
NC
NC
0578_3A
Figure 3. The 40-Lead PDIP Offers the Lowest Cost Package Solution
8
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
28F200BV
28F200BV
VPP
NC
NC
VPP
WP#
NC
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
RP# RP#
WE# WE#
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
8
8
A
A
7
7
9
9
A
6
A
6
10
11
12
13
14
15
10
11
12
13
14
15
A
A
4
A
5
5
A
4
PA28F002BC
BOOT BLOCK
44-Lead PSOP
0.525" x 1.110"
A
A
3
3
A
2
A
2
A
A
10
1
1
A
0
A
0
A
A
11
12
13
14
15
16
34
33
32
31
30
29
16
16
CE#
GND
OE#
DQ
DQ
8
CE#
GND
OE#
DQ
NC
NC
NC
TOP VIEW
GND
DQ /A
DQ
DQ
GND
A
-1
15 -1
DQ
7
0
7
0
NC
14
DQ
DQ
DQ
DQ
DQ
9
DQ
DQ
10
DQ
NC
DQ
NC
17
18
19
20
28
27
26
25
1
6
6
1
NC
DQ
13
DQ
DQ
5
5
2
2
NC
12
DQ
4
DQ
V
DQ
DQ
11
DQ
21
22
24
23
3
4
3
V
NC
CC
CC
0578_03
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
9
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
1.5 Pin Descriptions
E
Table 1. 28F002BC Pin Descriptions
Symbol
A–1
Type
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. A-1 is used on the PSOP package only. A17 is used on the
TSOP and PDIP packages.
,
INPUT
A0–A17
A9
INPUT
ADDRESS INPUT: When A9 is at VHH, the signature mode is accessed. During
this mode, A0 decodes between the manufacturer and device IDs.
DQ0–
DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE#
cycle during a program operation. Inputs commands to the Command User
Interface when CE# and WE# are active. Data is internally latched during the
write cycle. Outputs array, Intelligent Identifier and Status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high deselects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the
WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in
deep power-down mode, locks, and unlocks the boot block from program/erase.
When RP# is at logic high level (6.5V maximum), the boot block is locked and
cannot be programmed or erased.
When RP# = VHH (11.4V minimum ), the boot block is unlocked and can be
programmed or erased.
When RP# is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset—preventing any blocks from being
programmed or erased. When RP# transitions from logic low to logic high, the
flash memory enters the read array mode.
VCC
VPP
DEVICE POWER SUPPLY: 5.0V ± 10%, 5.0V ± 5%
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block. When VPP < VPPLK all blocks are locked and
memory contents cannot be altered.
GND
NC
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
10
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
2.0 PRODUCT DESCRIPTION
DQ -DQ
0
7
Input
Buffer
Output
Buffer
I/O Logic
Identifier
Register
Status
Register
CE#
WE#
OE#
RP#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
A
-A
17
0
Input
Y-Gating/Sensing
Buffer
Y-Decoder
X-Decoder
Write State
Machine
Program/Erase
Voltage Switch
V
PP
Address
Latch
V
CC
GND
Address
Counter
044819
Figure 5. 28F002BC Internal Block Diagram
11
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
2.1.1.2
Parameter Blocks - 8 KB (each)
2.1
Memory Organization
The 28F002BC has two 8-Kbyte parameter blocks
to facilitate storage of frequently updated system
parameters that would normally require an
EEPROM. The parameter blocks can also be used
to store additional boot or main code. By using
software techniques, the byte-rewrite functionality
of EEPROMs can be emulated. These techniques
are detailed in Intel’s application note AP-604 Using
Intel’s Boot Block Flash Memory Parameter Blocks
to Replace EEPROM.
2.1.1
BLOCKING
The 28F002BC features an asymmetrically-blocked
architecture that provides system memory
integration. Each block can be erased up to
100,000 times. The block sizes have been chosen
to optimize their functionality for common
applications of nonvolatile storage. For the address
locations of the blocks, see the memory map in
Figure 6.
2.1.1.3
Main Block - 96 KB and 128 KB
2.1.1.1
Boot Block - 16 KB
The 28F002BC contains one 96-Kbyte (98,304
byte) block and one 128-Kbyte (131,072 byte)
block. These blocks are typically used for data or
code storage.
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at the top of the address map as
shown in Figure 6. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
erasure. The boot block can be erased and written
when RP# is held at 12V for the duration of the
erase or program operation. This feature allows
customers to change the boot code when
necessary while providing security at other times.
2.1.2
28F002BC-T BLOCK MEMORY MAP
The 16-Kbyte boot block of the 28F002BC-T is
located from 3C000H to 3FFFFH. The first 8-Kbyte
parameter block resides in memory space from
3A000H to 3BFFFH. The second 8-Kbyte
parameter block consumes the memory area from
38000H to 39FFFH. The 96-Kbyte main block
extends from 20000H to 37FFFH, while the
128-Kbyte main block occupies the region from
00000H to 1FFFFH.
28F002BC-T
3FFFFH
16-Kbyte Boot Block
3C000H
3.0 PRINCIPLES OF OPERATION
3BFFFH
8-Kbyte Parameter Block
Flash memory improves upon EPROM capability
with in-circuit electrical write and erase. The Boot
Block flash memory utilizes a Command User
Interface (CUI) and automated algorithms to
simplify write and erase operations. The CUI allows
for 100% TTL-level control inputs, fixed power
supplies during erasure and programming, and
maximum EPROM compatibility.
3A000H
39FFFH
8-Kbyte Parameter Block
38000H
37FFFH
96-Kbyte Main Block
20000H
1FFFFH
128-Kbyte Main Block
00000H
0578_05
When VPP < VPPLK, the device will only successfully
execute the following commands: Read Array,
Read Status register, Clear Status register, and
Intelligent Identifier. The device provides standard
EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the CUI
or through the standard EPROM A9 high voltage
(VID) access for PROM programming equipment.
High voltage on VPP allows write and erase of the
device. With VPP active, all functions associated
Figure 6. 28F002BC-T Memory Map
12
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
3.2.1 READ ARRAY
with altering memory contents are accessible via
the CUI.
When RP# transitions from VIL (reset) to VIH, the
device will be in read array mode and will respond
to the read control inputs (CE#, OE#, and address
inputs) without any commands being written to the
CUI.
The purpose of the Write State Machine (WSM) is
to automate the write and erasure of the device
completely. The WSM will begin operation upon
receipt of a signal from the CUI and will report
status back through the status register. The CUI will
handle the WE# interface to the data and address
latches, as well as system software requests for
status while the WSM is in operation.
When the device is in read array mode, four control
signals must be manipulated to read data at the
outputs.
•
•
•
•
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
3.1
Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in
Tables 2 and 4.
In addition, the address of the desired location must
be applied to the address pins. Refer to AC
Characteristics for the exact sequence and timing
of these signals.
3.2
Read Operations
If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to the
CUI before array reads can take place.
The 28F002BC has three user read modes: read
array, read intelligent identifier, and read status
register.
During power-up conditions, it takes a maximum of
600 ns from when VCC is at 4.5V to when valid data
is available at the outputs.
Table 2. 28F002BC Bus Operations
Mode
Notes RP#
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIH
X
A9
X
A0
X
VPP
X
DQ0–7
DOUT
High Z
High Z
High Z
89H
Read
1,2,3
VIH
VIH
VIH
VIL
VIH
VIH
VIH
Output Disable
X
X
X
Standby
X
X
X
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
8
4
X
X
X
X
X
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VID
VID
X
VIL
VIH
X
X
4
X
7CH
5,6,7
VPPH
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP
.
3. See DC Characteristics for VPPLK, VPPH, VHH, VID voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A -A17 = X.
1
5. Refer to Table 3 for valid DIN during a write operation.
6. Command writes for program or block erase are only executed when VPP = VPPH
.
7. To write or erase the boot block, hold RP# at VHH
.
8. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
13
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
3.2.2 INTELLIGENT IDENTIFIERS 3.3.1
E
COMMAND USER INTERFACE (CUI)
The manufacturer and device codes are read via
the CUI or by taking the A9 pin to VID. Writing 90H
to the CUI places the device into Intelligent
Identifier read mode. A read of location 00000H
outputs the manufacturer’s identification code, 89H.
Reading location 00001H outputs the device ID,
7CH.
The Command User Interface (CUI) serves as the
interface between the microprocessor and the
internal chip controller. Commands are written to
the CUI using standard microprocessor write
timings. The available commands (summarized in
Tables 3 and 4) are Read Array, Read Intelligent
Identifier, Read Status Register, Clear Status
Register, Program Setup, Erase Setup/Confirm,
and Erase Suspend.
The 28F002BC device ID of 7CH is identical to the
E28F002BX (40-lead TSOP). It differs from the
PA28F200BX (44-lead PSOP), which has a device
ID of 2274H. Designers using the PA28F200BX in
the x8 mode who wish to migrate to the
PA28F002BC need to be mindful of this device ID
difference and modify software drivers as
necessary. The 40-lead PDIP device ID is 7CH.
For Read commands, the CUI points the read path
at either the array, the intelligent identifier, or the
status register depending on the command
received. For Program or Erase commands, the
CUI informs the Write State Machine (WSM) that a
Program or Erase has been requested. During the
execution of
a Program command, the WSM
controls the programming sequences and the CUI
responds only to status register reads. During an
erase cycle, the CUI responds only to status
register reads and Erase Suspend. After the WSM
has completed its task, it will set the WSM Status
bit (bit 7 of the status register) to a “1,” which will
also allow the CUI to respond to its full command
set. Note that after the WSM has returned control to
the CUI, the CUI will stay in the read status register
mode until it receives another command (see
Appendix B).
3.3
Write Operations
There are two commands that alter memory array
contents: Program Setup and Erase Setup/Confirm.
In addition, the Erase Suspend command suspends
the WSM during an erase operation and releases
the CUI to accept any Read command (so long as it
is to a block other than the one being erased).
Finally, there is a Clear Status Register command
for resetting the contents of the status register. This
command should be invoked following all
operations that modify the status register.
Table 3. Command Set Codes and
Corresponding Device Mode
Command Codes
Device Mode
Invalid/Reserved
All commands written to the CUI will be interpreted,
but for any write operation to be initiated, the VPP
00
20
40
50
70
90
B0
D0
FF
voltage must be at VHH. Depending on the
application, the design may have a switchable VPP
power supply or the VPP may be “hard-wired” to
12V. The 28F002BC will function normally in either
case. It is highly recommended that RP# is tied to
the system RESET for data protection during
unstable CPU reset and also for proper CPU / flash
synchronization.
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Furthermore, when attempting to modify the
contents of the 28F002BC’s boot block area, VHH
must be applied to both VPP and RP# for the
operation to be valid. Whether attempting to alter
the contents of the boot block or any other memory
array area, if the proper voltages are not applied to
the correct input signals the write operation will be
aborted. Subsequently, the status register will
respond with either Bit 3 (VPP low error), Bit 4
(program error) or Bit 5 (erase error) being set (refer
to Table 5 for status register definitions).
Erase Resume/Erase Confirm
Read Array
14
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Table 4. Command Bus Definitions
First Bus Cycle
Addr
Second Bus Cycle
Command
Notes
Oper
Write
Write
Write
Write
Write
Write
Write
Data
FFH
90H
70H
50H
40H
20H
B0H
Oper
Addr
Data
Read Array
X
X
Intelligent Identifier
Read Status Register
Clear Status Register
Program Setup
1,2
Read
Read
IA
X
IID
X
SRD
X
PA
BA
X
Write
Write
Write
PA
BA
X
PD
Block Erase/Confirm
Erase Suspend/Resume
D0H
D0H
ADDRESS
DATA
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
SRD = Status Register Data
IID = Intelligent Identifier Data
PD = Program Data
NOTES:
1. Bus operations are defined in Table 2.
2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes respectively.
3.3.1.1
Command Function Description
will output status register contents. Writing two
Read Array (FFH) commands to the CUI aborts the
current operation and resets to read array mode.
Device operations are selected by writing specific
commands into the CUI. Tables 3 and 4 define the
available commands. Status Register (SR) bits are
defined in Table 5.
Executing Read Array after the Erase Setup
command (instead of giving Erase Confirm) causes
the status register Erase and Program Status bits to
be set. This indicates that an erase operation was
initiated but not successfully confirmed (an Erase
Confirm at this point would be ignored by the CUI).
A subsequent Read Array command will point the
data path at the array (see Appendix B).
Invalid/Reserved
These are unassigned commands and should not
be used. Intel reserves the right to redefine these
codes for future functions.
Intelligent Identifier (90H)
Read Array (FFH)
After this command is executed, the CUI points the
output path to the intelligent identifier circuits. Only
intelligent identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode; all
other address inputs are ignored).
This single write cycle command points the read
path at the array. If the host CPU performs a
CE#/OE#-controlled Read immediately following a
two-write sequence (i.e.,
a Program or Erase
command) that started the WSM, then the device
15
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Read Status Register (70H)
Erase Setup (20H)
This is one of three commands that is executable
while the WSM is operating. After this command is
written, a read of the device will output the contents
of the status register, regardless of the address
presented to the device. The device automatically
enters this mode after program or erase has
completed.
The Erase Setup command prepares the CUI for
the Erase Confirm command. No other action is
taken. If the next command is not an Erase Confirm
command, then the CUI will set both the Program
Status and Erase Status bits of the status register
to a “1,” place the device into read status register
mode, and wait for another command.
Clear Status Register (50H)
Erase Confirm (D0H)
The WSM can set the Program Status and Erase
Status bits in the status register to “1,” but it cannot
clear them to “0.”
If the previous command was an Erase Setup
command, then the CUI will enable the WSM to
erase, at the same time closing the address and
data latches, and respond only to the Read Status
Register and Erase Suspend commands. While the
WSM is executing, the device will output status
register data when OE# is toggled low. Status
register data can only be updated by toggling either
OE# or CE#. If the previous command was not the
Erase Setup command (20H), the Erase Confirm
command is ignored. Status Register bits 4 and 5
are both set to indicate an invalid command
sequence.
The status register is operated in this fashion for
two reasons, the first is synchronization. Since the
WSM does not know when the host CPU has read
the status register, it would not know when to clear
the status bits. Second, if the CPU is programming
a string of bytes, it may be more efficient to query
the status register after programming the string.
Thus, if any errors exist while programming the
string, the status register will return the
accumulated error status. The Clear Status
Register command clears the Program, Erase, and
Erase Suspend (B0H)
V
PP Status bits to “0.”
This command is only valid while the WSM is
executing an erase operation. At all other times,
this command is ignored. After this command has
been executed, the CUI will set a signal that directs
the WSM to suspend erase operations. While
waiting for the erase to be suspended, the CUI
responds only to the Read Status Register
command or to the Erase Resume command. Once
the WSM has reached the Suspend state, it will set
an output in the CUI that allows the CUI to respond
to the Read Array, Read Status Register, and Erase
Resume commands. In this mode, the CUI will not
respond to any other commands. The WSM will
also set the WSM and Erase Suspend status bits to
a “1.” The WSM will continue to run, idling in the
Suspend state, regardless of the state of all input
control pins except VPP and RP#. If VPP is taken
below VPPLK, the VPP low status bit (SR.3) will be
set and the WSM will abort the suspended erase
operation. If active, RP# will immediately shut down
the WSM and the remainder of the chip. During a
suspend operation, the data and address latches
will remain closed, but the address pads are able to
drive the address into the read path.
Program Setup (40H)
This command simply sets the CUI into a state
such that the next write will load the Address and
Data registers. After this command is executed, the
outputs default to the status register. Two
consecutive Read Array commands (FFH) are
required to reset to Read Array after the Program
Setup command.
Program
The write following the Program Setup command
will latch address and data. Also, the CUI initiates
the WSM to begin execution of the program
algorithm. The device outputs status register data
when OE# is enabled. To read array data after the
program operation is completed, a Read Array
command is required.
16
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Erase Resume (D0H)
written to the CUI. Then, any other command may
be issued to the CUI. Note, again, that before a
This command will cause the CUI to clear the
Suspend state and clear the WSM Status Bit to a
“0,” but only if an Erase Suspend command was
previously issued. Erase Resume will not have any
effect under any other conditions.
read cycle can be initiated, a valid read command
must be written to the CUI to specify whether the
read data is to come from the memory array, status
register, or intelligent identifier.
3.3.3
PROGRAM MODE
3.3.2
STATUS REGISTER
Programming is executed using
a
two-write
The 28F002BC contains a status register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The status register may be
read at any time by writing the Read Status
Register command to the CUI. After writing this
command, all subsequent read operations output
data from the status register until another command
is written to the CUI. A Read Array command must
be written to the CUI to return to read array mode.
The status register bits are output on DQ[0:7]. The
contents of the status register are latched on
the falling edge of OE# or CE#, whichever
occurs last in the read cycle. This prevents
possible bus errors that might occur if the contents
of the status register change while reading the
status register. CE# or OE# must be toggled with
each subsequent status read to insure the status
register is updated; otherwise, the completion of a
program or erase operation will not be evident from
the status register.
sequence. The Program Setup command is written
to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM then executes a sequence of internally-
timed events to:
1. Program the desired bits of the addressed
memory byte.
2. Verify that the desired bits are sufficiently
programmed.
Programming of the memory results in specific bits
within a byte being changed to a “0.”
If the user attempts to program “1”s, there will be no
change in memory contents and no error is reported
by the status register.
Similar to erasure, the status register indicates
whether programming is complete. While the
program sequence is executing, bit 7 of the status
register is a “0.” The status register can be polled
by toggling either CE# or OE# to determine when
the program sequence is complete. Only the Read
Status Register command is valid while
programming is active.
When the WSM is active, the status register will
indicate the status of the WSM and upon command
completion, it will indicate success or failure of the
operation (see Table 5 for definition of status
register bits).
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, bit 4 of the status
register is set to a “1” to indicate a program failure.
3.3.2.1
Clearing the Status Register
The WSM sets status bits “3” through “7” to “1,” and
clears bits “6” and “7” to “0,” but cannot clear status
bits “3” through “5” to “0.” Bits 3 through 5 can only
be cleared by the controlling CPU through the use
of the Clear Status Register command. These bits
can indicate various error conditions. By allowing
the system software to control the resetting of these
bits, several operations may be performed (such as
cumulatively programming several bytes or erasing
multiple blocks in sequence). The status register
may then be read to determine if an error occurred
during that programming or erasure series. This
feature adds flexibility to the way the device may be
programmed or erased. To clear the status register,
If bit 3 is set to a “1,” then VPP
was not within
acceptable limits, and the WSM did not execute the
programming sequence. If the program operation
fails, bit 4 of the status register will be set within
1.5 ms, as determined by the timeout of the WSM.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, reads from the memory array cannot be
accomplished until the CUI is given the Read Array
command. Figure
7
shows the Automated
the
Clear
Status
Register
command
is
Programming Flowchart.
17
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Table 5. Status Register Bit Definition
WSMS
7
ESS
6
ES
5
DWS
4
VPPS
3
R
2
R
1
R
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS) The Write State Machine bit must first be checked to
1 = Ready
0 = Busy
determine program or Block Erase completion,
before the Program or Erase Status bits are checked
for success.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
When Erase Suspend is issued, the WSM halts
execution and sets both the WSMS and ESS bits to
“1.” The ESS bit remains set to “1” until an Erase
Resume command is issued.
0 = Erase In Progress/Completed
SR.5 = ERASE STATUS
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” the WSM has applied the
maximum number of erase pulses to the block and is
still unable to successfully verify block erasure.
SR.4 = PROGRAM STATUS
1 = Error in Byte Program
0 = Successful Byte Program
When this bit is set to “1,” the WSM has attempted
but failed to program a byte.
SR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP Status bit, unlike an A/D converter, does not
provide continuous indication of VPP level, but it does
check the VPP level intermittently. The WSM
interrogates VPP level only after the program or
erase command sequences have been entered, and
informs the system if VPP has not been switched on.
If VPP ever goes below VPPLK (even during an Erase
, the status register will set this bit and
Suspend)
abort the operation in progress, even if VPP is
returned to a valid level. The VPP Status bit is not
guaranteed to report accurate feedback between
V
PPLK and VPPH.
SR.2–SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the status register.
3.3.4
ERASE MODE
The WSM then executes a sequence of internally
timed events to:
Erase Setup and Erase Confirm commands to the
CUI, along with the address identifying the block to
be erased. This address is latched internally when
the Erase Confirm command is issued. Block
erasure results in all bits within the block being set
to “1.”
1. Program all bits within the block to “0.”
2. Verify that all bits within the block are
sufficiently programmed to “0.”
3. Erase all bits within the block (set all bits to “1”).
4. Verify that all bits within the block are
sufficiently erased.
If the Erase Confirm command does not follow the
Erase Setup command, the status register
responds by setting both SR.4 and SR.5 to “1” to
indicate an invalid command sequence. The WSM
returns to read status register mode.
While the erase sequence is executing, bit 7 of the
status register is a “0.”
18
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
When the status register indicates that erasure is
complete, the status bits, which indicate whether
the erase operation was successful, should be
checked. If the erase operation was unsuccessful,
bit 5 of the status register will be set (within 1.5 ms)
to “1,” indicating an erase failure. If VPP is not within
acceptable during the suspended period, the WSM
does not execute the erase sequence; instead, bit 5
of the status register is set to a “1” to indicate an
Erase Failure, and bit 3 is set to a “1” to indicate
that the VPP supply voltage was outside acceptable
limits.
erase sequence and finish erasing the block. As
with the end of a standard erase operation, the
status register must be read, cleared, and the next
instruction issued in order to continue. Figure 9
highlights the Erase Suspend/Resume Flowchart.
3.3.5
EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX IV flash memory technology. The
28F002BC flash memory is designed for 100,000
program/erase cycles on each of the five blocks. At
10% VPP, the parameter blocks are capable of
10,000 program/erase cycles. The combination of
low electric fields, clean oxide processing and
minimized oxide area per memory cell subjected to
the tunneling electric field results in very high
cycling capability.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after erasure is completed; however,
reads from the memory array cannot be
accomplished until the CUI is given the Read Array
command. Figure 8 details the Automated Block
Erase Flowchart.
3.4
Boot Block Locking
3.3.4.1
Suspending and Resuming Erase
The Boot Block memory architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks.
Since an erase operation may take a few seconds
to complete, an Erase Suspend command is
provided. This allows erase-sequence interruption
in order to read data from another block of the
memory array. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM pause the erase sequence
at a predetermined point in the erase algorithm. The
status register must then be read to determine if the
erase operation has been suspended. Taking VPP
below VPPLK latches the VPP low status and aborts
the operation in progress. VPP should be main-
tained at valid levels, even during Erase Suspend.
3.4.1
V
PP = VIL FOR COMPLETE
PROTECTION
For complete write protection of all blocks in the
flash device, the VPP programming voltage can be
held low. When VPP is below VPPLK, any program or
erase operation will cause the device to set an error
bit in the status register.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that being erased. The only other valid
commands at this time are Erase Resume and
Read Status Register.
3.4.2
RP# = VHH FOR BOOT BLOCK
UNLOCKING
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH, which
reduces active current draw.
In the case of boot block modifications (write and
erase), RP# and VPP are set to VHH (12V).
However, if RP# is not at VHH when a program or
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for status
register definitions) is set to indicate the failure to
complete the specified operation.
To resume the erase operation, the chip must be
enabled by taking CE# to VIL, then issuing the
Erase Resume command. When the Erase Resume
command is given, the WSM will continue with the
19
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Data = 40H
Start
Bus
Comments
Command
Operation
Write
Program
Setup
Write 40H and
Addr = Byte to Program
Byte Address
Write
Data = Data to Program
Program
Addr = Location to Program
Write Data and
Data Address
Read
Status Register Data
Toggle CE# or OE# to Update SRD.
Read
Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
SR.7 = 1
Repeat for subsequent writes.
SR Full Status Check can be done after each write, or after
a sequence of writes.
Write FFH after the last write operation to reset device to
read array mode.
?
Yes
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus
Operation
Comments
Command
Standby
Standby
Check SR.3
1 = V Low Detect
PP
1
V
Range Error
SR.3 =
0
PP
Check SR.4
1 = Program Error
1
Program Error
SR.4 =
0
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.4 is only cleared by the Clear Status Register command, in cases
where multiple bytes are programmed before full status is checked.
Program Successful
If error is detected, clear the status register before attempting retry
or other error recovery.
0578_06
Figure 7. Automated Programming Flowchart
20
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Start
Bus
Command
Comments
Operation
Write
Write
Erase Setup
Data = 20H
Addr = Within Block to Be Erased
Write 20H and
Block Address
Erase
Confirm
Data = D0H
Addr = Within Block to Be Erased
Write D0H and
Block Address
Read
Status Register Data
Toggle CE# or OE# to Update
Status Register
Read Status Register
Suspend Erase
Loop
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
0
Yes
Suspend
Erase
SR.7 =
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
1
Write FFH after the last operation to reset device to read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Read Status Register
Data (See Above)
Standby
Standby
Check SR.3
1 = V Low Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.4,5
Both 1 = Command
Sequence Error
1
1
Standby
Command Sequence
Error
Check SR.5
1 = Block Erase Error
SR.4,5 =
0
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
Block Erase
Error
SR.5 =
0
SR.5 is only cleared by the Clear Status Register command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Block Erase
Successful
0578_07
Figure 8. Automated Block Erase Flowchart
21
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Start
Bus
Command
Comments
Operation
Write
Read
Erase
Suspend
Data = B0H
Addr = X
Write B0H
Status Register Data
Toggle CE# or OE#
to Update SRD.
Addr = X
Read Status Register
Standby
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Check SR.6
1 = Erase Suspended
0 = Erase Completed
1
Write
Read
Read Array
Data = FFH
Addr = X
0
Erase Completed
SR.6 =
Read Array Data from Block
Other Than the One Being
Erased
1
Write
Erase Resume
Data = D0H
Addr = X
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
0578_08
Figure 9. Erase Suspend/Resume Flowchart
22
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
is reset to the read mode after power-up, but the
system must drop CE# low or present a new
address to ensure valid data at the outputs.
3.5
Power Consumption
3.5.1
ACTIVE POWER
A system designer must guard against spurious
With CE# at a logic-low level and RP# at a logic-
high level, the device is placed in the active mode.
The device ICC current is a maximum of 60 mA at
10 MHz with TTL input signals.
writes when VCC voltages are above VLKO and VPP
= VHH. Since both WE# and CE# must be low for a
command write, driving either signal to VIH will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to
system PowerGood/Reset) during power up/down,
invalid bus conditions during power-up can be
masked, providing yet another level of memory
protection.
3.5.2
STANDBY POWER
With CE# at a logic-high level (VIH), the memory is
placed in standby mode, where the maximum ICC
standby current is 100 µA. The standby operation
disables much of the device’s circuitry and
substantially reduces device power consumption.
The outputs (DQ[0:7]) are placed in
a high-
impedance state independent of the status of the
OE# signal. When CE# is at a logic-high level
during erase or program, the device will continue to
perform the erase or program function and
consume erase or program active power until erase
or program is completed.
3.6.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated write/erase devices because the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
3.5.3
DEEP POWER-DOWN
without
a
flash memory reset, proper CPU
The 28F002BC flash memory supports a typical ICC
of 0.2 µA in deep power-down mode. This mode is
activated by the RP# pin when it is at a logic-low
(GND ± 0.2V); in this mode, all internal circuits are
turned off to save power.
initialization would not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.
Setting the RP# pin low de-selects the memory and
places the output drivers in a high impedance state.
Recovery from the deep power-down state requires
3.6.2
V
CC, VPP AND RP# TRANSITIONS
a
minimum access time of 300 ns (see AC
Characteristics table, tPHQV parameter).
The CUI latches commands as issued by system
software and is not altered by VPP, CE# transitions,
or WSM actions. Its default state upon power-up,
after exit from deep power-down mode, or after VCC
transitions above VLKO, is read array mode.
During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as the data has been
corrupted. RP# transitions to VIL or turning power
off to the device will clear the status register.
After any program or block erase operation is
complete, and even after VPP transitions down to
V
PPLK, the CUI must be reset to read array mode
3.6
Power-Up/Down Operation
via the Read Array command if access to the flash
memory is desired.
The 28F002BC offers protection against accidental
block erasure or programming during power
transitions. Power supply sequencing is not
required, since the device is indifferent as to which
power supply, VPP or VCC, powers-up first. The CUI
23
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
3.7.1
E
V
PP TRACE ON PRINTED CIRCUIT
3.7
Power Supply Decoupling
BOARDS
Flash memory’s power switching characteristics
require careful device decoupling methods. System
designers should consider three supply current
issues:
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin supplies the flash memory cells current
for programming and erasing. One should use
similar trace widths and layout considerations given
to the VCC power supply trace. Adequate VPP
supply traces and decoupling capacitors placed
adjacent to the component will decrease spikes and
overshoots.
1. Standby current levels (ICCS
)
2. Active current levels (ICCR
)
3. Transient peaks produced by falling and rising
edges of CE#
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have
a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
24
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
4.0 ELECTRICAL SPECIFICATIONS
NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
4.1
Absolute Maximum Ratings
Operating Temperature
During Read ................................ 0°C to +70°C
During Write and Block Erase...... 0°C to +70°C
Temperature Bias.................... –10°C to +80°C
Storage Temperature................... –65°C to +125°C
Voltage on Any Pin (except VCC, VPP, A9 and RP#)
with Respect to GND............. –2.0V to +7.0V(1)
Voltage on Pin RP# or Pin A9
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
with Respect to GND........ –2.0V to +13.5V(1, 2)
VPP Program Voltage
with Respect to GND during Write
and Block Erase .............. –2.0V to +14.0V(1, 2)
VCC Supply Voltage
with Respect to GND............ –2.0V to +7.0V(1)
Output Short Circuit Current.....................100 mA(3)
NOTES:
1. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to-2.0V for periods <20
ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for
periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.Maximum DC voltage on RP# or A9 may
overshoot to 13.5V for periods <20 ns.
3. Output shorted for no more than one second.No more than one output shorted at a time.
4.2
Operating Conditions
Table 6. Temperature and VCC Operating Conditions
Symbol
Parameter
Operating Temperature
5V VCC Supply Voltage (10%)
Notes
Min
0
Max
70
Units
°C
TA
VCC
4.50
5.50
Volts
25
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
4.2.1 CAPACITANCE
E
TA = +25° C, f = 1 MHz
Symbol
Parameter
Notes
1
Typ
6
Max
8
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
Output Capacitance
COUT
1, 2
10
12
pF
VOUT = 0V
NOTES:
1. Sampled, not 100% tested.
2. For the 28F002BC, address pin A10 follows the COUT capacitance numbers.
4.2.2
INPUT/OUTPUT TEST CONDITIONS
2.4
2.0
2.0
INPUT
OUTPUT
TEST POINTS
0.8
0.8
0.45
0578_09
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL
)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL.
Figure 10. Inputs and Measurement Points
1.3V
1N914
RL
DEVICE
UNDER
OUT
TEST
CL
0578_10
NOTES:
CL = 100 pF, includes Jig Capacitance
RL = 3.3KΩ
Figure 11. Standard Test Configuration
26
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
4.2.3
DC CHARACTERISTICS
Table 7. DC Characteristics
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
CE# = RP# = WP# =
VIH
IIL
Input Load Current
1
± 1.0
µA
ILO
Output Leakage Current
1
± 10
1.5
µA
ICCS
VCC Standby Current
1,3
mA
V
CC = VCC Max
50
0.2
20
100
8.0
55
µA
µA
CE# = RP# = VCC
0.2V
±
VCC Deep Power-Down
Current
VCC = VCC Max
V
RP# = GND ± 0.2V
ICCD
1
IN = VCC or GND
VCC Read Current
CMOS INPUTS
ICCR
1,5
mA
V
CC = VCC Max
CE# = GND
f = 10 MHz
I
OUT = 0 mA
CMOS Inputs: GND ±
0.2V or VCC ± 0.2V
TTL INPUTS
20
60
mA
V
CC = VCC Max
CE# = VIL
f = 10 MHz
I
OUT = 0 mA
TTL Inputs: VIL or VIH
ICCW
ICCE
VCC Program Current
VCC Erase Current
1,4
1,4
50
30
mA
mA
Byte Prog. in Progress
Block Erase in
Progress
VCC Erase Suspend
Current
CE# = VIH
Block Erase Suspend
ICCES
1,2
5
10
mA
IPPS
IPPD
VPP Standby Current
1
1
± 10
5.0
µA
µA
V
PP ≤ VCC
VPP Deep Power-Down
Current
RP# = GND ± 0.2V
IPPR
IPPW
VPP Read Current
1
200
20
µA
VPP > VCC
VPP = VPPH
Byte Prog. in Progress
VPP Program Current
1,4
mA
VPP = VPPH
Block Erase in
Progress
VPP = VPPH
Block Erase
Suspended
IPPE
VPP Erase Current
1,4
1
15
mA
µA
VPP Erase Suspend
Current
IPPES
200
27
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Table 7. DC Characteristics (Continued)
Symbol
IRP#
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
RP# Boot Block Unlock
Current
1,4
500
µA
RP# = VHH
A9 Intelligent Identifier
Current
A9 Intelligent Identifier
Voltage
IID
1,4
500
13.2
0.8
µA
V
A9 = VID
VID
10.8
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
V
V
VCC
+
0.5V
V
I
CC = VCC Min
OL = 5.8 mA
CC = VCC Min
OH = –2.5 mA
CC = VCC Min
OH = –1.5 mA
CC = VCC Min
OH = –100 µA
VOL
VOH
Output Low Voltage
0.45
V
V
V
I
Output High Voltage
(TTL)
2.4
V
I
Output High Voltage
(CMOS)
0.85
VCC
V
V
I
VCC
–
0.4V
Complete Write
Protection
VPPLK
VPPH
VPPH
VLKO
VHH
VPP Lock-Out Voltage
3
7
8
0.0
11.4
10.8
2.0
6.5
V
V
V
V
V
VPP (Program/
Erase Operations)
VPP (Program/
Erase Operations)
VCC Erase/Write Lock
Voltage
12.0
12.0
12.6
13.2
RP# Unlock Voltage
8
10.8
12.0
13.2
Boot Block Unlock
Voltage
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP =12.0V , T = +25°C. These currents are
valid for all product versions (packages and speeds).
2.
I
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
CCES and ICCR
.
3. Block erases and byte writes are inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH and VPPLK
.
4. Sampled, not 100% tested.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH
.
6.
7.
8.
V
V
CC = 12.0V ± 10% for applications requiring 100,000 block erase cycles.
PP = 12.0V ± 5% for applications requiring 100,000 block erase cycles.
V
PP = 12.0V ± 10% for applications requiring wider VPP tolerances: Parameter blocks can sustain 10,000 block erase
cycles; main blocks support up to 100 block erase cycles. Note that erase times are close to maximum spec limits when
using this option.
28
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
4.2.4
AC CHARACTERISTICS
Table 8. AC Characteristics: Read Only Operations
28F002BC-80 28F002BC-120
VCC = 5V ± 10%
100 pF
Symbol
Parameter
Notes
VCC = 5V ± 10%
100 pF
Units
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
Read Cycle Time
80
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Output Delay
CE# to Output Delay
RP# to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# to Output in High Z
OE# to Output in Low Z
OE# to Output in High Z
80
80
120
120
300
40
2
300
40
2
3
3
3
3
3
0
0
0
0
0
0
30
30
30
30
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE—tOE after the falling edge of CE# without impact on tCE
.
3. Sampled, but not 100% tested.
4. See Standard Test Configuration (Figure 11).
29
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Device and
Data
Valid
Address Selection
Standby
VIH
ADDRESSES (A)
VIL
Address Stable
tAVAV
VIH
CE# (E)
VIL
tEHQZ
VIH
OE# (G)
VIL
tGHQZ
VIH
WE# (W)
tGLQV
tGLQX
tOH
VIL
tELQV
VOH
DATA (D/Q)
VOL
tELQX
High Z
High Z
Valid Output
tAVQV
VIH
RP#(P)
tPHQV
VIL
0578_11
Figure 12. AC Waveforms for Read Operations
Table 9. AC Characteristics: WE#—Controlled Write Operations(1)
28F002BC-80
28F002BC-120
Symbol
Parameter
Notes VCC = 5V ± 10%
100 pF
VCC = 5V ± 10%
100 pF
Units
Min
80
Max
Min
120
215
0
Max
tAVAV
Write Cycle Time
ns
ns
ns
ns
tPHWL
tELWL
tPHHWH
RP# Setup to WE# Going Low
CE# Setup to WE# Going Low
215
0
Boot Block Lock Setup to WE#
Going High
6, 8
100
100
tVPWH
tAVWH
tDVWH
tWLWH
tWHDX
tWHAX
tWHEH
VPP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
WE# Pulse Width
5, 8
3
100
50
50
50
0
100
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
4
Data Hold Time from WE# High
Address Hold Time from WE# High
CE# Hold Time from WE# High
4
3
0
0
0
0
30
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Table 9. AC Characteristics: WE#—Controlled Write Operations(1) (Continued)
28F002BC-80
28F002BC-120
Symbol
Parameter
Notes VCC = 5V ± 10%
100 pF
VCC = 5V ± 10%
100 pF
Units
Min
20
Max
Min
20
Max
tWHWL
WE# Pulse Width High
ns
µs
s
tWHQV1
tWHQV2
tWHQV3
Duration of Programming Operation
Duration of Erase Operation (Boot)
2, 5
2, 5, 6
2,5
6
6
0.3
0.3
0.3
0.3
Duration of Erase Operation
(Parameter)
s
tWHQV4
tQVVL
Duration of Erase Operation (Main)
2, 5
5, 8
6, 8
7, 8
0.6
0
0.6
0
s
VPP Hold from Valid SRD
ns
ns
ns
RP# VHH Hold from Valid SRD
tQVPH
0
0
tPHBR
Boot Block Lock Delay
100
100
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A .
IN
4. Refer to command definition table for valid D .
IN
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at VHH until operation completes successfully.
7. Time tPHBR is required for successful relocking of the boot block.
8. Sampled, but not 100% tested.
31
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
1
2
3
4
5
6
VIH
ADDRESSES (A)
VIL
AIN
AIN
tAVAV
tAVWH
tWHAX
VIH
CE# (E)
VIL
tELWL
tWHEH
VIH
OE# (G)
VIL
tWHWL
tWHQV1,2,3,4
VIH
WE# (W)
VIL
tWLWH
tDVWH
tWHDX
VIH
DATA (D/Q)
VIL
High Z
t PHWL
Valid
SRD
D
D
IN
D
IN
IN
tPHHWH
tQVPH
VHH
6.5V
VIH
RP# (P)
VIL
VIH
WP#
VIL
tVPWH
tQVVL
VPPH2
VPPH
VPPLK
VIL
1
VPP(V)
0578_12
NOTES:
1. VCC Power-Up and Standby
2. Write Program Setup or Erase Setup Command
3. Write Valid Address and Data (Program or Erase Confirm Command
4. Automated Program or Erase Delay
5. Read Status Register Data
6. Write Read Array Command
Figure 13. AC Waveforms for Write and Erase Operations (WE#—Controlled Writes)
32
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
Table 10. AC Characteristics: CE#—Controlled Write Operations(1,9)
28F002BC-80 28F002BC-120
Symbol
Parameter
Notes VCC = 5V ± 10%
100 pF
VCC= 5V ± 10%
100 pF
Units
Min
Max
Min
120
215
Max
tAVAV
tPHEL
Write Cycle Time
80
ns
ns
RP# High Recovery to CE# Going
Low
215
tWLEL
WE# Setup to CE# Going Low
0
0
ns
ns
tPHHEH
Boot Block Lock Setup to CE# Going
High
6, 8
100
100
VPP Setup to CE# Going High
tVPEH
tAVEH
tDVEH
tELEH
5, 8
3
100
50
50
50
0
100
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
Address Setup to CE# Going High
Data Setup to CE# Going High
CE# Pulse Width
4
tEHDX
tEHAX
tEHWH
tEHEL
Data Hold Time from CE# High
Address Hold Time from CE# High
WE # Hold Time from CE# High
CE# Pulse Width High
4
3
0
0
0
0
30
6
30
6
tEHQV1
tEHQV2
tEHQV3
Duration of Programming Operation
Duration of Erase Operation (Boot)
2, 5
2, 5, 6
2, 5
0.3
0.3
0.3
0.3
Duration of Erase Operation
(Parameter)
s
tEHQV4
tQVVL
tQVPH
Duration of Erase Operation (Main)
VPP Hold from Valid SRD
2, 5
5, 8
6, 8
7, 8
0.6
0
0.6
0
s
ns
ns
ns
RP# VHH Hold from Valid SRD
Boot Block Lock Delay
0
0
tPHBR
100
100
NOTES:
See WE# Controlled Write Operations for notes 1 through 8.
9. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
33
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
1
2
3
4
5
6
VIH
ADDRESSES (A)
VIL
AIN
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (E)
VIL
tWLEL
tEHWH
VIH
OE# (G)
VIL
t EHEL
t EHQV1,2,3,4
VIH
CE# (W)
VIL
t ELEH
t DVEH
t EHDX
VIH
DATA (D/Q)
VIL
High Z
t PHWL
Valid
SRD
D
D
IN
D
IN
IN
tPHHEH
tQVPH
VHH
6.5V
VIH
RP# (P)
VIL
VIH
WP#
VIL
t VPEH
tQVVL
VPPH
2
VPPH
VPPLK
VIL
1
VPP(V)
0578_13
NOTES:
1. VCC Power-Up and Standby
2. Write Program Setup or Erase Setup Command
3. Write Valid Address and Data (Program or Erase Confirm Command
4. Automated Program or Erase Delay
5. Read Status Register Data
6. Write Read Array Command
Figure 14. Alternate AC Waveforms for Write and Erase Operations (CE#—Controlled Writes)
Table 11. Erase and Program Timings (TA = +25°C)
VPP = 12V ± 10%2
VPP = 12V ± 5%
VCC = 5V ± 10%
Parameter1
VCC = 5V ± 10%
Units
Typ
5.8
14
Max
40
Typ
1.0
2.4
1.2
Max
7
Boot/Parameter Block Erase Time
Main Block Erase Time
s
s
s
60
14
Main Block Write Time
6.0
20
4.2
NOTES:
1. All numbers are sampled, not 100% tested.
2. Erase times near max limits when the 10% VPP option is used.
34
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
APPENDIX A
ORDERING INFORMATION
E2 8F0 0 2BC -
2
T1 0
Package
E = 40-Lead TSOP
P = 40-Lead PDIP
PA = 44-Lead PSOP
Access Speed (ns)
80, 120
Product Line Designator
for all Intel Flash products
T = Top Boot
Density/Organization
Architecture
B = Boot Block
00X = x8-only (X = 2)
0578_14
VALID COMBINATIONS:
40-Lead TSOP
40-Lead PDIP
44-Lead PSOP
PA28F002BC-T80
PA28F002BC-T120
Commercial 2 M
E28F002BC-T80
E28F002BC-T120
P28F002BC-T80
P28F002BC-T120
35
PRELIMINARY
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
APPENDIX B
WSM TRANSITION TABLE
Write State Machine Current/Next States
Command Input (and Next State)
Current
State
SR.7
Data
When
Read
Read
Array
(FFH)
Program Erase
Erase
Erase
Erase
Read
Clear
Read
ID
(90H)
Setup
(40H)
Setup Confirm Susp. Resume Status Status
(20H)
(D0H)
(B0H)
(D0H)
(70H)
(50H)
Read
Array
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
“1”
“1”
“0”
Array
Status
Status
Read Array
Program
Setup
Program (Command Input = Byte Program Data)
Program
Program*
(Not
Comp.)
Program
(Comp.)
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
“1”
“1”
Status
Status
Read Array
Erase
Setup
Erase Command Error
Erase
Cmd.
Error
Erase
Erase
Erase Command Error
Erase
Cmd.
Error
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
“1”
“0”
Status
Status
Status
Read Array
Erase
(Not
Comp.)
Erase
Susp. to
Status
Erase
Erase
Erase
(Comp.)
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
“1”
“1”
Read Array
Erase
Erase
Suspend
to Status
Erase
Erase
Erase
Erase
Erase
Erase
Status Susp. to Susp. to Susp. to Erase Susp. to
Erase
Erase
Susp. to Susp. to Susp. to
Status
Array
Array
Array
Array
Array
Array
Erase
Suspend
to Array
Erase
Erase
Erase
Erase
Erase
Erase
Erase
“1”
Array
Susp. to Susp. to Susp. to Erase Susp. to
Array
Susp. to Susp. to Susp. to
Status
Array
Array
Array
Array
Array
Read
Status
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
“1”
“1”
Status
ID
Read Array
Read Array
Read
Identifier
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array Read ID
NOTE:
You cannot program “1”s to the flash. Writing FFH after the Program Setup command will initiate the program algorithm of the
WSM machine. The WSM will attempt the program, realize you are trying to program “1”s, and exit to read status mode without
changing memory contents. No error is returned. Writing another FFH while in read status mode will return the flash to Read
Array.
36
PRELIMINARY
E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
APPENDIX C
ADDITIONAL INFORMATION
(1,2)
RELATED INTEL INFORMATION
Order Number
Document
292130
292098
292148
292161
292163
290448
290451
290531
290530
AB-57 Boot Block Architecture for Safe Firmware Updates
AP-363 Extended Flash BIOS Concepts for Portable Computers
AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM
AP-608 Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory
AP-610 Flash Memory In-System Code and Data Update Techniques
28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet
28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet
28F002/200BV-T/B 2-Mbit SmartVoltage Flash Memory Datasheet
28F004/400BV-T/B 4-Mbit SmartVoltage Flash Memory Datasheet
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
37
PRELIMINARY
相关型号：
©2020 ICPDF网 联系我们和版权申明