HA-5221 [INTERSIL]
100MHz, Low Noise, Precision Operational Amplifier; 为100MHz ，低噪声，精密运算放大器
| 型号： | HA-5221 |
| 厂家： | 
Intersil |
| 描述： | 100MHz, Low Noise, Precision Operational Amplifier |
| 文件： | 总12页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5221
TM
Data Sheet
April 2000
File Number 2915.5
100MHz, Low Noise, Precision
Operational Amplifier
Features
• Gain Bandwidth Product. . . . . . . . . . . . . . . . . . . . 100MHz
• Unity Gain Bandwidth. . . . . . . . . . . . . . . . . . . . . . . 35MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V/µs
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.3mV
• High Open Loop Gain. . . . . . . . . . . . . . . . . . . . . . . 128dB
• Low Noise Voltage at 1kHz. . . . . . . . . . . . . . . . 3.4nV/√Hz
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 56mA
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
The HA-5221 is a single high performance dielectrically
isolated, op amp, featuring precision DC characteristics while
providing excellent AC characteristics. Designed for audio,
video, and other demanding applications, noise (3.4nV/√Hz at
1kHz), total harmonic distortion (<0.005%), and DC errors are
kept to a minimum.
The precision performance is shown by low offset voltage
(0.3mV), low bias currents (40nA), low offset currents
(15nA), and high open loop gain (128dB). The combination
of these excellent DC characteristics with the fast settling
time (0.4µs) makes the HA-5221 ideally suited for precision
signal conditioning.
Applications
• Precision Test Systems
• Active Filtering
The unique design of the HA-5221 gives it outstanding AC
characteristics not normally associated with precision op
amps, high unity gain bandwidth (35MHz) and high slew rate
(25V/µs). Other key specifications include high CMRR (95dB)
and high PSRR (100dB). The combination of these
specifications will allow the HA-5221 to be used in RF signal
conditioning as well as video amplifiers.
• Small Signal Video
• Accurate Signal Processing
• RF Signal Conditioning
Pinout
For MIL-STD-883C compliant product and Ceramic LCC
packaging, consult the HA-5221/883C data sheet. (Intersil
AnswerFAX (321-724-7800) Document #3716.)
HA-5221
(CERDIP, SOIC)
TOP VIEW
Ordering Information
-BAL
-IN
1
2
3
4
8
7
6
5
+BAL
V+
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
8 Ld CERDIP
8 Ld SOIC
+
+IN
V-
OUT
NC
HA7-5221-5
0 to 75
F8.3A
M8.15
HA9P5221-5
(H52215)
0 to 75
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HA-5221
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 35V
Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
135
157
50
N/A
o
Maximum Junction Temperature (Hermetic Package) . . . . . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range
HA-5221-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input is protected by back-to-back zener diodes. See applications section.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
PARAMETER
V
= ±15V, Unless Otherwise Specified
SUPPLY
o
TEST CONDITIONS
TEMP. ( C)
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Input Offset Voltage
25
Full
Full
25
-
0.30
0.35
0.5
40
0.75
1.5
-
mV
mV
-
o
Average Offset Voltage Drift
Input Bias Current
-
µV/ C
-
100
200
100
150
750
1500
-
nA
nA
nA
nA
µV
µV
V
Full
25
-
70
Input Offset Current
-
15
Full
25
-
30
Input Offset Voltage Match
-
400
-
Full
25
-
Common Mode Range
Differential Input Resistance
Input Noise Voltage
±12
-
25
-
-
-
-
-
-
-
-
-
70
-
kΩ
f = 0.1Hz to 10Hz
25
0.25
6.2
3.6
3.4
4.7
1.8
0.97
<0.005
-
µV
P-P
Input Noise Voltage Density (Notes 3, 11) f = 10Hz
25
10
6
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
%
f = 100Hz
25
f = 1000Hz
25
4.0
8.0
2.8
1.8
-
Input Noise Current Density (Notes 3, 11) f = 10Hz
25
f = 100Hz
25
f = 1000Hz
25
THD+N
Note 4
25
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Note 5
25
Full
Full
25
106
100
86
-
128
120
95
-
-
-
-
dB
dB
CMRR
V
= ±10V
dB
CM
Unity Gain Bandwidth
-3dB
35
MHz
2
HA-5221
Electrical Specifications
PARAMETER
V
= ±15V, Unless Otherwise Specified (Continued)
SUPPLY
o
TEST CONDITIONS
1kHz to 400kHz
TEMP. ( C)
MIN
TYP
100
-
MAX
UNITS
MHz
V/V
Gain Bandwidth Product
Minimum Stable Gain
25
-
-
-
Full
1
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
= 333Ω
Full
25
±10
±12
±11.5
±30
-
-
-
-
-
-
-
-
V
V
L
L
L
R
R
= 1kΩ
= 1kΩ
±12.5
±12.1
±56
10
Full
Full
25
V
Output Current
V
= ±10V
mA
Ω
OUT
Output Resistance
Full Power Bandwidth
Note 6
25
239
398
kHz
TRANSIENT RESPONSE (Note 11)
Slew Rate
Notes 7, 11
Notes 8, 11
Notes 8, 11
0.1%
Full
Full
Full
25
15
-
25
13
-
20
50
-
V/µs
ns
Rise Time
Overshoot
-
28
%
Settling Time (Notes 9, 10)
-
0.4
1.5
µs
0.01%
25
-
-
µs
POWER SUPPLY
PSRR
V
= ±10V to ±20V
Full
Full
86
-
100
8
-
dB
S
Supply Current
11
mA
NOTES:
3. Refer to typical performance curve in data sheet.
4. A
5. V
= 10, f = 1kHz, V = 5V , R = 600Ω, 10Hz to 100kHz, minimum resolution of test equipment is 0.005%.
RMS L
VCL
O
O
= 0 to ±10V, R = 1kΩ, C = 50pF.
OUT
L
L
Slew Rate
--------------------------
6. Full Power Bandwidth is calculated by: FPBW =
, V
= 10V .
PEAK
2πV
PEAK
7. V
8. V
= ±2.5V, R = 1kΩ, C = 50pF.
L L
OUT
= ±100mV, R = 1kΩ, C = 50pF.
OUT
L
L
9. Settling time is specified for a 10V step and A = -1.
V
10. See Test Circuits.
11. Guaranteed by characterization.
Test Circuits and Waveforms
V
+
IN
V
OUT
-
1kΩ
50pF
FIGURE 1. TRANSIENT RESPONSE TEST CIRCUIT
3
HA-5221
Test Circuits and Waveforms (Continued)
100mV
0V
2.5V
0V
V
IN
-100mV
-2.5V
2.5V
100mV
V
0V
-100mV
OUT
0V
-2.5V
V
= ±100mV
OUT
V
= 2.5V
OUT
Vertical Scale = 100mV/Div.,
Horizontal Scale = 200ns/Div.
Vertical Scale = 2V/Div.,
Horizontal Scale = 200ns/Div.
FIGURE 2. LARGE SIGNAL RESPONSE
FIGURE 3. SMALL SIGNAL RESPONSE
V
SETTLE
5K
5K
2K
+
2K
V
IN
V
OUT
NOTES:
12. A = -1.
V
13. Feedback and summing resistors must be matched (0.1%).
14. HP5082-2810 clipping diodes recommended.
15. Tektronix P6201 FET probe used at settling point.
FIGURE 4. SETTLING TIME TEST CIRCUIT
Application Information
Operation at Various Supply Voltages
+15V
The HA-5221 operates over a wide range of supply voltages
with little variation in performance. The supplies may be
varied from ±5V to ±15V. See typical performance curves for
variations in supply current, slew rate and output voltage
swing.
7
R
1
P
2
3
8
6
+
Offset Adjustment
4
The following diagram shows the offset voltage adjustment
configuration for the HA-5221. By moving the potentiometer
wiper towards pin 8 (+BAL), the op amps output voltage will
increase; towards pin 1 (-BAL) decreases the output voltage.
A 20kΩ trim pot will allow an offset voltage adjustment of
about 10mV.
-15V
Capacitive Loading Considerations
When driving capacitive loads >80pF, a small resistor, 50Ω
to 100Ω, should be connected in series with the output and
inside the feedback loop.
4
HA-5221
Saturation Recovery
R
LIMIT
2
When an op amp is over driven, output devices can saturate
and sometimes take a long time to recover. By clamping the
input, output saturation can be avoided. If output saturation
can not be avoided, the maximum recovery time when
overdriven into the positive rail is 10.6µs. When driven into
the negative rail the maximum recovery time is 3.8µs.
6
∆V
IN
V
+
OUT
R
LIMIT
3
PC Board Layout Guidelines
When designing with the HA-5221, good high frequency
(RF) techniques should be used when building a PC board.
Use of ground plane is recommended. Power supply
decoupling is very important. A 0.01µF to 0.1µF high quality
ceramic capacitor at each power supply pin with a 2.2µF to
10µF tantalum close by will provide excellent decoupling.
Chip capacitors produce the best results due to ease of
placement next to the op amp and basically no lead
inductance. If leaded capacitors are used, the leads should
be kept as short as possible to minimize lead inductance.
Input Protection
The HA-5221 has built in back-to-back protection diodes
which limit the maximum allowable differential input voltage
to approximately 5V. If the HA-5221 is used in circuits where
the maximum differential voltage may be exceeded, then
current limiting resistors must be used. The input current
should be limited to a maximum of 10mA.
o
Typical Performance Curves V = ±15V, T = 25 C
S
A
12
R
= 1K, C = 50pF
L
L
9
A
= +1, R = 1K, C = 50pF
V
L
L
120
100
80
60
40
20
0
6
3
GAIN
GAIN
0
-3
-6
180
135
90
45
0
180
135
PHASE
PHASE
10K
90
45
0
10K
100K
1M
FREQUENCY (Hz)
10M
100M
1K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 6. CLOSED LOOP GAIN vs FREQUENCY
9
80
A
= -1, R = 1K, C = 50pF
A = -1000
V
V
L
L
R
= 1K, C = 50pF
L
L
6
3
0
60
40
20
0
A
= -100
= -10
V
A
GAIN
V
A
= -10
V
180
135
90
180
135
90
45
0
A
= -100
V
PHASE
A
= -1000
V
45
0
10K
100K
1M
FREQUENCY (Hz)
10M
100M
10K
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 7. CLOSED LOOP GAIN vs FREQUENCY
FIGURE 8. VARIOUS CLOSED LOOP GAINS vs FREQUENCY
5
HA-5221
o
Typical Performance Curves V = ±15V, T = 25 C (Continued)
S
A
A
= +1, R = 1K
L
A
= +1, R = 1K
L
V
V
120
100
80
60
40
20
0
100
80
-PSRR
60
40
20
0
+PSRR
10K
100K
1M
10M
100M
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
300
250
200
150
100
50
20
18
16
14
12
10
8
R
= 1K
L
6
0
4
-50
2
0
-60
-100
-40
-20
0
20
40
60
o
80
100 120
-60
-40 -20
0
20
40
60
o
80
100 120
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE
FIGURE 12. OFFSET VOLTAGE vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
14
R
= 600Ω
L
13.5
13
160
140
120
100
80
12.5
12
60
40
11.5
11
20
0
-20
-40
10.5
10
-60
-40
-20
0
20
40
60
o
80
100 120
-60
-40 -20
0
20
40
60
o
80
100 120
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 14. OUTPUT VOLTAGE SWING vs TEMPERATURE
FIGURE 13. BIAS CURRENT vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
6
HA-5221
o
Typical Performance Curves V = ±15V, T = 25 C (Continued)
S
A
70
60
1.1
A
= +1, R = 1K, C = 50pF
V
L
L
1.05
50
40
1.0
0.95
0.9
30
20
0.85
0.8
10
0
0
1
2
3
4
5
-60
-40 -20
0
20
40
60
o
80
100 120
TEMPERATURE ( C)
TIME AFTER POWER UP (MINUTES)
FIGURE 15. SLEW RATE vs TEMPERATURE
FIGURE 16. OFFSET VOLTAGE WARM-UP DRIFT
(CERDIP PACKAGES)
8.5
8.25
8
36
A
= +1, R = 2K, C = 50pF
L L
34
32
30
28
26
24
22
20
18
16
14
12
10
V
+SLEW RATE
-SLEW RATE
7.75
7.5
5
7
9
11
13
15
17
5
7
9
11
13
15
17
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE
20
FIGURE 18. SLEW RATE vs SUPPLY VOLTAGE
R
= 600Ω
L
16
24
21
18
15
12
9
15
10
14
12
10
8
6
5
0
4
6
VOLTAGE NOISE
CURRENT NOISE
2
3
0
0
10K
1
10
100
1K
5
7
9
11
13
15
17
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 19. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE
FIGURE 20. NOISE CHARACTERISTICS
7
HA-5221
o
Typical Performance Curves V = ±15V, T = 25 C (Continued)
S
A
100
90
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
80
70
60
50
40
30
+PSRR
-PSRR
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CMRR
98
97
96
95
-60
-40
-20
0
20
40
60
o
80
100
120
-60
-40
-20
0
20
40
60
80
100 120
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 21. OFFSET CURRENT vs TEMPERATURE
(4 REPRESENTATIVE UNITS)
FIGURE 22. CMRR AND PSRR vs TEMPERATURE
130
45
120
100
80
PHASE MARGIN
A
= +1, R = 1K
L
V
40
35
30
110
90
BANDWIDTH
60
40
20
0
25
20
15
70
50
1
10
100
1000
0
1
2
3
4
5
LOAD CAPACITANCE (pF)
TIME AFTER SHORT CIRCUIT (MINUTES)
FIGURE 23. BANDWIDTH AND PHASE MARGIN vs LOAD
CAPACITANCE
FIGURE 24. SHORT CIRCUIT OUTPUT CURRENT vs TIME
Vertical Scale = 1mV/Div.; Horizontal Scale = 1s/Div.
Vertical Scale = 10mV/Div.; Horizontal Scale = 1s/Div.
A
= +25,000; E = 0.168µV
RTI
P-P
A
= +25,000; E = 1.5µV RTI
P-P
V
N
V
N
FIGURE 25. 0.1Hz TO 10Hz NOISE
FIGURE 26. 0.1Hz TO 1MHz
8
HA-5221
o
Typical Performance Curves V = ±15V, T = 25 C (Continued)
S
A
18
16
14
12
10
8
18
16
A
= +1, R = 1K, C = 15pF, THD ≤ 0.01%
L L
A
= +1, THD ≤ 0.01%, f = 1kHz
V
V
V
V
= ±18
= ±15
S
S
V
V
= ±18
= ±15
S
14
12
S
10
8
V
= ±10
= ±5
S
V
V
= ±10
= ±5
S
6
4
2
6
4
2
0
V
S
S
0
10
10K
100K
1M
10M
100
1K
10K
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
FIGURE 27. OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 28. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
10
9.5
9
8.5
8
7.5
7
6.5
6
-60
-40
-20
0
20
40
60
o
80
100 120
TEMPERATURE ( C)
FIGURE 29. SUPPLY CURRENT vs TEMPERATURE
9
HA-5221
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (POWERED UP):
72 mils x 94 mils
V-
1840µm x 2400µm
TRANSISTOR COUNT:
METALLIZATION:
62
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
PROCESS:
Bipolar Dielectric Isolation
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
3
4
2
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
Metallization Mask Layout
HA-5221
-IN
V-
+IN
-BAL
+BAL
OUT
V+
10
HA-5221
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
A
2
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
D
S
M
S
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
11
HA-5221
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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12
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