HC55185AIM [INTERSIL]
VoIP Ringing SLIC Family; 网络电话振铃SLIC家庭型号: | HC55185AIM |
厂家: | Intersil |
描述: | VoIP Ringing SLIC Family |
文件: | 总17页 (文件大小:170K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HC55185
TM
Data Sheet
April 2000
File Number 4831.2
VoIP Ringing SLIC Family
Features
The RSLIC-VoIP family of
ringing subscriber line
interface circuits (RSLIC)
supports analog Plain Old
Telephone Service (POTS) in
• Onboard Ringing Generation
• Compatible with Existing HC5518x Devices
• Low Standby Power Consumption (75V, 65mW)
• Reduced Idle Channel Noise
• Programmable Transient Current Limit
• Improved Off Hook Software Interface
• Integrated MTU DC Characteristics
• Low External Component Count
short and medium loop length, wireless and wireline
applications. Ideally suited for remote subscriber units, this
family of products offers flexibility to designers with high
ringing voltage and low power consumption system
requirements.
• Silent Polarity Reversal
The RSLIC-VoIP family operates to 100V which translates
directly to the amount of ringing voltage supplied to the end
subscriber. With the high operating voltage, subscriber loop
lengths can be extended to 500Ω (i.e., 5,000 feet) and
beyond.
• Pulse Metering and On Hook Transmission
• Tip Open Ground Start Operation
• Thermal Shutdown with Alarm Indicator
• 28 Lead Surface Mount Packaging
• Dielectric Isolated (DI) High Voltage Design
Other key features across the product family include: low
power consumption, ringing using sinusoidal or trapezoidal
waveforms, robust auto-detection mechanisms for when
subscribers go on or off hook, and minimal external discrete
application components. Integrated test access features are
also offered on selected products to support loopback
testing as well as line measurement tests.
Applications
• Voice Over Internet Protocol (VoIP)
• Cable Modems
• Voice Over DSL (VoDSL)
• Short Loop Access Platforms
• Remote Subscriber Units
• Terminal Adapters
There are five product offerings of the HC55185 with each
version providing voltage grades of high battery voltage and
longitudinal balance. The voltage feed amplifier design uses
low fixed loop gains to achieve high analog performance with
low susceptibility to system induced noise.
Related Literature
• AN9814, User’s Guide for Development Board
• AN9824, Modeling of the AC Loop
• Interfacing to DSP CODECs (Contact Factory)
Block Diagram
POL
CDC
VBL
VBH
ILIM
DC
CONTROL
BATTERY
SWITCH
RINGING
PORT
VRS
2-WIRE
PORT
TIP
VRX
VTX
-IN
RING
TRANSMIT
SENSING
4-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
VFB
TL
F2
F1
F0
SW+
SW-
TEST
ACCESS
DETECTOR
LOGIC
CONTROL
LOGIC
RTD RD E0 DET ALM
BSEL SWC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
4-1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
RSLIC18™ is a trademark of Intersil Corporation.
HC55185
Ordering Information (PLCC Package Only)
LONGITUDINAL
BALANCE
FULL
TEST
TEMP.
RANGE
PACKAGE
NO.
o
PART NUMBER
HIGH BATTERY (VBH)
C
PACKAGE
100V
85V
75V
58dB
53dB
HC55185AIM
HC55185BIM
HC55185CIM
HC55185DIM
HC55185ECM
HC55185FCM
HC5518XEVAL1
•
•
•
•
•
•
•
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 75
28 Ld PLCC
28 Ld PLCC
28 Ld PLCC
28 Ld PLCC
28 Ld PLCC
28 Ld PLCC
N28.45
N28.45
N28.45
N28.45
N28.45
N28.45
•
•
•
•
•
•
•
•
•
•
0 to 85
Evaluation board platform, including CODEC.
Also available in Tape and Reel
Device Operating Modes
MODE
Low Power Standby
Forward Active
Unused
F2
F1
F0
0
E0 = 1 E0 = 0 HC55185A HC55185B HC55185C HC55185D HC55185E HC55185F
0
0
SHD
SHD
n/a
GKD
GKD
n/a
•
•
•
•
•
•
•
•
•
•
•
•
0
0
1
0
1
0
Reverse Active
Ringing
0
1
1
SHD
RTD
SHD
SHD
n/a
GKD
RTD
GKD
GKD
n/a
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
0
0
Forward Loop Back
Tip Open
1
0
1
1
1
0
Power Denial
1
1
1
•
•
Device Pinout
HC55185
(PLCC)
TOP VIEW
4
27
26
3
2
1
28
RTD
CDC
SW+
25
24
5
6
SW-
23 VCC
SWC
F2
7
22
8
-IN
VFB
21
F1
9
VTX
20
F0
10
11
E0
VRX
19
12
13
14
15
17
16
18
4-2
HC55185
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
Maximum Supply Voltages
Thermal Resistance (Typical, Note 1)
θ
JA
o
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
CC
CC
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 C/W
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
- V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V
BH
o
o
Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V
ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
o
(PLCC - Lead Tips Only)
Operating Conditions
Die Characteristics
Temperature Range
Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C
Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Positive Power Supply (V ) . . . . . . . . . . . . . . . . . . . . . . . +5V, ±5%
o
o
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
BH
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
o
o
CC
Low Battery Power Supply (V ) . . . . . . . . . . . . . -16V to -52V, ±5%
BL
High Battery Power Supply (V
)
BH
AIM, CIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V to 100V, ±5%
BL
BIM, DIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
V
to -85V, ±10%
to -75V, ±10%
BL
BL
Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
o
o
Electrical Specifications Unless Otherwise Specified, T = -40 C to 85 C for industrial (I) grade and T = 0 C to 85 C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.
PARAMETER
RINGING PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNITS
VRS Input Impedance (Note 2)
Differential Ringing Gain (Note 3)
Ringing Voltage Total Distortion
4-Wire to 2-Wire Ringing Off Isolation
2-Wire to 4-Wire Transmit Isolation
450
-
-
82
3.0
-
kΩ
V/V
%
VRS to 2-wire, R
= ∞
78
-
80
-
LOAD
R
= 1.3 kΩ, V
T-R
= |V | -5
L
BH
Active mode, referenced to VRS input
-
90
80
dB
dB
Ringing mode referenced to the differential ringing
amplitude
-
-
Centering Voltage Accuracy
Tip, Referenced to V /2 + 0.5
BH
-
-
2.5
2.5
-
-
V
V
Ring, Referenced to V /2 + 0.5
BH
AC TRANSMISSION PARAMETERS
Receive Input Impedance (Note 2)
Transmit Output Impedance (Note 2)
4-Wire Port Overload Level
160
-
-
-
1
-
-
-
-
-
-
-
-
-
kΩ
-
Ω
THD = 1%
3.1
3.1
-
3.5
3.5
24
40
21
62
59
67
64
V
V
PK
PK
2-Wire Port Overload Level
THD = 1%
2-Wire Return Loss
300Hz
dB
1kHz
-
dB
dB
dB
dB
dB
dB
3.4kHz
-
2-Wire Longitudinal Balance (Notes 4, 5)
4-Wire Longitudinal Balance
Forward Active, Grade A and B
Forward Active, Grade C, D and E
Forward Active, Grade A and B
Forward Active, Grade C, D and E
58
53
58
53
4-3
HC55185
o
o
o
o
Electrical Specifications Unless Otherwise Specified, T = -40 C to 85 C for industrial (I) grade and T = 0 C to 85 C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.
PARAMETER
2-Wire to 4-Wire Level Linearity
4-Wire to 2-Wire Level Linearity
Referenced to -10dBm
TEST CONDITIONS
+3 to -40dBm, 1kHz
MIN
TYP
0.025
0.050
0.100
-
MAX UNITS
-
-
-
-
-
-
-
dB
dB
dB
-40 to -50dBm, 1kHz
-50 to -55dBm, 1kHz
-
Longitudinal Current Capability (Per Wire) (Note 2)
Test for False Detect
20
10
-0.20
mA
RMS
RMS
Test for False Detect, Low Power Standby
-
mA
4-Wire to 2-Wire Insertion Loss
2-Wire to 4-Wire Insertion Loss
4-Wire to 4-Wire Insertion Loss
Forward Active Idle Channel Noise (Note 5)
0.00 +0.20
dB
-6.22 -6.02 -5.82
-6.22 -6.02 -5.82
dB
dB
o
2-Wire C-Message, T = 25 C
-
-
-
-
10
4
13
7
dBrnC
dBrnC
dBrnC
dBrnC
o
4-Wire C-Message, T = 25 C
o
Reverse Active Idle Channel Noise (Note 5)
2-Wire C-Message, T = 25 C
11
5
14
8
o
4-Wire C-Message, T = 25 C
DC PARAMETERS
Off Hook Loop Current Limit
Programming Accuracy
Programming Range
Programming Accuracy
Programming Range
Forward Polarity Only
-8.5
15
-10
40
18
-
-
-
+8.5
45
+10
100
26
-
%
mA
%
Off Hook Transient Current Limit
-
-
mA
mA
Loop Current During Low Power Standby
-
Open Circuit Voltage
(|Tip - Ring|)
V
V
V
V
V
= -16V
= -24V
> -60V
= -48V
> -60V
8.0
15.5
49
44.5
51.5
V
V
V
V
V
BL
BL
BH
BL
BH
DC
DC
DC
DC
DC
14
43
-
17
-
Low Power Standby
Open Circuit Voltage
(Tip - Ring)
-
43
-
Absolute Open Circuit Voltage
V
V
V
in LPS and FA
in RA
> -60V
-
-53
-56
V
RG
TG
BH
DC
TEST ACCESS FUNCTIONS
Switch On Voltage
I
= 45mA
-
-
0.30
-
0.60
52
V
V
OL
Loopback Max Battery
LOOP DETECTORS AND SUPERVISORY FUNCTIONS
Switch Hook Programming Range
Switch Hook Programming Accuracy
Dial Pulse Distortion
5
-10
-
-
-
15
+10
1
mA
%
Assumes 1% External Programming Resistor
-
%
Ring Trip Comparator Threshold
Ring Trip Programming Current Accuracy
Ground Key Threshold
2.3
-10
-
2.45
-
2.9
+10
-
V
%
12
175
mA
o
Thermal Alarm Output
IC Junction Temperature
-
-
C
4-4
HC55185
o
o
o
o
Electrical Specifications Unless Otherwise Specified, T = -40 C to 85 C for industrial (I) grade and T = 0 C to 85 C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.
PARAMETER
LOGIC INPUTS (F0, F1, F2, E0, SWC)
Input Low Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
-
-
-
-
-
0.8
V
V
Input High Voltage
2.0
-20
-
-
-
Input Low Current
V
V
= 0.4V
= 2.4V
µA
µA
IL
Input High Current
1
IH
LOGIC OUTPUTS (DET, ALM)
Output Low Voltage
I
I
= 5mA
-
.15
3.5
0.4
-
V
V
OL
Output High Voltage
= 100µA
2.4
OH
SUPPLY CURRENTS
Low Power Standby, BSEL = 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.9
0.66
4.9
1.2
7.0
0.9
2.2
6.4
0.3
2.0
10.3
23.5
3.8
.3
6.0
0.90
6.5
2.5
9.5
2.0
3.0
9.0
1.0
3.0
13.5
32
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
BH
CC
BL
Forward or Reverse, BSEL = 0
Forward, BSEL = 1
CC
BL
BH
CC
BL
Ringing, BSEL = 1
BH
CC
BL
Forward Loopback, BSEL = 0
Tip Open, BSEL = 0
5.5
1.0
6.0
0.5
CC
BL
Power Denial, BSEL = 0 or 1
4.0
0.22
CC
BL
ON HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
V
V
V
V
V
V
V
= -24V
= -100V
= -85V
= -75V
= -100V
= -85V
= -75V
-
-
-
-
-
-
-
55
85
-
-
-
-
-
-
-
mW
mW
mW
mW
mW
mW
mW
BL
Low Power Standby
BH
BH
BH
BH
BH
BH
75
65
Ringing
250
230
225
OFF HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
V
= -24V
-
305
-
mW
BL
POWER SUPPLY REJECTION RATIO
4-5
HC55185
o
o
o
o
Electrical Specifications Unless Otherwise Specified, T = -40 C to 85 C for industrial (I) grade and T = 0 C to 85 C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.
PARAMETER
TEST CONDITIONS
MIN
TYP
40
35
28
45
43
33
30
35
33
40
45
MAX UNITS
V
V
to 2-Wire
to 4-Wire
f = 300Hz
f = 1kHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
CC
f = 3.4kHz
f = 300Hz
f = 1kHz
CC
f = 3.4kHz
V
V
V
V
to 2-Wire
to 4-Wire
to 2-Wire
to 4-Wire
300Hz ≤ f ≤ 3.4kHz
300Hz ≤ f ≤ 3.4kHz
300Hz ≤ f ≤ 3.4kHz
300Hz ≤ f ≤ 1kHz
1kHz < f ≤ 3.4kHz
BL
BL
BH
BH
NOTES:
2. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.
3. Differential Ringing Gain is measured with VRS = 0.795V
for -75V devices.
for -100V devices, VRS = 0.663 V
for -85V devices and VRS = 0.575V
RMS RMS
RMS
4. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal.
5. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical
characterization and design.
6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current
limits.
feature. This programming resistor is connected from pin 16
(TL) to ground. In addition some component values have
Product Family Cross Reference
The following table provides an ordering and functional cross
been changed to improve overall device performance. The
reference for the existing HC55180 thru HC55184 products
table below lists the component value changes required for
and the new and improved HC55185 product.
the HC55185 application circuit.
TABLE 1. PRODUCT CROSS REFERENCE
TABLE 2. COMPONENT VALUE CHANGES
EXISTING DEVICES
HC55180CIM, HC55180DIM
HC55181AIM, HC55182AIM
HC55181BIM, HC55182BIM
HC55181CIM, HC55182CIM
HC55181DIM, HC55182DIM
HC55183ECM, HC55184ECM
FUNCTIONAL EQUIVALENT
None Offered
REFERENCE
HC55180 - 184
210kΩ
HC55185
66.5kΩ
≥ 49Ω
≥ 49Ω
4.7µ
RS
HC55185AIM
RP1
RP2
CFB
≥ 35Ω
HC55185BIM
≥ 35Ω
HC55185CIM
0.47µ
HC55185DIM
The value of RS is based on a 600Ω termination impedance
and RP1 = RP2 = 49.9Ω. Design equations are provided to
calculate RS for other combinations of termination and
protection resistance.
HC55185ECM
Any of the HC55185 products may be used without the
battery switch function by shorting the supply pins VBL and
VBH together. This provides compatibility with HC55180
type applications which do not require the battery switch.
The CFB capacitor must be non-polarized for proper device
operation in Reverse Active. Ceramic surface mount
capacitors (1206 body style) are available from Panasonic
with a 6.3V voltage rating. These can be used for CFB since
it is internally limited to approximately 3V. The CDC
capacitor may be either polarized or non polarized.
Application Circuit Modifications
The HC55185 basic application circuit is nearly identical to
that of the HC55180 thru HC55184.The HC55185 requires
an additional resistor to program the transient current limit
4-6
HC55185
FUNCTIONAL DESCRIPTION
Parametric Improvements
Each amplifier is designed to limit source current and sink
current. The diagram below shows the functionality of the
circuit for the case of limiting the source current. A similar
diagram applies to the sink current limit with current polarity
changed accordingly.
The most significant parametric improvement of the
HC55185 is reduction in Idle Channel Noise. This
improvement was accomplished by redistributing gains in
the impedance matching loop. The impact to the application
circuit is the change in the impedance programming resistor
RS. The redistribution of gains also improves AC
performance at the upper end of the voice band.
I
/K
O
I
= 1.21/TL
I
ERR
REF
200k
Functional Improvements
In addition to parametric improvements, internal circuit
changes and application circuit changes have been made to
improve the overall device functionality.
TIP or RING
-
+
20
I
O
I
SIG
VB/2
Off Hook Interface
The transient behavior of the device in response to mode
changes has been significantly improved. The benefit to the
application is reduction or more likely elimination of DET
glitches when off hook events occur. In addition to internal
circuit modifications, the change of CFB value contributes to
this functional improvement.
FIGURE 1. CURRENT LIMIT FUNCTIONAL DIAGRAM
During normal operation, the error current (I
) is zero and
ERR
the output voltage is determined by the signal current (I
)
SIG
multiplied by the 200k feedback resistor. With the current
polarity as shown for I , the output voltage moves positive
Transient Current Limit
SIG
with respect to half battery. Assuming the amplifier output is
driving a load at a more negative potential, the amplifier
output will source current.
The drive current capability of the output amplifiers is
determined by an externally programmable output current
limit circuit which is separate from the DC loop current limit
function and programmed at the pin TL. The current limit
circuit works in both the source and sink direction, with an
internally fixed offset to prevent the current limit functions
from turning on simultaneously. The current limit function is
provided by sensing line current and reducing the voltage
drive to the load when the externally set threshold is
exceeded, hence forcing a constant source or sink current.
During excessive output source current flow, the scaled
output current (I /K) exceeds the reference current (I
)
O
REF
forcing an error current (I
). With the polarity as shown
ERR
the error current subtracts from the signal current, which
reduces the amplifier output voltage. By reducing the output
voltage the source current to the load is decreased and the
output current is limited.
SOURCE CURRENT PROGRAMMING
DETERMINING THE PROPER SETTING
The source current is externally programmed as shown in
Equation 1.
Since this feature programs the maximum output current of
the device, the setting must be high enough to allow for
detection of ring trip or programmed off hook loop current,
whichever is greater.
1780
(EQ. 1)
R
= -------------
TL
I
SRC
For example a source current limit setting of 50mA is
To allow for proper ring trip operation, the transient current
limit setting should be set at least 25% higher than the peak
ring trip current setting. Setting the transient current 25%
higher should account for programming tolerances of both
the ring trip threshold and the transient current limit.
programmed with a 35.6kΩ resistor connected from pin 16 of
the device to ground. This setting determines the maximum
amount of current which flows from Tip to Ring during an off
hook event until the DC loop current limit responds. In
addition this setting also determines the amount of current
which will flow from Tip or Ring when external battery faults
occur.
If loop current is larger than ring trip current (low REN
applications) then the transient current limit should be set at
least 35% higher than the loop current setting. The slightly
higher offset accounts for the slope of the loop current limit
function.
SINK CURRENT PROGRAMMING
The sink current limit is internally offset 20% higher than the
externally programmed source current limit setting.
Attention to detail should be exercised when programming
the transient current limit setting. If ring trip detect does not
occur while ringing, then re-examine the transient current
limit and ring trip threshold settings.
(EQ. 2)
I
= 1.20 × I
SRC
SNK
If the source current limit is set to 50mA, the sink current
limit will be 60mA. This setting will determine the amount of
which flows into Tip or Ring when external ground faults
occur.
4-7
HC55185
4-WIRE TO 2-WIRE GAIN
Design Equations
The 4-wire to 2-wire gain is defined as the receive gain. It is
a function of the terminating impedance, synthesized
impedance and protection resistors. Equation 8 calculates
Loop Supervision Thresholds
SWITCH HOOK DETECT
the receive gain, G
.
The switch hook detect threshold is set by a single external
42
resistor, R . Equation 3 is used to calculate the value of R
SH
.
Z
L
SH
(EQ. 3)
(EQ. 8)
-----------------------------------------
O
G
= –2
42
Z
+ 2R + Z
P L
R
= 600 ⁄ I
SH
SH
When the device source impedance and protection resistors
equals the terminating impedance, the receive gain equals
unity.
The term I
is the desired DC loop current threshold. The
SH
loop current threshold programming range is from 5mA to
15mA.
2-WIRE TO 4-WIRE GAIN
GROUND KEY DETECT
The 2-wire to 4-wire gain (G ) is the gain from tip and ring to
24
the VTX output. The transmit gain is calculated in Equation 9.
The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.
Z
O
(EQ. 9)
-----------------------------------------
O
G
= –
24
Z
+ 2R + Z
P L
When the protection resistors are set to zero, the transmit
gain is -6dB.
RING TRIP DETECT
The ring trip detect threshold is set by a single external
resistor, R . I should be set between the peak ringing
current and the peak off hook current while still ringing. In
RT RT
TRANSHYBRID GAIN
The transhybrid gain is defined as the 4-wire to 4-wire gain
(EQ. 4)
(G ).
44
R
= 1800 ⁄ I
RT
RT
Z
addition, the ring trip current must be set below the transient
O
(EQ. 10)
--------------------------------------
= –
G
44
Z
+ 2R + Z
P L
current limit, including tolerances. The capacitor C , in
O
RT
parallel with R , will set the ring trip response time.
RT
When the protection resistors are set to zero, the transhybrid
gain is -6dB.
Loop Current Limit
The loop current limit of the device is programmed by the
external resistor R . The value of R can be calculated
COMPLEX IMPEDANCE SYNTHESIS
IL IL
using Equation 5.
1760
Substituting the impedance programming resistor, R , with a
S
complex programming network provides complex
impedance synthesis.
(EQ. 5)
R
= ------------
IL
I
LIM
The term I
is the desired loop current limit. The loop
2-WIRE
NETWORK
PROGRAMMING
NETWORK
LIM
current limit programming range is from 15mA to 45mA.
C
C
2
P
Impedance Matching
R
R
1
S
The impedance of the device is programmed with the
R
R
2
P
external component R . R is the gain setting resistor for
S
S
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
FIGURE 2. COMPLEX PROGRAMMING NETWORK
network can be substituted for R .
S
The reference designators in the programming network
RESISTIVE IMPEDANCE SYNTHESIS
match the evaluation board. The component R has a
S
The source impedance of the device, Z , can be calculated
O
different design equation than the R used for resistive
S
in Equation 6.
impedance synthesis. The design equations for each
component are provided below.
(EQ. 6)
R
= 133.3(Z )
O
S
(EQ. 11)
R
= 133.3 × (R – 2(R ))
1 P
S
The required impedance is defined by the terminating
impedance and protection resistors as shown in Equation 7.
(EQ. 12)
(EQ. 13)
R
C
= 133.3 × R
P
P
2
(EQ. 7)
˙
Z
= Z – 2R
L P
= C ⁄ 133.3
O
2
4-8
HC55185
Ring terminal will be clamped by the internal reference. The
Low Power Standby
same Ring relationships apply when operating from the low
battery voltage. For high battery voltages (VBH) less than or
equal to the internal MTU reference threshold:
(EQ. 14)
Overview
The low power standby mode (LPS, 000) should be used
during idle line conditions. The device is designed to operate
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be
operated from the low battery. Operation from the low
battery will decrease the standby power dissipation.
V
= V
+ 4
BH
RING
Loop Current
During LPS, the device will provide current to a load. The
current path is through resistors and switches, and will be
function of the off hook loop resistance (R
). This
LOOP
includes the off hook phone resistance and copper loop
resistance. The current available during LPS is determined
by Equation 15.
TABLE 3. DEVICE INTERFACES DURING LPS
INTERFACE
Receive
ON
OFF
NOTES
(EQ. 15)
x
x
x
AC transmission, impedance
matching and ringing are
disabled during this mode.
I
= (– 1 – (–49)) ⁄ (600 + 600 + R
)
LOOP
LOOP
Ringing
Internal current limiting of the standby switches will limit the
maximum current to 20mA.
Transmit
2-Wire
x
x
Amplifiers disabled.
Another loop current related parameter is longitudinal
current capability. The longitudinal current capability is
Loop Detect
Switch hook or ground key.
reduced to 10mA
current capability is a result of turning off the Tip and Ring
amplifiers.
per pin. The reduction in longitudinal
RMS
2-Wire Interface
During LPS, the 2-wire interface is maintained with internal
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will
provide MTU compliance, loop current and loop supervision.
Figure 3 represents the internal circuitry providing the 2-wire
interface during low power standby.
On Hook Power Dissipation
The on hook power dissipation of the device during LPS is
determined by the operating voltages and quiescent currents
and is calculated using Equation 16.
GND
(EQ. 16)
P
= V
× I
+ V × I
+ V
× I
CC CCQ
LPS
BH
BHQ
BL
BLQ
600Ω
TIP AMP
The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.
TIP
RING
RING AMP
Standby Current Power Dissipation
600Ω
Any standby line current, I
power dissipation term P
SLC
, introduces an additional
. Equation 17 illustrates the
SLC
MTU REF
power contribution is zero when the standby line current is
zero.
FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
MTU Compliance
(EQ. 17)
P
= I
× ( V
– 49 + 1 + I
x1200)
SLC
SLC
SLC
BH
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage is 42.75V. The
high side of the MTU range is 56V. The voltage is expressed
as the difference between Tip and Ring.
If the battery voltage is less than -49V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 18.
(EQ. 18)
P
= I
× ( V
+ 1 + I
x1200)
SLC
SLC
SLC
BH
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of
-49V (by MTU REF) when operating from either the high or
low battery. A switch and 600Ω resistor connect the MTU
reference to the Ring terminal. When the high battery
voltage exceeds the MTU reference of -49V (typically), the
Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.
4-9
HC55185
filter is set by the external capacitor C . The value of the
DC
external capacitor should be 4.7µF.
Forward Active
Overview
Most applications will operate the device from low battery
while off hook. The DC feed characteristic of the device will
drive Tip and Ring towards half battery to regulate the DC
loop current. For light loads, Tip will be near -4V and Ring
The forward active mode (FA, 001) is the primary AC
transmission mode of the device. On hook transmission, DC
loop feed and voice transmission are supported during forward
active. Loop supervision is provided by either the switch hook
detector (E0 = 1) or the ground key detector (E0 = 0). The
device may be operated from either high or low battery for on-
hook transmission and low battery for loop feed.
will be near V
+ 4V. The following diagram shows the DC
VBL
feed characteristic.
V
m = (∆V /∆I ) = 11.1kΩ
TR
TR(OC)
L
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.5V
.
PEAK
I
LIM
I
(mA)
LOOP
When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 19.
(EQ. 19)
FIGURE 5. DC FEED CHARACTERISTIC
The point on the y-axis labeled V
is the open circuit
TR(OC)
Tip to Ring voltage and is defined by the feed battery
voltage.
V
= V
+ 4
BH
RING
(EQ. 20)
V
= V
– 8
BL
TR(OC)
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should
be selected for DC loop feed and voice transmission.
The curve of Figure 5 determines the actual loop current for
a given set of loop conditions. The loop conditions are
determined by the low battery voltage and the DC loop
impedance. The DC loop impedance is the sum of the
protection resistance, copper resistance (ohms/foot) and the
telephone off hook DC resistance.
Feed Architecture
The design implements a voltage feed current sense
architecture. The device controls the voltage across Tip and
Ring based on the sensing of load current. Resistors are
placed in series with Tip and Ring outputs to provide the
current sensing. The diagram below illustrates the concept.
I
I
A
SC
I
I
B
LIM
R
R
A
B
V
IN
R
CS
-
V
+
OUT
2R
R
KNEE
P
R
(Ω)
LOOP
R
R
L
C
FIGURE 6. I
VERSUS R
LOAD CHARACTERISTIC
LOOP
LOOP
-
+
The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
K
S
FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM
loop as the short circuit current I
.
SC
V
– 2R I
TR(OC)
P LIM
By monitoring the current at the amplifier output, a negative
feedback mechanism sets the output voltage for a defined
(EQ. 21)
I
= I
+ -----------------------------------------------------
SC
LIM
1.1e4
load. The amplifier gains are set by resistor ratios (R , R ,
A
B
The term I
is the programmed current limit, 1760/R .
IL
LIM
R ) providing all the performance benefits of matched
C
The line segment I represents the constant current region
of the loop current limit function.
A
resistors. The internal sense resistor, R , is much smaller
CS
than the gain resistors and is typically 20Ω for this device.
V
– R
I
LOOP LIM
TR(OC)
(EQ. 22)
The feedback mechanism, K , represents the amplifier
I = I
+ --------------------------------------------------------------
S
A
LIM
1.1e4
configuration providing the negative feedback.
The maximum loop impedance for a programmed loop
DC Loop Feed
current is defined as R
.
KNEE
The feedback mechanism for monitoring the DC portion of
the loop current is the loop detector. A low pass filter is used
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass
V
TR(OC)
(EQ. 23)
R
= -----------------------
KNEE
I
LIM
4-10
HC55185
When R
is exceeded, the device will transition from
maintain voice quality. Most applications will use a summing
amplifier in the CODEC front end as shown below to cancel
the echo signal.
KNEE
constant current feed to constant voltage, resistive feed. The
line segment I represents the resistive feed portion of the
B
load characteristic.
V
R
TR(OC)
(EQ. 24)
I
= -----------------------
B
R
VRX
VTX
R
R
LOOP
RX OUT
A
R
1:1
Voice Transmission
R
F
B
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below.
-
+
T
A
TX IN
R
S
+2.4V
CODEC
-IN
HC5518x
R
R
FIGURE 8. TRANSHYBRID BALANCE INTERFACE
VRX
20
20
-
R
The resistor ratio, R /R , provides the final adjustment for
F
B
TIP
+
1:1
the transmit gain, G . The transmit gain is calculated using
TX
Equation 27.
VTX
+
RING
-
R
F
R
B
T
A
(EQ. 27)
-------
= –G
R
S
TX
24
R
3R
-IN
C
4R
4R
4R
4R
Most applications set R = R , hence the device 2-wire to
F
B
FB
8K
4-wire equals the transmit gain. Typically R is greater than
B
-
+
VFB
20kΩ to prevent loading of the device transmit output.
V
SA
3R
The resistor ratio, R /R , is determined by the transhybrid
F
A
gain of the device, G . R is previously defined by the
44
F
transmit gain requirement and R is calculated using
Equation 28.
A
FIGURE 7. AC SIGNAL TRANSMISSION MODEL
R
B
R = ----------
(EQ. 28)
The gain of the transmit amplifier, set by R , determines the
S
A
G
44
programmed impedance of the device. The capacitor C
FB
blocks the DC component of the loop current. The ground
symbols in the model represent AC grounds, not actual DC
potentials.
Power Dissipation
The power dissipated by the device during on hook
transmission is strictly a function of the quiescent currents
for each supply voltage during Forward Active operation.
The sense amp output voltage, V , as a function of Tip and
SA
Ring voltage and load is calculated using Equation 25.
P
= V
× I
+ V × I
+ V
× I
CC CCQ
(EQ. 29)
FAQ
BH
BL
BLQ
BHQ
30
(EQ. 25)
------
V
= –(V – V
)
SA
T
R
Z
L
Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to R
current, I , and the power dissipation is calculated using
Equation 30.
The transmit amplifier provides the programmable gain
required for impedance synthesis. In addition, the output of
this amplifier interfaces to the CODEC transmit input. The
output voltage is calculated using Equation 26.
, the device is providing constant
KNEE
A
R
2
(EQ. 30)
S
P
= P
+ (V xI ) – (R
LOOP
xI
)
A
(EQ. 26)
FA(IA)
FA(Q)
BL
A
----------
V
= –V
SA
VTX
8e3
If the loop length is greater than R
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 31.
, the device is
KNEE
Once the impedance matching components have been
selected using the design equations, the above equations
provide additional insight as to the expected AC node
voltages for a specific Tip and Ring load.
2
(EQ. 31)
P
= P
+ (V xI ) – (R xI
LOOP
)
B
FA(IB)
FA(Q)
BL
B
Transhybrid Balance
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
The final step in completing the impedance synthesis design
is calculating the necessary gains for transhybrid balance.
The AC feed back loop produces an echo at the V output
TX
of the signal injected at V . The echo must be cancelled to
RX
4-11
HC55185
Ringing
Reverse Active
Overview
Overview
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.
The ringing mode (RNG, 100) provides linear amplification
to support a variety of ringing waveforms. A programmable
ring trip function provides loop supervision and auto
disconnect upon ring trip. The device is designed to operate
from the high battery during this mode.
Architecture
During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.
The device provides linear amplification to the signal applied
to the ringing input, V . The differential ringing gain of the
RS
device is 80V/V. The circuit model for the ringing path is
shown in the following figure.
R
R/8
-
Silent Polarity Reversal
+
20
20
VRS
-
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.
TIP
+
600K
5:1
V
+
BH
2
-
+
RING
-
The device uses an external low voltage capacitor, C
, to
POL
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.
R
FIGURE 10. LINEAR RINGING MODEL
The voltage gain from the VRS input to the Tip output is
40V/V. The resistor ratio provides a gain of 8 and the current
mirror provides a gain of 5. The voltage gain from the VRS
input to the Ring output is -40V/V. The equations for the Tip
and Ring outputs during ringing are provided below.
V
The internal circuitry used to set the polarity reversal time is
shown below.
I
1
POL
BH
2
(EQ. 33)
V = ----------- + (40 × VRS)
T
75kΩ
C
POL
V
BH
(EQ. 34)
I
2
V
= ----------- – (40 × VRS)
R
2
When the input signal at VRS is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
FIGURE 9. REVERSAL TIMING CONTROL
During forward active, the current from source I1 charges the
external timing capacitor C
and the switch is open. The
POL
internal resistor provides a clamping function for voltages on
the POL node. During reverse active, the switch closes and
I2 (roughly twice I1) pulls current from I1 and the timing
capacitor. The current at the POL node provides the drive to
a differential pair which controls the reversal time of the Tip
and Ring DC voltages.
Ringing Input
The ringing input, V , is a high impedance input. The high
RS
impedance allows the use of low value capacitors for AC
coupling the ring signal. The V
input is enabled only
RS
∆time
(EQ. 32)
C
= ----------------
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.
POL
75000
Where ∆time is the required reversal time. Polarized
capacitors may be used for C . The low voltage at the
POL pin and minimal voltage excursion ±0.75V, are well
When operating from a battery of -100V, each amplifier, Tip
POL
and Ring, will swing a maximum of 95V . Hence, the
P-P
maximum signal swing at VRS to achieve full scale ringing is
suited to polarized capacitors.
approximately 2.4V . The low signal levels are compatible
P-P
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator. See Applications Section.
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
4-12
HC55185
Forward Loop Back
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
R
and C . The resistor R sets the trip threshold and the
RT
RT RT
capacitor C sets the trip response time. Most applications will
RT
require a trip response time less than 150ms.
TIP
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
TIP AMP
600Ω
RING AMP
RING
FIGURE 11. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P , and the silent interval power, P .
r
s
t
t
r
s
AC Verification
(EQ. 35)
------------- -------------
+ P ×
s
P
= P ×
RNG
r
t + t
t + t
r s
r
s
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
The terms t and t represent the cadence. The ringing
R
S
interval is t and the silent interval is t . The typical cadence
R
S
ratio t :t is 1:2.
R S
The quiescent power of the device in the ringing mode is
defined in Equation 36.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
P
= V
× I
+ V × I
+ V
× I
CC CCQ
(EQ. 36)
r(Q)
BH
BHQ
BL
BLQ
The total power during the ringing interval is the sum of the
the test level times the gain R /R of the transhybrid
F
A
quiescent power and loading power:
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
return signal would be much lower in amplitude than the first
step, indicating the device was active and the internal
termination attenuated the return signal.
2
V
RMS
(EQ. 37)
, is
P
= P
+ V
× I
– -----------------------------------------
r
r(Q)
BH
AVG
Z
+ R
LOOP
REN
For sinusoidal waveforms, the average current, I
defined in Equation 38.
AVG
V
× 2
System architectures which disable the transhybrid function
would achieve test coverage with a signal step. Once the
transhybrid function is disable, program the device for FLB
and send the test tone. The return signal level is determined
by the 4-wire to 4-wire gain of the device.
2
π Z
RMS
(EQ. 38)
-- -----------------------------------------
=
I
AVG
+ R
LOOP
REN
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
4-13
HC55185
Functionality
Tip Open
The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.
Overview
The tip open mode (110) is intended for compatibility for
PBX type interfaces. Used during idle line conditions, the
device does not provide transmission. Loop supervision is
provided by either the switch hook detector (E0 = 1) or the
ground key detector (E0 = 0). The ground key detector will
be used in most applications. The device may be operated
from either high or low battery.
When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET output.
The only external component required to support the battery
switch is a diode in series with the V
event that high battery is removed, the diode allows the
device to transition to low battery operation.
supply lead. In the
BH
Functionality
During tip open operation, the Tip switch is disabled and the
Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be the
Ring switch.
Low Battery Operation
All off hook operating conditions should use the low battery.
The prime benefit will be reduced power dissipation. The
typical low battery for the device is -24V. However this may
be increased to support longer loop lengths or high loop
current requirements. Standby conditions may also operate
from the low battery if MTU compliance is not required,
further reducing standby power dissipation.
In keeping with the MTU characteristics of the device, Ring
will not exceed -56V when operating from the high battery.
Though MTU does not apply to tip open, safety requirements
are satisfied.
Power Denial
High Battery Operation
Overview
Other than ringing, the high battery should be used for
standby conditions which must provide MTU compliance.
During standby operation the power consumption is typically
85mW with -100V battery. If ringing requirements do not
require full 100V operation, then a lower battery will result in
lower standby power.
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
shut down in the presence of a persistent thermal alarm.
Switching between high and low battery will have no effect
during power denial.
High Voltage Decoupling
Functionality
The 100V rating of the device will require a capacitor of
higher voltage rating for decoupling. Suggested decoupling
values for all device pins are 0.1µF. Standard surface mount
ceramic capacitors are rated at 100V. For applications driven
at low cost and small size, the decoupling scheme shown
below could be implemented.
During power denial, both the Tip and Ring amplifiers are
disabled, representing high impedances. The voltages at
both outputs are near ground.
Thermal Shutdown
In the event the safe die temperature is exceeded, the ALM
output will go low and DET will go high and the part will
automatically shut down. When the device cools, ALM will
go high and DET will reflect the loop status. If the thermal
fault persists, ALM will go low again and the part will shut
down. Programming power denial will permanently
0.22µ
0.22µ
VBL
VBH
shutdown the device and stop the self cooling cycling.
HC5518X
Battery Switching
FIGURE 12. ALTERNATE DECOUPLING SCHEME
Overview
It is important to place the external diode between the VBH
pin and the decoupling capacitor. Attaching the decoupling
capacitor directly to the VBH pin will degrade the reliability of
the device. Refer to Figure 12 for the proper arrangement.
This applies to both single and stacked and decoupling
arrangements.
The integrated battery switch selects between the high
battery and low battery. The battery switch is controlled
with the logic input BSEL. When BSEL is a logic high, the
high battery is selected and when a logic low, the low
battery is selected. All operating modes of the device will
operate from high or low battery except forward loop back.
If VBL and VBH are tied together to override the battery
switch function, then the external diode is not needed and
the decoupling may be attached directly to VBH.
4-14
HC55185
Basic Application Circuit
Uncommitted Switch
C
PS1
Overview
C
PS2
The uncommitted switch is a three terminal device designed
for flexibility. The independent logic control input, SWC,
allows switch operation regardless of device operating
mode. The switch is activated by a logic low. The positive
and negative terminals of the device are labeled SW+ and
SW- respectively.
D
1
C
PS3
VCC
VBH
VRX
VBL
C
C
RX
RS
R
R
P1
U
1
TIP
HC55185 VRS
Relay Driver
P2
VTX
RING
SW+
SW-
C
The uncommitted switch may be used as a relay driver by
connecting SW+ to the relay coil and SW- to ground. The
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.
TX
R
S
-IN
C
RT
RT
C
FB
VFB
R
RTD
+5V
SWC
BSEL
E0
R
SH
RELAY
RD
R
IL
ILIM
F0
SW+
C
DC
CDC
POL
V
F1
CC
SWC
C
SW-
POL
F2
DET
R
TL
TL
ALM
BGND
FIGURE 13. EXTERNAL RELAY SWITCHING
AGND
Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.
FIGURE 15. HC55185 BASIC APPLICATION CIRCUIT
TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST
Test Load
COMPONENT
VALUE
HC55185
18.7kΩ
23.7kΩ
49.9kΩ
71.5kΩ
66.5kΩ
0.47µF
4.7µF
TOL
N/A
1%
RATING
N/A
The switch may be used to connect test loads across Tip
and Ring. The test loads can provide external test
termination for the device. Proper connection of the
uncommitted switch to Tip and Ring is shown below.
U1 - Ringing SLIC
R
R
R
R
R
C
C
C
C
D
R
0.1W
0.1W
0.1W
0.1W
0.1W
10V
TL
RT
SH
IL
1%
1%
TIP
1%
1%
S
RING
, C , C , C , C
RX RS TX RT POL
20%
20%
20%
20%
, C
10V
DC FB
TEST
LOAD
0.1µF
>100V
100V
PS1
SW+
, C
PS3
0.1µF
PS2
1
SWC
1N400X type with breakdown > 100V.
SW-
, R
P2
P1
FIGURE 14. TEST LOAD SWITCHING
Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are reversed
for half of the ringing cycle. With independent logic control
and the blocking diode, the uncommitted switch may be
continuously connected to the Tip and Ring terminals.
Design Parameters: Ring Trip Threshold = 76mA
, Switch
PEAK
Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize
Device Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω
protection resistors, impedance across Tip and Ring
terminals = 599Ω. Transient current limit = 95mA.
4-15
HC55185
Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
1
2
TIP
TIP power amplifier output.
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
3
4
5
6
7
VBL
VBH
SW+
SW-
SWC
Low battery supply connection.
High battery supply connection for the most negative battery.
Uncommitted switch positive terminal.
Uncommitted switch negative terminal.
Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and
logic “1” disabling the switch.
8
F2
Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of
operation of the device.
9
F1
F0
E0
Mode control input.
Mode control input.
10
11
Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0)
comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table
shown on page 2).
12
13
DET
ALM
Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode.
The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on
page 2).
Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature
o
(approximately 175 C) and the device has been powered down automatically.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND
BSEL
TL
Analog ground reference. This pin should be externally connected to BGND.
Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
Programming pin for the transient current limit feature, set by an external resistor to ground.
External capacitor on this pin sets the polarity reversal time.
POL
VRS
VRX
VTX
VFB
-IN
Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC.
Transmit Output Voltage - Output of impedance matching amplifier, AC couples to CODEC.
Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.
Impedance matching amplifier summing node.
VCC
CDC
RTD
ILIM
RD
Positive voltage power supply, usually +5V.
DC Biasing Filter Capacitor - Connects between this pin and V
Ring trip filter network.
.
CC
Loop Current Limit programming resistor.
Switch hook detection threshold programming resistor.
RING power amplifier output.
RING
4-16
HC55185
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.485
0.450
0.191
0.485
0.450
0.191
0.180
0.120
0.495
0.456
0.219
0.495
0.456
0.219
-
2.29
3.04
-
-
D2/E2
D2/E2
12.32
11.43
4.86
12.57
11.58
5.56
C
L
D1
D2
E
3
E1 E
4, 5
-
12.32
11.43
4.86
12.57
11.58
5.56
VIEW “A”
E1
E2
N
3
4, 5
6
0.020 (0.51)
MIN
28
28
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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4-17
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