HD-15531883 [INTERSIL]
CMOS Manchester Encoder-Decoder; CMOS曼彻斯特编码器，解码器
| 型号： | HD-15531883 |
| 厂家： | 
Intersil |
| 描述： | CMOS Manchester Encoder-Decoder |
| 文件： | 总8页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
HD-15531/883
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Intersil HD-15531/883 is a high performance CMOS
device intended to service the requirements of MIL-STD-
1553 and similar Manchester II encoded, time division multi-
plexed serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections oper-
ate independently of each other, except for the master reset
and word length functions. This circuit provides many of the
requirements of MIL-STD-1553. The Encoder produces the
sync pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes the sync pulse and identi-
fies it as well as decoding the data bits and checking parity.
• Support of MIL-STD-1553
• Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec
• Data Rate (15531). . . . . . . . . . . . . . . . .1.25 Megabit/Sec
• Variable Frame Length to 32-Bits
• Sync Identification and Lock-In
• Separate Manchester II Encode, Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
The HD-15531/883 also surpasses the requirements of MIL-
STD-1553 by allowing the word length to be programmable
(from 2 to 28 data bits). A frame consists of three bits for
sync followed by the data word (2 to 28 data bits) followed by
one bit of parity, thus, the frame length will vary from 6 to 32
bit periods. This chip also allows selection of either even or
odd parity for the Encoder and Decoder separately.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MIL-STD-1553 over both temperature and
voltage. For high speed applications the 15531B will support
a 2.5 Megabit/sec data rate.
The HD-15531/883 can also be used in many party line digi-
tal data communications applications, such as a local area
network or an environmental control system driven from a
single twisted pair or fiber optic cable throughout a building.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
1.25MBIT/SEC
HD1-15531/883
2.5MBIT/SEC
HD1-15531B/883
PKG. NO.
F40.6
o
o
-55 C to +125 C
FN2962.1
170
HD-15531/883
Pinout
HD-15531/883 (CERDIP)
TOP VIEW
VCC
1
2
40
39
38
COUNT C1
COUNT C4
DATA SYNC
VALID WORD
TAKE DATA’
TAKE DATA
3
4
37 ENCODER CLK
5
COUNT C3
NC
36
35
34
33
32
31
30
29
28
27
SERIAL DATA OUT
SYNCHR DATA
6
7
SYNCHR DATA SEL
ENCODER SHIFT CLK
SEND CLK IN
8
SYNCHR CLK
DECODER CLK
9
SEND DATA
10
11
12
SYNCHR CLK SEL
BIPOLAR ZERO IN
BIPOLAR ONE IN
ENCODER PARITY SEL
SYNC SEL
ENCODER ENABLE
SERIAL DATA IN
13
14
15
16
UNIPOLAR DATA IN
DECODER SHIFT CLK
BIPOLAR ONE OUT
26 OUTPUT INHIBIT
TRANSITION SEL
NC
25 BIPOLAR ZERO OUT
17
18
19
24
23
÷ 6 OUT
COMMAND SYNC
COUNT 2
DECODER PARITY SEL
22 MASTER RESET
21
DECODER RESET
COUNT C0 20
GND
Block Diagrams
ENCODER
GND
V
CC
21
22
33
24
1
MASTER RESET
SEND CLK IN
6 OUT
OUTPUT
INHIBIT
26
27
25
BIPOLAR
÷ 2
ONE OUT
CHARACTER
FORMER
÷ 6
BIPOLAR
ZERO OUT
ENCODER
CLK
37
BIT
COUNTER
34
28
29
30
31
32
20 40 23 36 39
SEND
DATA
SERIAL
DATA IN
SYNC
SELECT
C
C
C
C
C
4
0
1
2
3
ENCODER
ENCODER ENCODER
SHIFT
CLK
ENABLE
PARITY
SELECT
171
HD-15531/883
Block Diagrams (Continued)
DECODER
7
8
SYNCHRONOUS
DATA SELECT
SYNCHRONOUS
DATA
13
UNIPOLAR
DATA IN
4
TAKE DATA
COMMAND
DATA
SELECT
GATE
12
11
17
38
TRANSITION
FINDER
CHARACTER
IDENTIFIER
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
DATA SYNC
5
SERIAL
DATA OUT
9
2
DECODER
CLK
VALID WORD
CLOCK
SELECT
DATA
BIT
RATE
CLK
PARITY
SYNCHRONIZER
16
CHECK
PARITY
SELECT
15
DECODER
CLK SELECT
8
SYNCHRONOUS
CLK
14
DECODER
SHIFT CLK
10
22
SYNCHRONOUS
CLK SELECT
MASTER
RESET
19
3
BIT
COUNTER
DECODER
RESET
TAKE DATA
20 40 23 36 39
C0 C1 C2 C3 C4
172
HD-15531/883
Absolute Maximum Ratings
Thermal Information
Thermal Resistance
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
θ
θ
JA
JC
o
o
CERDIP Package . . . . . . . . . . . . . . . . . .
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C
35 C/W
9 C/W
o
o
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Sync. Transition Span (TD2). . . . . . . . . . . 18 TDC Typical, (Note 1)
Short Data Transition Span (TD4). . . . . . . . 6 TDC Typical, (Note 1)
Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)
o
o
Operating Temperature Range (T ). . . . . . . . . . . . -55 C to +125 C
A
Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . .8ns Max
Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max
TABLE 1. HD-15531/883, HD-15531B/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
MAX
GROUP A
SUBGROUPS
SYMBOL
PARAMETER
TEST CONDITIONS
TEMPERATURE
MIN
UNITS
o
o
Input LOW Voltage
VIL
VIH
VCC = 4.5V and 5.5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
0.2 VCC
V
A
o
o
Input HIGH Voltage
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
-55 C ≤ T ≤ +125 C 0.7 VCC
-
V
V
V
V
A
o
o
Input LOW Clock Voltage
Input HIGH Clock Voltage
Output LOW Voltage
VILC
VIHC
VOL
-55 C ≤ T ≤ +125 C
-
GND +0.5
A
o
o
-55 C ≤ T ≤ +125 C VCC -0.5
-
A
o
o
IOL = +1.8mA,
VCC = 4.5V (Note 2)
-55 C ≤ T ≤ +125 C
-
2.4
-1.0
-
0.4
A
o
o
Output HIGH Voltage
Input Leakage Current
Standby Supply Current
VOH
II
IOH = -3.0mA,
VCC = 4.5V (Note 2)
1, 2, 3
1, 2, 3
1, 2, 3
7, 8
-55 C ≤ T ≤ +125 C
-
+1.0
2
V
µA
mA
-
A
o
o
VI = VCC or GND,
VCC = 5.5V
-55 C ≤ T ≤ +125 C
A
o
o
ICCSB
FT
VIN = VCC = 5.5V,
Outputs Open
-55 C ≤ T ≤ +125 C
A
o
o
Functional Test
NOTES:
(Note 3)
-55 C ≤ T ≤ +125 C
-
-
A
1. TDC = Decoder clock period = 1/FDC.
2. Interchanging of force and sense conditions is permitted.
3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH ≥ VCC/2 and VOL ≤ VCC/2.
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
GROUPA
SUB-
HD-15531/883
HD-15531B/883
(NOTE 2)
PARAMETER SYMBOL
ENCODER TIMING
CONDI-TIONS
GROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
o
o
Encoder
Clock
FEC
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
15
-
30
MHz
A
Frequency
o
o
Send Clock
Frequency
FESC
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
2.5
-
5.0
MHz
A
173
HD-15531/883
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
GROUPA
SUB-
HD-15531/883
HD-15531B/883
(NOTE 2)
PARAMETER SYMBOL
CONDI-TIONS
GROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
o
o
Encoder Data
Rate
FED
TMR
TE1
TE2
TE3
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
1.25
-
2.5
MHz
A
o
o
Master Reset
Pulse Width
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
150
-
-
150
-
-
80
-
ns
ns
ns
ns
A
o
o
Shift Clock
Delay
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
125
A
o
o
Serial Data
Setup
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
75
75
-
-
50
50
A
o
o
Serial Data
Hold
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
A
o
o
Enable Setup
TE4
TE5
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
90
-
-
90
-
-
ns
ns
A
o
o
Enable Pulse
Width
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
100
100
A
o
o
Sync Setup
TE6
TE7
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
55
-
-
55
-
-
ns
ns
A
o
o
Sync Pulse
Width
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
150
150
A
o
o
Send Data
Delay
TE8
TE9
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
0
-
50
0
-
50
ns
ns
A
o
o
Bipolar Output
Delay
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
130
130
A
o
o
Enable Hold
Sync Hold
TE10
TE11
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
10
95
-
-
10
95
-
-
ns
ns
A
o
o
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
A
DECODER TIMING
o
o
Decoder
Clock
FDC
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
15
-
30
MHz
A
Frequency
o
o
Decoder Sync
Clock
FDS
FDD
TDR
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
-
2.5
1.25
-
-
-
5.0
2.5
-
MHz
MHz
ns
A
o
o
Decoder Data
Rate
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
A
o
o
Decoder Re-
set Pulse
Width
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
150
150
A
o
o
Decoder Re-
set Setup
Time
TDRS
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
75
-
75
-
ns
A
o
o
Decoder Re-
set Hold Time
TDRH
TMR
TD1
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
10
-
-
-
10
-
-
-
ns
ns
ns
ns
ns
A
o
o
Master Reset
Pulse
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
150
150
A
o
o
Bipolar Data
Pulse Width
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C TDC +10
TDC +10
(Note 1)
A
(Note 1)
o
o
One Zero
Overlap
TD3
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
TDC-10
(Note 1)
-
TDC-10
(Note 1)
A
o
o
Sync Delay
(ON)
TD6
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-20
110
-20
110
A
174
HD-15531/883
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
GROUPA
SUB-
HD-15531/883
HD-15531B/883
(NOTE 2)
PARAMETER SYMBOL
CONDI-TIONS
GROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
o
o
Take Data
Delay (ON)
TD7
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
0
110
0
110
ns
A
o
o
Serial Data
Out Delay
TD8
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
-
0
0
0
-
80
-
80
110
110
110
75
ns
ns
ns
ns
ns
A
o
o
Sync Delay
(OFF)
TD9
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
110
110
110
75
0
0
0
-
A
o
o
Take Data
Delay (OFF)
TD10
TD11
TD12
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
A
o
o
Valid Word
Delay
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
A
o
o
Sync Clock to
Shift Clock
Delay
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
A
o
o
Sync Data
Setup
TD13
VCC = 4.5V and 5.5V 9, 10, 11 -55 C ≤ T ≤ +125 C
75
-
75
-
ns
A
NOTES:
1. TDC = Decoder Clock Period = 1/FDC.
2. AC Testing as follows: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing reference levels: VCC/2;
Output load: CL = 50pF.
TABLE 3. HD-15531/883, HD-15531B/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN MAX UNITS
o
Input Capacitance
CI
VCC = OPEN, f = 1MHz, All measure-
ments referenced to device GND
1
T
= +25 C
-
-
-
25
25
10
pF
A
o
Input/Output Capaci-
tance
CIO
VCC = OPEN, f = 1MHz, All measure-
ments referenced to device GND
1
T
= +25 C
pF
A
o
o
Operating Power
Supply Current
ICCOP
VCC = 5.5V, f = 1MHz
1, 2
-55 C ≤ T ≤ +125 C
mA
A
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major
process and/or design changes.
2. Guaranteed but not 100% tested.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
Samples/5005
Samples/5005
SUBGROUPS
-
Interim Test
PDA
1, 7, 9
1
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
Groups C & D
175
HD-15531/883
Burn-In Circuit
HD1-15531/883 CERDIP
R
R
VCC
A
1
2
40
VCC
VCC
A
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
3
R
R
A
4
FO
A
5
GND
NC
A
R
R
R
R
R
V
6
CC
GND
VCC
FO
7
8
9
A
R
GND
10
11
12
13
14
15
16
17
18
19
20
VCC
GND
VCC
GND
R
R
R
R
R
GND
A
R
VCC
NC
VCC
A
A
R
R
R
R
R
GND
GND
VCC
VCC
GND
GND
R
R
VCC
R
A
R
GND
NOTES:
1. VCC = 5.5V ±0.5V.
2. VIH = 4.5V ±10%.
3. VIL = -0.2V to +0.4V.
4. R = 47kΩ ±5%.
5. F0 = 100kHz ±10%.
176
HD-15531/883
Die Characteristics
DIE DIMENSIONS:
155 x 195 x 19 ±1mils
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si-Al
WORST CASE CURRENT DENSITY:
2.0 x 10 A/cm
5
2
Thickness: 11kÅ ±2kÅ
Metallization Mask Layout
HD-15531/883
COUNT C1
COUNT C4
DATA SYNC
VALID WORD
TAKE DATA’ VCC
ENCODER CLK
TAKE DATA
COUNT C3
SERIAL DATA OUT
ENCODER SHIFT CLK
SEND CLK IN
SYNCHR DATA
SYNCHR DATA SEL
SYNCHR CLK
SEND DATA
DECODER CLK
ENCODER PARITY SEL
SYNC SEL
SYNCHR CLK SEL
BIPOLAR ZERO IN
BIPOLAR ONE IN
ENCODER ENABLE
SERIAL DATA IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
BIPOLAR ONE OUT
OUTPUT INHIBIT
TRANSITION SEL
COMMAND SYNC
BIPOLAR ZERO OUT
DECODER
PARITY SEL
COUNT
C0
MASTER COUNT
RESET
2
DECODER
RESET
GND
÷ 6 OUT
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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177
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