HD3-4702-9Z [INTERSIL]
CMOS Programmable Bit Rate Generator; CMOS可编程的位速率发生器
| 型号： | HD3-4702-9Z |
| 厂家： | 
Intersil |
| 描述： | CMOS Programmable Bit Rate Generator |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD-4702
®
Data Sheet
August 24, 2006
FN2954.2
CMOS Programmable Bit Rate Generator
Features
The HD-4702 Bit Rate Generator provides the necessary
clock signals for digital data transmission systems, such as a
UART. It generates 13 commonly used bit rates using an on-
chip crystal oscillator or an external input. For conventional
operation generating 16 output clock pulses per bit period,
the input clock frequency must be 2.4576MHz (i.e. 9600
Baud x 16 x 16, since there is an internal ³ 16 prescaler). A
lower input frequency will result in a proportionally lower
output frequency.
• HD-4702 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard Frequency
Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702 Controls up to Eight Transmission
Channels
The HD-4702 can provide multi-channel operation with a
minimum of external logic by having the clock frequency CO
and the ³ 8 prescaler outputs Q0, Q1, Q2 available externally.
All signals have a 50% duty cycle except 1800 Baud, which
has less than 0.39% distortion.
• Initialization Circuit Facilitates Diagnostic Fault Isolation
• On-Chip Input Pull-Up Circuit
Ordering Information
The four rate select inputs (S0-S3) select which bit rate is at
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes for
the HD-4702 do not select an internally generated frequency,
but select an input into which the user can feed either a
different frequency, or a static level (High or Low) to generate
“ZERO BAUD”.
TEMP.
RANGE
PART
NUMBER
PART
MARKING
PKG.
NO.
o
PACKAGE
( C)
PDIP
-40 to +85 HD3-4702-9
-40 to +85 HD3-4702-9Z*
HD3-4702-9
E16.3
PDIP
(Pb-free)
HD3-4702-9Z E16.3
The bit rates most commonly used in modern data terminals
(110, 150, 300, 1200, 2400 Baud) require that no more than
one input be grounded for the HD-4702, which is easily
achieved with a single 5-position switch.
CerDIP
SMD#
-55 to +125 5962-9051801MEA
F16.3
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
The HD-4702 has an initialization circuit which generates a
master reset for the scan counter. This signal is derived from
a digital differentiator that senses the first high level on the
CP input after the ECP input goes low. When ECP is high,
selecting the crystal input, CP must be low. A high level on
CP would apply a continuous reset. See Clock Modes and
Initialization below.
Truth Table
Pinout
TRUTH TABLE FOR RATE SELECT INPUTS
HD-4702 (16 Ld PDIP)
(Using 2.4576MHz Crystal)
TOP VIEW
S3
S2
S1
S0
OUTPUT RATE (Z)
Q0
Q1
Q2
1
2
3
4
5
6
7
8
16 V
CC
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
MUX Input (IM)
MUX Input (IM)
50 Baud
75 Baud
134.5 Baud
200 Baud
15 I
M
14 S0
13 S1
12 S2
11 S3
10 Z
L
E
H
H
H
H
L
L
L
L
H
H
H
H
CP
L
CP
H
H
L
600 Baud
O
X
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
I
X
L
9
CO
GND
H
H
L
L
H
H
150 Baud
110 Baud
NOTE: 19200 Baud by connecting Q2 to IM.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HD-4702
Pin Description
PIN NUMBER
TYPE
SYMBOL
DESCRIPTION
16
V
V
: Is the +5V power supply pin. A 0.1μF capacitor between pins 16 and 8 is
CC
CC
recommended for decoupling.
8
5
4
GND
CP
GROUND
I
I
EXTERNAL CLOCK INPUT
E
EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be
generated from the CP input.
CP
7
I
I
CRYSTAL INPUT
X
6
O
I
O
CRYSTAL DRIVE OUTPUT
MULTIPLEXED INPUT
BAUD RATE SELECT INPUTS
CLOCK OUTPUT
X
15
I
M
11, 12, 13, 14
I
S0 - S3
CO
9
O
O
O
1, 2, 3
10
Q
- Q
Z
SCAN COUNTER OUTPUTS
BIT RATE OUTPUT
0
2
CLOCK MODES AND INITIALIZATION
IX
E
CP
OPERATION
CP
H
L
L
Clocked from I
X
X
X
X
Clocked from CP
H
L
H
Continuous Reset
Reset During 1st CP = High
Time
H = HIGH Level
L = LOW Level
X = Don’t Care
= Clock Pulse
= 1st HIGH Level Clock Pulse after E
goes LOW
CP
NOTE: Actual output frequency is 16 times the indicated Output
Rate, assuming a clock frequency of 2.4576MHz.
FN2954.2
August 24, 2006
2
HD-4702
Block Diagram
7 5
1 5 0
3 0 0
6 0 0
1 2 0
2 4 0
0
0
0
0
4 8 0
9 6 0
FN2954.2
August 24, 2006
3
HD-4702
Other bit rate combinations can be generated by changing the
Scan Counter to Selector interconnection or by inserting logic
gates into this path.
Application Information
Single Channel Bit Rate Generator
Figure 1 shows the simplest application of the HD-4702. This
circuit generates one of five possible bit rates as determined by
the setting of a single pole, 5-position switch. The Bit Rate Out-
put (Z) drives one standard TTL load or four low power Schot-
tky loads over the full temperature range. The possible output
frequencies correspond to 110, 150, 300, 1200, and 2400
Baud. For many low cost terminals, these five bit rates are ade-
quate.
I
S0 S1 S2 S3
HD-4702
M
C
E
P
56pF
56pF
CP
I
X
†
10M
O
X
C
Q
Q
Q
2
Z
O
0
1
1
2
SPST SWITCH
2.4576 MHz
CRYSTAL
5
3
4
I
S0 S1 S2 S3
HD-4702
M
C
E
P
A0
A1
D
E
93L34
56pF
56pF
CP
A2 CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
I
X
†
10M
O
X
C
Q
Q
Q
2
Z
O
0
1
† See Table 1.
2.4576 MHz
CRYSTAL
OUTPUT
FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH
EIGHT SIMULTANEOUS FREQUENCIES
† See Table 1.
19200 Baud Operation
Though a 19200 Baud signal is not internally routed to the mul-
tiplexer, the HD-4702 can be used to generate this bit rate by
SWITCH POSITION
HD-4702 BIT RATE
connecting the Q output to IM input and applying select code.
An additional 2-input NOR gate can be used to retain the “Zero
Baud” feature on select code 1 for the HD-4702 (See Figure 3).
1
2
3
4
5
110 Baud
150 Baud
300 Baud
1200 Baud
2400 Baud
2
FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES
I
S0 S1 S2 S3
HD-4702
M
C
E
P
Simultaneous Generation of Several Bit Rates
56pF
56pF
CP
Figure 2 shows a simple scheme that generates eight bit rates
on eight output lines, using one HD-4702 and one 93L34 Bit
Addressable Latch. This and the following applications take
advantage of the built-in scan counter (prescaler) outputs. As
I
X
†
10M
O
X
C
Q
Q
Q
2
Z
O
0
1
2.4576 MHz
CRYSTAL
shown in the block diagram, these outputs (Q to Q ) go
0
2
through a complete sequence of eight states for every half-
period of the highest output frequency (9600 Baud). Feeding
these Scan Counter Outputs back to the Select Inputs of the
multiplexer causes the HD-4702 to interrogate sequentially
eight different frequency signals. The 93L34 8-bit addressable
Latch, addressed by the same Scan Counter Outputs, re-con-
verts the multiplexed single Output (Z) of the HD-4702 into
eight parallel output frequency signals. In the simple scheme of
Figure 2, input S3 is left open (HIGH) and the following bit rates
are generated:
OUTPUT
† See Table 1.
FIGURE 3. 19200 BAUD OPERATION
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETERS
Frequency
TYPICAL CRYSTAL SPEC
2.4576MHz “AT” Cut
250
Series Resistance (Max)
Unwanted Modes
-6.0dB (Min)
Q0: 110 Baud
Q3: 1800 Baud
Q6: 300 Baud
Q1: 9600 Baud
Q4: 1200 Baud
Q7: 150 Baud
Q2: 4800 Baud
Q5: 2400 Baud
Type of Operation
Load Capacitance
Parallel
32pF +0.5
FN2954.2
August 24, 2006
4
HD-4702
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θ
θ
JA
JC
o
o
CC
CERDIP Package. . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . .
78 C/W
23 C/W
o
90 C/W
N/A
Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300 C
o
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HD-4702-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
HD-4702-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
o
o
o
o
o
o
Electrical Specifications
V
= 5V ±10%, T = -40 C to +85 C (HD-4702-9), T = -55 C to +125 C (HD-4702-8)
CC
A
A
LIMITS
SYMBOL
PARAMETER
MIN
70%
MAX
UNITS
TEST CONDITIONS
V
Input High Voltage
Input Low Voltage
V
V
-
V
V
V
= 4.5V
= 4.5V
IH
CC
CC
CC
V
-
V
30%
V
IL
CC
V
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
-0.1
-
V
I
I
≤ -1μA, V
CC
= 4.5V, (Note 1)
= 4.5V, (Note 1)
OH1
CC
OH
OL
V
-
0.1
+1
+1
V
≤ +1μA, V
CC
OL1
I
-1
-1
μA
μA
V
V
= V , All 0ther Pins = 0V, V
CC CC
= 5.5V
= 5.5V
IH
IN
IN
I
= 0V, All Other Pins = V , V
CC CC
ILX
(l Input)
X
I
Input Low Current
(All Other Inputs)
-
-100
μA
mA
mA
mA
mA
mA
μA
V
= 0V, All Other Pins = V , V
CC CC
= 5.5V
IL
IN
(Note 2)
= V - 0.5, V
CC CC
I
Output High Current
(O )
X
-0.1
-1.0
-0.3
0.1
1.6
-
-
V
= 4.5V, Input at 0V
per Logic Function or Truth Table
OHX
OUT
or V
CC
I
I
Output High Current
(All Other Outputs)
-
V
or V
= 2.5V, V
= 4.5V, Input at 0V
OH1
OH2
OUT
CC
per Logic Function or Truth Table
CC
Output High Current
(All Other Outputs)
-
V
or V
= V
-0.5, V = 4.5V, Input at 0V
CC
OUT
CC
per Logic Function or Truth Table
CC
I
Output Low Current
(O )
X
-
V
= 0.4V, V
= 4.5V, Input at 0V
OLX
OUT
or V
CC
per Logic Function or Truth Table
CC
= 0.4V, V
I
Output Low Current
(All Other Outputs)
-
V
= 4.5V Input, at 0V
OL
OUT
or V
CC
per Logic Function or Truth Table
CC
I
Supply Current
(Static)
1500
1000
E
= V , CP = 0V, V
= 5.5V,
CC
CC
CP
CC
All Other Inputs = GND, (Note 2)
-
μA
E
= V , CP = 0V, V
= 5.5V,
CC
CP
CC
All Other Inputs = V , (Note 2)
CC
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs
except I .
X
FN2954.2
August 24, 2006
5
HD-4702
o
o
o
o
Electrical Specifications
V
= 5V ±10%, T = -40 C to +85 C (HD-4702-9), T = -55 C to +125 C (HD-4702-8)
CC
A
A
LIMITS
TEST
SYMBOL
AC PARAMETER
MIN
MAX
350
275
260
220
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CONDITIONS
t
t
t
t
t
t
t
t
Propagation Delay, I to CO
X
-
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
-
Propagation Delay, CP to CO
Propagation Delay, CO to Qn
Propagation Delay, CO to Z
-
-
-
(Note 2)
-
(Note 2)
-
85
-
75
V
= 4.5V
CC
≤ 7pF on O
t
t
Output Transition Time (Except O )
X
-
160
TLH
THL
C
L
X
C
= 50pF
L
-
75
(Note 1)
t
Set-Up Time, Select to CO
Hold Time, Select to CO
350
-
s
t
0
-
h
t
Set-Up Time, I to CO
350
-
s
M
t
Hold Time, I to CO
M
0
-
h
t
(L)
Minimum Clock Pulse Width, Low (Notes 3, 4)
Minimum Clock Pulse Width, High (Notes 3, 4)
120
-
wCP
t
(H)
120
-
-
wCP
t
(L)
Minimum I Pulse Width, Low (Note 4)
160
wCP
X
t
(H)
Minimum I Pulse Width, High (Note 4)
160
-
wCP
X
t
t
t
t
t
t
t
t
Propagation Delay I to CO
X
-
-
-
-
-
-
-
-
-
-
300
250
215
195
(Note 2)
(Note 2)
75
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
Propagation Delay CP to CO
Propagation Delay CO to Qn
Propagation Delay CO to Z
V
= 4.5V
CC
≤ 7pF on O
C
L
X
C
= 15pF
L
(Note 1)
65
t
t
Output Transition Time (Except O )
80
TLH
THL
X
40
NOTES:
1. Propagation Delays (t
and t
) and Output Transition Times (t
and t
) will change with Output Load Capacitance (C ). Setup Times
THL L
PLH
PHL
TLH
(t ), Hold Times (t ), and Minimum Pulse Widths (t ) do not vary with load capacitance.
s
h
w
2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns.
3. The first High Level Clock Pulse after E goes Low must be at least 350ns long to guarantee reset of all Counters.
CP
4. It is recommended that input rise and fall times to the clock inputs (CP, I ) be less than 15ns.
X
FN2954.2
August 24, 2006
6
HD-4702
o
Capacitance
T
= +25 C; Frequency = 1MHz
A
SYMBOL
PARAMETER
Input Capacitance
TYPICAL
UNITS
pF
CONDITIONS
C
7
All measurements are referenced the
device GND
IN
C
Output Capacitance
15
pF
OUT
Switching Waveforms
t
(H)
t (L)
W
W
50%
50%
50%
CP/I
X
50%
CO
t
t
h
s
I
/S
N
50%
M
NOTE:
1. Setup and Hold times are shown as positive values but may be specified as negative values.
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
V
OH
IH
50%
50%
V
V
OL
IL
NOTE:
1. AC Testing: All input signals must switch between V and V Input rise and fall times are driven at 1ns per volt.
IL IH.
FN2954.2
August 24, 2006
7
HD-4702
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
INCHES
MILLIMETERS
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
2. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
5. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
6. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
7. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
8. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
9. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
10. N is the maximum number of terminal positions.
11. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN2954.2
August 24, 2006
8
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