HD3-6402R-9 [INTERSIL]
CMOS Universal Asynchronous Receiver Transmitter (UART); CMOS通用异步收发器（ UART ）
| 型号： | HD3-6402R-9 |
| 厂家： | 
Intersil |
| 描述： | CMOS Universal Asynchronous Receiver Transmitter (UART) |
| 文件： | 总7页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
HD-6402
CMOS Universal Asynchronous
Receiver Transmitter (UART)
March 1997
Features
Description
• 8.0MHz Operating Frequency (HD-6402B)
• 2.0MHz Operating Frequency (HD-6402R)
• Low Power CMOS Design
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmit-
ting 5-bit code.
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by compar-
ison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.
Ordering Information
PACKAGE
Plastic DIP
TEMPERATURE RANGE
2MHz = 125K BAUD
HD3-6402R-9
8MHz = 500K BAUD
HD3-6402B-9
PKG. NO.
E40.6
o
o
-40 C to +85 C
o
o
CERDIP
SMD#
-40 C to +85 C
HD1-6402R-9
HD1-6402B-9
F40.6
F40.6
o
o
-55 C to +125 C
5962-9052501MQA
5962-9052502MQA
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
V
1
2
3
4
5
6
7
8
9
40 TRC
CC
NC
GND
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
RBR3 10
RBR2 11
RBR1 12
PE 13
FE 14
OE 15
SFD 16
RRC 17
DRR 18
DR 19
RRI 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 2956.1
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
1
HD-6402
Functional Diagram
(32)
(30)
(28)
(26)
TBR8 (33)
(31)
(29)
(27)
TBR1
(24) TRE
TRANSMITTER BUFFER REGISTER
PARITY
(22) TBRE †
LOGIC
STOP
START
TRANSMITTER REGISTER
MULTIPLEXER
(23) TBRL
(40) TRC
TRANSMITTER
TIMING AND
CONTROL
(25) TRO
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
(36) SBS
(16) SFD
(39) EPE
(35) PI
CONTROL
REGISTER
(20) RRI
MULTIPLEXER
(17) RRC
(18) DRR
START
LOGIC
RECEIVER
TIMING AND
CONTROL
RECEIVER REGISTER
STOP
LOGIC
PARITY
LOGIC
(19) DR †
RECEIVER BUFFER REGISTER
3-STATE
(4) RRD
(16) SFD
BUFFERS
† RBR8
† RBR1
† THESE OUTPUTS ARE
THREE-STATE
† OE
(15)
† FE
(14)
† PE
(13)
(5) (6) (7) (8) (9) (10) (11) (12)
Control Definition
CONTROL WORD
CHARACTER FORMAT
DATA BITS PARITY BIT
ODD
CLS 2
CLS 1
PI
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
EPE
0
SBS
0
START BIT
STOP BITS
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1.5
1
0
1
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
ODD
EVEN
EVEN
NONE
NONE
ODD
1
0
1
1
1.5
1
X
X
0
0
1
1.5
1
0
0
1
ODD
2
1
0
EVEN
EVEN
NONE
NONE
ODD
1
1
1
2
X
x
0
1
1
2
0
0
1
0
1
ODD
2
1
0
EVEN
EVEN
NONE
NONE
ODD
1
1
1
2
X
x
0
1
1
2
0
0
1
0
1
ODD
2
1
0
EVEN
EVEN
NONE
NONE
1
1
1
2
X
x
0
1
1
2
2
HD-6402
Pin Description
PIN TYPE SYMBOL
DESCRIPTION
PIN TYPE SYMBOL
DESCRIPTION
Positive Voltage Supply
No Connection
24
O
TRE
A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
1
2
3
4
V
†
CC
NC
GND Ground
25
26
O
I
TRO Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
I
RRD A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
TRB1 Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
5
O
RBR8 The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. Word for-
mats less than 8 characters are right justified to
RBR1.
27
28
29
30
31
32
33
34
I
I
I
I
I
I
I
I
TBR2 See Pin 26-TBR1.
TBR3 See Pin 26-TBR1.
TBR4 See Pin 26-TBR1.
TBR5 See Pin 26-TBR1.
TBR6 See Pin 26-TBR1.
TBR7 See Pin 26-TBR1.
TBR8 See Pin 26-TBR1.
6
7
O
O
O
O
O
O
O
O
RBR7 See Pin 5-RBR8
RBR6 See Pin 5-RBR8
RBR5 See Pin 5-RBR8
RBR4 See Pin 5-RBR8
RBR3 See Pin 5-RBR8
RBR2 See Pin 5-RBR8
RBR1 See Pin 5-RBR8
8
9
10
11
12
13
CRL
A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
PE
A high level on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
14
15
O
O
FE
A high level on FRAMING ERROR indicates the
first stop bit was invalid.
35
36
I
I
PI
A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
OE
A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
SBS
A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
37
I
CLS2 These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
16
I
SFD
A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
17
18
19
I
I
RRC The Receiver register clock is 16X the receiver
data rate.
38
39
I
I
CLS1 See Pin 37-CLS2.
EPE
When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
DRR A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
O
DR
A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
40
I
TRC
The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
† A 0.1µF decoupling capacitor from the V
ommended.
pin to the GND is rec-
CC
20
21
I
I
RRI
MR
Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
V
and t . Wait 18 clock cycles after the falling
MR
IH
edge of MR before beginning operation.
22
23
O
I
TBRE A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.
TBRL A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
3
HD-6402
HD-6402
Transmitter Operation
The transmitter section accepts parallel data, formats the data The rising edge of TBRL clears Transmitter Buffer Register
and transmits the data in serial form on the Transmitter Regis- Empty (TBRE). 0 to 1 Clock cycles later, data is transferred
ter Output (TRO) terminal (See serial data format). Data is to the transmitter register, the Transmitter Register Empty
loaded from the inputs TBR1-TBR8 into the Transmitter Buffer (TRE) pin goes to a low state, TBRE is set high and serial
Register by applying a logic low on the Transmitter Buffer data information is transmitted. The output data is clocked
Register Load (TBRL) input (A). Valid data must be present at by Transmitter Register Clock (TRC) at a clock rate 16 times
least t prior to and t
following the rising edge of TBRL. If the data rate. A second low level pulse on TBRL loads data
set hold
words less than 8 bits are used, only the least significant bits into the Transmitter Buffer Register (C). Data transfer to the
are transmitted. The character is right justified, so the least transmitter register is delayed until transmission of the cur-
significant bit corresponds to TBR1 (B).
rent data is complete (D). Data is automatically transferred to
the transmitter register and transmission of that character
begins one clock cycle later.
1
TBRL
TBRE
TRE
1/2 CLOCK
0 TO 1 CLOCK
DATA
TRO
END OF LAST STOP BIT
A
B
C
D
FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE)
Receiver Operation
Data is received in serial form at the Receiver Register Input character is right justified to the least significant bit RBR1. A
(RRI). When no data is being received, RRI must remain logic high on Overrun Error (OE) indicates overruns. An
high. The data is clocked through the Receiver Register overrun occurs when DR has not been cleared before the
Clock (RRC). The clock rate is 16 times the data rate. A low present character was transferred to the RBR. One clock
level on Data Received Reset (DRR) clears the Data cycle later DR is reset to a logic high, and Framing Error
Receiver (DR) line (A). During the first stop bit data is trans- (FE) is evaluated (C). A logic high on FE indicates an invalid
ferred from the Receiver Register to the Receiver Buffer stop bit was received, a framing error. A logic high on Parity
Register (RBR) (B). If the word is less than 8 bits, the Error (PE) indicates a parity error.
unused most significant bits will be a logic low. The output
BEGINNING OF FIRST STOP BIT
RRI
RBR1-8, OE, PE
7 1/2 CLOCK CYCLES
DRR
DR
FE
1 CLOCK CYCLE
A
B
C
FIGURE 2. RECEIVER TIMING (NOT TO SCALE)
4
HD-6402
START BIT
5-8 DATA BITS
1, 11/2 OR 2 STOP BITS
†
LSB
MSB
PARITY
† IF ENABLED
FIGURE 3. SERIAL DATA FORMAT
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have symmetrical square wave, the center of the start bit will be
occurred as much as one clock cycle before it was detected, located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
as indicated by the shaded portion (A). The center of the start receiver margin of 46.875%. The receiver begins searching
bit is defined as clock count 7 1/2. If the receiver clock is a for the next start bit at the center of the first stop bit.
CLOCK
COUNT 71/2 DEFINED
CENTER OF START BIT
START
A
RRI INPUT
71/2 CLOCK CYCLES
81/2 CLOCK CYCLES
FIGURE 4.
Interfacing with the HD-6402
TRANSMITTER
TBR1
RECEIVER
RB1
RS232
DRIVER
RS232
RECEIVER
TRO
RRI
TBR8
RB8
CONTROL
CONTROL
DIGITAL
SYSTEM
DIGITAL
SYSTEM
HD-6402
HD-6402
CONTROL
RB1
CONTROL
TBR1
RS232
RECEIVER
RS232
DRIVER
RRI
TRO
RB8
TBR8
RECEIVER
TRANSMITTER
FIGURE 5. TYPICAL SERIAL DATA LINK
5
HD-6402
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.5V to V +0.5V
Thermal Resistance (Typical)
CERDIP Package . . . . . . . . . . . . . . . . 50 C/W
PDIP Package . . . . . . . . . . . . . . . . . . . 50 C/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 Gates
θ
θ
JC
12 C/W
N/A
JA
o
o
CC
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
o
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HD-6402R-9, HD6402B-9 . . . . . . . . . . . . . . . . . . .-40 C to +85 C
o
o
o
o
DC Electrical Specifications V = 5.0V ± 10%, T = -40 C to +85 C (HD-6402R-9, HD-6402B-9)
CC
A
LIMITS
SYMBOL
PARAMETER
MIN
2.0
-
MAX
-
UNITS
CONDITIONS
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Input Leakage Current
V
V
V
V
V
= 5.5V
= 4.5V
IH
CC
V
0.8
1.0
IL
CC
II
-1.0
3.0
µA
V
= GND or V , V
= 5.5V
= -2.5mA, V = 4.5V
CC
IN
CC CC
V
Logical ‘‘1’’ Output Voltage
-
-
I
I
OH
OH
OH
V
-0.4
= -100µA
CC
V
I
Logical ‘‘0’’ Output Voltage
Output Leakage Current
Standby Supply Current
-
-1.0
-
0.4
1.0
V
I
= +2.5mA, V = 4.5V
CC
OL
OL
µA
µA
V
= GND or V , V
CC CC
= 5.5V
O
O
ICCSB
100
V
= GND or V ; V
CC CC
= 5.5V,
IN
Output Open
ICCOP
Operating Supply Current (See Note)
-
2.0
mA
V
V
= 5.5V, Clock Freq. = 2MHz,
or GND, Outputs Open
CC
CC
= V
IN
NOTE: Guaranteed, but not 100% tested
o
Capacitance T = +25 C
A
LIMIT
PARAMETER
Input Capacitance
SYMBOL
CIN
CONDITIONS
TYPICAL
UNITS
Freq. = 1MHz, all measurements are referenced to de-
vice GND
25
25
pF
pF
Output Capacitance
COUT
o
o
AC Electrical Specifications V = 5.0V ± 10%, T = -40 C to +85 C (HD-6402R-9, HD6402B-9)
CC
A
LIMITS HD-6402R LIMITS HD-6402B
SYMBOL
PARAMETER
Clock Frequency
MIN
D.C.
150
150
50
MAX
MIN
D.C.
75
MAX
UNITS
MHz
ns
CONDITIONS
C = 50pF
(1) fCLOCK
2.0
8.0
L
See Switching Waveform
(2) t
(3) t
(4) t
(5) t
(6) t
Pulse Widths, CRL, DRR, TBRL
Pulse Width MR
-
-
-
PW
-
150
20
ns
MR
Input Data Setup Time
Input Data Hold Time
Output Enable Time
-
-
-
ns
SET
HOLD
EN
60
20
-
ns
-
160
-
35
ns
6
HD-6402
Switching Waveforms
CLS1, CLS2, SBS, PI, EPE
VALID DATA
SFD
RRD
TBR1 - TBR8
TBRL
VALID DATA
STATUS OR
RBR1 - RBR8
CRL
t
(4)
SET
HOLD
(5)
t
HOLD
(5)
t
(4)
SET
t
EN
(6)
t
t
PW
(2)
t
PW
(2)
FIGURE 6. DATA INPUT CYCLE
FIGURE 7. CONTROL REGISTER LOAD
CYCLE
FIGURE 8. STATUS FLAG OUTPUT
ENABLE TIME OR DATA OUT-
PUT ENABLE TIME
A.C. Testing Input, Output Waveform
INPUT
OUTPUT
V
+ 20% V
V
IH
IH
OH
1.5V
1.5V
V
- 50% V
V
IL
IL
OL
FIGURE 9.
NOTE: A.C. Testing: All input signals must switch between V - 50% V and V + 20% V . Input rise and fall times are driven at 1ns/V.
IL IL IH IH
Test Circuit
OUT
C
L
(SEE NOTE)
FIGURE 10.
NOTE: Includes stray and jig capacitance, C = 50pF.
L
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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