HI20201JCB [INTERSIL]
10-Bit, 160 MSPS, Ultra High Speed D/A Converter; 10位， 160 MSPS ，超高速D / A转换器
| 型号： | HI20201JCB |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, 160 MSPS, Ultra High Speed D/A Converter |
| 文件： | 总11页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI20201
10-Bit, 160 MSPS,
Ultra High Speed D/A Converter
August 1997
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz The HI20201 is a 160MHz ultra high speed D/A converter. The
converter is based on an R/2R switched current source archi-
tecture that includes an input data register with a complement
• Resolution (HI20201) . . . . . . . . . . . . . . . . . . . . . . . 10-Bit
feature and is Emitter Coupled Logic (ECL) compatible.
• Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB
• Low Glitch Noise
The HI20201 is available in a commercial temperature range
and offered in a 28 lead plastic SOIC (300 mil) and a 28 lead
plastic DIP package.
• Analog Multiplying Function
• Low Power Consumption . . . . . . . . . . . . . . . . . .420mW
• Evaluation Board Available
Ordering Information
• Direct Replacement for Sony CX20201-1, CX20202-1
PART
NUMBER
TEMP.
o
RANGE ( C)
-20 to 75
-20 to 75
25
PACKAGE
28 Ld SOIC
28 Ld PDIP
Evaluation Kit
PKG. NO.
M28.3A-S
E28.6A-S
Applications
HI20201JCB
HI20201JCP
HI20201-EV
• Wireless Communications
• Signal Reconstruction
• Direct Digital Synthesis
• High Definition Video Systems
• Digital Measurement Systems
• Radar
Pinout
HI20201
(PDIP, SOIC)
TOP VIEW
1
2
28 AV
SS
(MSB) D9
D8
27
V
REF
3
26 AV
EE
D7
25 NC
24 NC
23 NC
22 NC
21 NC
4
D6
5
D5
6
D4
7
D3
8
D2
9
20
I
D1
OUT
10
11
12
13
14
19 NC
18 AV
(LSB) D0
NC
SS
17 DV
NC
SS
16 COMPL
CLK
CLK
15 DV
EE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number 3581.5
10-1197
HI20201
Typical Application Circuit
HI20201
.
(28) AV
SS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9 (MSB) (1)
1.5kΩ
1kΩ
D8 (2)
~2.7V
D7 (3)
D6 (4)
D5 (5)
D4 (6)
D3 (7)
D2 (8)
D1 (9)
D0 (LSB) (10)
(11)
(27) V
REF
2kΩ
DIGITAL
DATA
(ECL)
TL431CP
-5.2V
(26) AV
EE
0.047µF
1.0µF
75Ω COAX CABLE
D/A OUT
(20) I
(12)
OUT
(18, 19, 21-25) NC
82Ω 82Ω
(17) DV
SS
CLK (13)
CLK (14)
CLK
(16) COMPL
-1.3V
1.0µF
3.6kΩ
0.047µF
131Ω
-5.2V
(15) DV
EE
131Ω
-5.2V
Functional Block Diagram
(LSB) D0
D1
6 LSBs
CURRENT
CELLS
D2
D3
R/2R
NET/WORK
D4
INPUT
8-BIT
REGISTER
BUFFER
D5
15
15
15
15
15
D6
D7
UPPER
4-BIT
ENCODER
15
15
D8
15
15
I
OUT
(MSB) D9
SWITCHED
CURRENT
CELLS
COMPL
BIAS CURRENT
GENERATOR
CLK
CLK
CLOCK
BUFFER
V
REF
10-1198
HI20201
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage DV to DV
. . . . . . . . . . . . . . . . . . . -7.0V
. . . . . . . . . . . . . . . . . . -7.0V
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
EE
SS
to AV
Analog Supply Voltage AV
DD
SS
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
58
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DV
Reference Input Voltage . . . . . . . . . . . . . . . . . . . . . . +0.3 to AV
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
V
V
EE
o
EE
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
o
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage
Reference Input Voltage, V
. . . . . . . . V + 0.5V to V + 1.4V
EE EE
REF
AV , DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V Load Resistance, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥75Ω
EE
EE
L
AV - DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Output Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V
EE EE
OUT
o
o
Digital Input Voltage
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20 C to 75 C
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V
IH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V
IL
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
T = 25 C, AV = DV = -5.2V, AGND = DGND = 0V, R = ∞, V
= -1V
A
EE
EE
L
OUT
HI20201JCB/JCP
TYP
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
MAX
UNITS
10
-
-
-
-
Bits
LSB
LSB
LSB
LSB
mA
Integral Linearity Error, INL
Differential Linearity Error, DNL
f
f
= 160MHz (End Point)
= 160MHz
±1.0
±0.50
-
S
-
-
S
Offset Error, V
OS
(Adjustable to Zero)
(Note 3)
(Note 3)
-
7
-
Full Scale Error, FSE (Adjustable to Zero)
Full Scale Output Current, I
-
±102
20
-
-
FS
DYNAMIC CHARACTERISTICS
Throughput Rate
See Figure 11
160
-
-
-
-
MHz
pV/s
Glitch Energy, GE
R
= 75Ω
15
OUT
REFERENCE INPUT
Voltage Reference Input Range
Reference Input Current
With Respect to AV
+0.5
-0.1
-
-
+1.4
-3.0
-
V
EE
V
= -4.58V
-0.4
14.0
µA
REF
Voltage Reference to Output Small
Signal Bandwidth
-3dB point 1V
Input
MHz
P-P
Output Rise Time, t
R
R
= 75Ω
-
-
1.5
1.5
-
-
ns
ns
r
LOAD
LOAD
Output Fall Time, t
= 75Ω
f
DIGITAL INPUTS
Input Logic High Voltage, V
IH
(Note 2)
(Note 2)
-1.0
-0.89
-1.75
1.5
V
V
Input Logic Low Voltage, V
-1.6
6.0
IL
Input Logic Current, I , I
IL IH
(For D9 thru D6, COMPL)
V
= -0.89V, V = -1.75V (Note 2)
IL
0.1
0.1
µA
IH
Input Logic Current, I , I (For D5 thru D0)
IL IH
V
= -0.89V, V = -1.75V (Note 2)
IL
0.75
3.0
µA
IH
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 11
See Figure 11
See Figure 11
See Figure 11
5
1
-
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
-
HLD
Propagation Delay Time, t
1
3.8
5.2
PD
Settling Time, t
(to / LSB)
-
SET
2
10-1199
HI20201
o
Electrical Specifications
T = 25 C, AV = DV = -5.2V, AGND = DGND = 0V, R = ∞, V = -1V (Continued)
EE EE OUT
A
L
HI20201JCB/JCP
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
POWER SUPPLY CHARACTERISITICS
I
-60
-
-75
-90
mA
EE
Power Dissipation
NOTES:
75Ω load
420
470
mW
2. Parameter guaranteed by design or characterization and not production tested.
3. Excludes error due to reference drift.
4. Electrical specifications guaranteed only under the stated operating conditions.
Timing Diagram
CLK
CLK
DATA
t
t
HD
SU
N
N + 1
t
t
D
D
0V
N + 1
90%
N
D/A OUT
-1V
50%
10%
t
t
f
r
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
Pin Descriptions
28 PIN SOIC
PIN NAME
PIN DESCRIPTION
1-10
D0 (LSB)-D9 (MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 9, the Most Significant Bit.
11, 12, 19, 21- 25
NC
No Connect, not used.
13
14
15
16
Negative Differential Clock Input.
Positive Differential Clock Input
Digital (ECL) Power Supply -4.75V to -7V.
CLK
CLK
DV
EE
COMPL
Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the
input buffer. When cleared to a (ECL) logic Low the input data is not complemented.
17
18
20
26
27
28
DV
AV
Digital Ground.
SS
Analog Ground.
SS
I
Current Output Pin.
OUT
AV
Analog Supply -4.75V to -7V.
Input Reference Voltage used to set the output full scale range.
Analog Ground.
EE
V
REF
AV
SS
10-1200
HI20201
Typical Performance Curves
1.05
1.00
0.95
-2.0
o
T
= 25 C, V = -5.2V
EE
A
LINEAR AREA
R
= 10kΩ
L
R
= 10kΩ
L
-1.0
R
= 75Ω
L
R
= 75Ω
L
0
0.5
-20
0
20
40
60
80
1.0
1.5
o
AMBIENT TEMPERATURE ( C)
V
- V (V)
EE
REF
FIGURE 2. V
RATIO vs (V
REF
- V
EE
)
FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT
TEMPERATURE
O(FS)
0
-10
-20
f
= 100MHz
CLK
10.0
8.0
6.0
4.0
2.0
GAIN
0
PHASE
-90
-180
10K
100K
1M
10M
100M
-50
0
50
100
o
MULTIPLYING INPUT SIGNAL FREQUENCY (Hz)
CASE TEMPERATURE ( C)
FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING
INPUT SIGNAL FREQUENCY
FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE (FULL
SCALE - 1023mV)
10-1201
HI20201
Detailed Description
The HI20201 is a 10-bit, current output D/A converter. The 01 1111 1111 to 10 0000 0000. But in the HI20201 the glitch
DAC can run at 160MHz and is ECL compatible. The archi- is moved to the 00 0001 1111 to 11 1110 0000 transition.
tecture is segmented/R2R combination to reduce glitch and This is achieved by the split R2R/segmented current source
improve linearity.
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant
over the entire output range. By making the glitch a constant
size over the entire output range this effectively integrates
this error out of the end application.
Architecture
The HI20201 is a combined R2R/segmented current source
design. The 6 least significant bits of the converter are
derived by a traditional R2R network to binary weight the
1mA current sources. The upper 4 most significant bits are
implemented as segmented or thermometer encoded cur-
rent sources. The encoder converts the incoming 4 bits to 15
control lines to enable the most significant current sources.
The thermometer encoder will convert binary to individual
control lines. See Table 1.
In measuring the output glitch of the HI20201 the output is
terminated into a 75Ω load. The glitch is measured at the
major carry’s throughout the DAC’s output range.
HI20201
34MHz
LOW PASS
FILTER
TABLE 1. THERMOMETER ENCODER
THERMOMETER CODE
SCOPE
(20) I
OUT
50Ω
75Ω
MSB
0
BIT 8
BIT 7
BIT 6
1 = ON, 0 = OFF, I - I
15
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000 0000 0000 0000
000 0000 0000 0001
000 0000 0000 0011
000 0000 0000 0111
000 0000 0000 1111
000 0000 0001 1111
000 0000 0011 1111
000 0000 0111 1111
000 0000 1111 1111
000 0001 1111 1111
000 0011 1111 1111
000 0111 1111 1111
000 1111 1111 1111
001 1111 1111 1111
011 1111 1111 1111
111 1111 1111 1111
0
FIGURE 6. HI20201 GLITCH TEST CIRCUIT
0
0
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 7 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
0
0
0
0
1
1
1
1
1
1
A (mV)
GLITCH ENERGY = (a x t)/2
1
1
The architecture of the HI20201 is designed to minimize
glitch while providing a manufacturable 10-bit design that
does not require laser trimming to achieve good linearity.
t (ns)
FIGURE 7. GLITCH ENERGY
Glitch
Glitch is caused by the time skew between bits of the Setting Full Scale
incoming digital data. Typically the switching time of digital
The full scale output voltage is set by the Voltage Reference
pin (27). The output voltage performance will vary as shown
in Figure 2.
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). In an ECL system
where the logic levels switch from one non-saturated level to
another, the switching times can be considered close to The output structure of the HI20201 can handle down to a
symmetrical. This helps to reduce glitch in the D/A. Unequal 75Ω load effectively. To drive a 50Ω load Figure 8 is sug-
delay paths through the device can also cause one current gested. Note the equivalent output load is ~75Ω.
source to change before another. To minimize this the Intersil
HI20201 employs an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
10-1202
HI20201
Clock Phase Relationship
The HI20201 is designed to be operated at very high speed
(i.e., 160MHz). The clock lines should be driven with
ECL100K logic for full performance. Any external data
drivers and clock drivers should be terminated with 50Ω to
minimize reflections and ringing.
HI20201
(20) I
50Ω COAX CABLE
39Ω
D/A OUT
OUT
100Ω
Internal Data Register
(18, 19, 21-25) NC
The HI20201 incorporates a data register as shown in the
Functional Block Diagram. This register is updated on the
rising edge of the CLK line. The state of the Complement bit
(COMPL) will determine the data coding. See Table 2.
FIGURE 8. HI20201 DRIVING A 50Ω LOAD
Variable Attenuator Capability
The HI20201 can be used in a multiplying mode with a
TABLE 2. INPUT CODING TABLE
OUTPUT CODE
variable frequency input on the V
pin. In order for the
REF
part to operate correctly a DC bias must be applied and the
incoming AC signal should be coupled to the V pin. See
INPUT CODE
00 0000 0000
10 0000 0000
11 1111 1111
COMPL = 1
COMPL = 0
REF
0
-0.5
-1
-1
-0.5
0
Figure 13 for the application circuit. The user must first
adjust the DC reference voltage. The incoming signal must
be attenuated so as not to exceed the maximum (+1.4V) and
minimum (+0.5V) reference input. The typical output Small
Signal Bandwidth is 14MHz.
Thermal Considerations
Integral Linearity
The temperature coefficient of the full scale output voltage
and zero offset voltage depend on the load resistance con-
The Integral Linearity is measured using the End Point
method. In the End Point method the gain is adjusted. A line
is then established from the zero point to the end point or
Full Scale of the converter. All codes along the transfer curve
must fall within an error band of 1 LSB of the line. Figure 10
shows the linearity test circuit.
nected to I
. The larger the load resistor, the better (i.e.,
OUT
smaller) the temperature coefficient of the D/A. See Figure 3
in the performance curves section.
Noise Reduction
Differential Linearity
Digital switching noise must be minimized to guarantee system
specifications. Since 1 LSB corresponds to 1mV for 10-bit reso-
lution, care must be taken in the layout of a circuit board.
The Differential Linearity is the difference from the ideal step.
To guarantee monotonicity a maximum of 1 LSB differential
error is allowed. When more than 1 LSB is specified the con-
verter is considered to be missing codes. Figure 10 shows
the linearity test circuit.
Separate ground planes should be used for DV
SS
and
AV . They should be connected back at the power supply.
SS
Separate power planes should be used for DV and AV
EE
.
EE
They should be decoupled with a 1µF tantalum capacitor
and a ceramic 0.047µF capacitor positioned as close to the
body of the IC as possible.
10-1203
HI20201
Test Circuits
S1
S2
S3
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
a
b
a
S20
S16
a
b
I6
3
I1
5.2V
b
S4
S5
S6
S7
S8
S9
S10
4.56V
4
5
I2
S11
b
6
a
7
-0.89V
-1.75V
8
1mA
b
a
b
a
S19
a
b
9
10
11
12
13
14
V1
b
-0.89V OR
-1.75V
S17
a
b
S12
a
b
a
S18
S14
I5
I3
I4
a
a
b
b
a
S13
S15
5.2V
b
b
-0.89V
-1.75V
FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE
LINEARITY ERRORS ARE MEASURED AS FOLLOWS
S1
0
S2
0
S3
0
• • • •
• • • •
• • • •
• • • •
S9
0
S10 D/A OUT
0
1
0
V
V
V
0
1
2
0
0
0
0
“1”
S1
S2
S3
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0
0
0
1
†
•
•
•
•
“0”
10K
•
•
0.89V
1.75V
3
1
1
1
• • • •
1
1
V
1023
5.2V
S4
S5
S6
S7
S8
S9
S10
4
INTEGRAL
LINEARITY ERROR
DIFFERENTIAL
LINEARITY ERROR
5
6
V
V
V
V
V
V
V
V
V
V
0
10-BIT
DATA
V
V
V
V
- V
- V
- V
- V
- V
- V
- V
- V
- V
1
1
2
4
8
0
7
2
1
D/A
OUT
8
4
3
8
7
9
V
16
32
64
128
192
16
32
64
15
31
63
127
191
V
V
V0
10
11
12
13
14
V
V
128
192
•
•
•
•
•
•
1.3V
5.2V
V
V
V
- V
960
960
959
1 SHOT
CLK
1023
Error at individual measurement points are calculated
according to the following definition.
†Adjust so that the full scale of DC voltage at pin 20 becomes
1.023V, that is, to satisfy V - V = 1.023V.
(V
- V )/1023 = V
/1023 ≡ 1 LSB.
0(FS)
1023
0
O
1023
FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR
10-1204
HI20201
Test Circuits (Continued)
1
/
HD100151
6
B
10kΩ
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MSB
82
82
D
Q
Q
3
131
131
4
-5.2V
-5.2V CLKF
-5.2V
5
TO PG
6
-1.3V
7
50Ω
8
C
1
50Ω
39
9
OUT
HD100116
TO SCOPE
82
10
11
12
13
14
LSB
100
1
CLKF
470
131
82
82
A
DL
CLK
CLK
1
-5.2V
131
131
131
DL: Delay line
Capacitors are 0.047µF ceramic chip capacitors unless otherwise specified.
-1.3V
-5.2V
FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND
SETTLING TIME CIRCUIT
Measuring Settling Time
Settling time is measured as follows. The relationship
between V and V
as shown in the D/A output waveform
0(FS)
in Figure 12 is expressed as
-tτ
V = V
(1 - e ).
0(FS)
The settling time for respective accuracy of 10, 9 and 8-bit is
specified as
τ
V = 0.9995 V
V = 0.999 V
V = 0.999 V
0(FS)
0(FS)
0(FS)
which results in the following:
t
t
t
= 7.60τ for 10-bit,
= 6.93τ for 9-bit, and
= 6.24τ for 8-bit,
V
= 1V
S
S
S
0(FS)
V
Rise time (t ) and fall time (t ) are defined as the time interval
r
f
to slew from 10% to 90% of full scale voltage (V
):
0(FS)
τ
V = 0.1 V
V = 0.9 V
0(FS)
0(FS)
FIGURE 12. D/A OUTPUT WAVEFORM
and calculated as t = t = 2.20τ.
r
f
The settling time is obtained by combining these expressions:
t
t
t
= 3.45t for 10-bit,
r
S
S
S
= 3.15t for 9-bit, and
r
= 6.24t for 8-bit
r
10-1205
HI20201
Test Circuits (Continued)
Adjust so that the voltage at point B
becomes -1V with no AC input.
“1”
10kΩ
0.1µF
OSC
1
2
28
27
26
25
24
23
22
21
0.047µ
51
3
A
4
-5.2V
5
6
7
8
B
TO SCOPE
9
20
19
18
17
16
15
10
11
12
13
14
CLK
CLK
A GND D GND
-5.2V
FIGURE 13A.
FIGURE 13B.
FIGURE 13C.
V
V
-0.62V
WAVEFORM AT POINT A
EE
EE
-0.31V
1V
AT 1MHz
-1V
P-P
WAVEFORM AT POINT B
FIGURE 13. MULTIPLYING BANDWIDTH
10-1206
HI20201
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10-1207
相关型号：
HI20206JCP
TRIPLE, PARALLEL, 8 BITS INPUT LOADING, 0.016 us SETTLING TIME, 8-BIT DAC, PDIP42
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