HI5810JIJ [INTERSIL]
CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold; CMOS 10微秒， 12位，采样A / D转换器，内置跟踪保持
| 型号： | HI5810JIJ |
| 厂家： | 
Intersil |
| 描述： | CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 文件： | 总12页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5810
CMOS 10 Microsecond, 12-Bit, Sampling
A/D Converter with Internal Track and Hold
August 1997
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs The HI5810 is a fast, low power, 12-bit, successive-
approximation, analog-to-digital converter. It can operate from
a single 3V to 6V supply and typically draws just 1.9mA when
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .100 KSPS
operating at 5V. The HI5810 features a built-in track and hold.
The conversion time is as low as 10µs with a 5V supply.
• Built-In Track and Hold
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V
The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through a
full conversion cycle. The output is user selectable: [i.e.,
• Maximum Power Consumption. . . . . . . . . . . . . . .40mW
12-bit, 8-bit (MSBs), and/or 4-bit (LSBs)]. A data ready flag,
and conversion-start input complete the digital interface.
• Internal or External Clock
• 1MHz Input Bandwidth . . . . . . . . . . . . . . . . . . . . . -3dB
An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.
Applications
Ordering Information
• Remote Low Power Data Acquisition Systems
INL (LSB)
(MAX OVER
TEMP.)
TEMP.
PART
NUMBER
RANGE
PKG.
NO.
• Digital Audio
o
( C)
PACKAGE
• DSP Modems
HI5810JIP
HI5810KIP
HI5810JIB
HI5810KIB
HI5810JIJ
HI5810KIJ
±2.5
±2.0
±2.5
±2.0
±2.5
±2.0
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld SOIC
-40 to 85 24 Ld SOIC
E24.3
E24.3
M24.3
M24.3
• General Purpose DSP Front End
• µP Controlled Measurement Systems
• Process Controls
-40 to 85 24 Ld CERDIP F24.3
-40 to 85 24 Ld CERDIP F24.3
• Industrial Controls
Pinout
HI5810
(PDIP, CERDIP, SOIC)
TOP VIEW
DRDY
(LSB) D0
D1
1
2
3
4
5
6
7
8
9
24
V
DD
23 OEL
22 CLK
21 STRT
D2
D3
20 V
19 V
-
REF
REF
D4
+
D5
18
V
IN
D6
17 V
+
AA
D7
16
V
-
AA
D8 10
D9 11
15 OEM
14 D11 (MSB)
13 D10
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number 3633.1
6-1777
HI5810
Functional Block Diagram
STRT
V
DD
TO INTERNAL LOGIC
V
SS
V
IN
CLK
CLOCK
CONTROL
AND
TIMING
DRDY
32C
OEM
V
+
REF
16C
8C
D11 (MSB)
50Ω
SUBSTRATE
D10
D9
D8
D7
D6
4C
2C
V
+
AA
C
V
-
32C
AA
64C
63
16C
12-BIT
12-BIT EDGE
SUCCESSIVE
APPROXIMATION
REGISTER
TRIGGERED
“D” LATCHED
8C
4C
2C
D5
D4
D3
C
C
P1
D2
D1
V
-
REF
D0 (LSB)
OEL
6-1778
HI5810
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
( C/W)
θ
( C/W)
JA
JC
V
to V
. . . . . . . . . . . . . . . . . . . .(V -0.5V) < V < +6.5V
SS DD
60
80
75
12
N/A
N/A
DD
SS
V
+ to V -. . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V +6.5V)
AA AA SS SS
V
+ to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
DD
AA
Analog and Reference Inputs
+ V -. . . . . . . . . (V -0.3V) < V
o
V
V
< (V
+0.3V)
+0.3V)
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
IN, REF , REF SS INA
DD
DD
o
Digital I/O Pins . . . . . . . . . . . . . . (V -0.3V) < VI/O < (V
SS
o
o
o
Operating Conditions
(SOIC - Lead Tips Only)
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
SS AA
- = GND, CLK = External 1.5MHz,
REF
DD
REF
Unless Otherwise Specified
o
o
o
25 C
-40 C TO 85 C
PARAMETER
MIN
TYP
MAX
MIN
MAX
TEST CONDITIONS
UNITS
ACCURACY
Resolution
12
-
-
-
-
-
-
-
-
-
-
-
12
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Linearity Error, INL
(End Point)
J
±2.5
±2.0
±2.0
±2.0
±3.5
±2.5
±2.5
±1.5
±2.5
±2.0
±2.0
±2.0
±3.5
±2.5
±2.5
±1.5
K
J
-
-
Differential Linearity Error, DNL
-
-
K
J
-
-
Gain Error, FSE
(Adjustable to Zero)
-
-
K
J
-
-
Offset Error, V
OS
(Adjustable to Zero)
-
-
K
-
-
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
J
f
f
= Internal Clock, f = 1kHz
IN
-
-
-
-
-
-
-
-
68.8
62.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
S
S
= 1.5MHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.0
63.6
dB
dB
RMS Noise + Distortion
S
S
= 1.5MHz, f = 1kHz
IN
Signal to Noise Ratio, SNR
RMS Signal
f
f
= Internal Clock, f = 1kHz
IN
70.5
63.2
dB
dB
S
S
= 1.5MHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.5
65.0
dB
dB
RMS Noise
S
S
= 1.5MHz, f = 1kHz
IN
Total Harmonic Distortion, THD
f
f
= Internal Clock, f = 1kHz
IN
-73.9
-68.4
dBc
dBc
S
S
= 1.5MHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
-80.3
69.7
dBc
dBc
S
S
= 1.5MHz, f = 1kHz
IN
Spurious Free Dynamic Range, SFDR
f
f
= Internal Clock, f = 1kHz
IN
75.4
69.2
dB
dB
S
S
= 1.5MHz, f = 1kHz
IN
K
f
f
= Internal Clock, f = 1kHz
IN
80.9
70.7
dB
dB
S
S
= 1.5MHz, f = 1kHz
IN
ANALOG INPUT
Input Current, Dynamic
At V = V
IN
+, 0V
-
±125
±150
-
±150
µA
REF
6-1779
HI5810
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
- = GND, CLK = External 1.5MHz,
REF
DD
REF
SS
AA
Unless Otherwise Specified (Continued)
o
o
o
25 C
-40 C TO 85 C
PARAMETER
MIN
TYP
MAX
MIN
MAX
TEST CONDITIONS
UNITS
Input Current, Static
Conversion Stopped
-
±0.6
±10
-
±10
µA
Input Bandwidth -3dB
-
-
-
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
µA
Ω
Reference Input Current
160
420
380
20
Input Series Resistance, R
In Series with Input C
During Sample State
During Hold State
S
SAMPLE
HOLD
SAMPLE
Input Capacitance, C
Input Capacitance, C
pF
pF
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
2.4
-
-
-
0.8
±10
-
2.4
-
V
V
IH
Low-Level Input Voltage, V
-
-
-
-
-
-
0.8
±10
-
IL
Input Leakage Current, I
IL
Except CLK, V = 0V, 5V
IN
-
µA
pF
Input Capacitance, C
10
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
I
I
= -400µA
4.6
-
-
-
0.4
±10
-
4.6
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
= 1.6mA
-
-
-
-
-
-
0.4
±10
-
OL
SINK
Three-State Leakage, I
Except DRDY, V
Except DRDY
= 0V, 5V
OUT
-
µA
pF
OZ
Output Capacitance, C
20
OUT
CLOCK
High-Level Output Voltage, V
I
I
= -100µA (Note 2)
4
-
-
-
-
-
4
-
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
Input Current
= 100µA (Note 2)
1
1
OL
SINK
CLK Only, V = 0V, 5V
IN
-
±5
-
±5
mA
TIMING
Conversion Time (t
+ t
)
10
-
-
10
-
µs
CONV
ACQ
(Includes Acquisition Time)
Clock Frequency
Internal Clock, (CLK = Open)
External CLK (Note 2)
External CLK (Note 2)
(Note 2)
200
300
-
400
2.0
-
150
500
-
kHz
MHz
ns
0.05
-
Clock Pulse Width, t
, t
LOW HIGH
100
-
100
-
Aperture Delay, t APR
-
-
35
105
100
30
60
4
50
150
160
-
-
70
180
195
-
ns
D
Clock to Data Ready Delay, t DRDY
D1
(Note 2)
-
ns
Clock to Data Ready Delay, t DRDY
D2
(Note 2)
-
-
75
100
15
-
ns
Start Removal Time, t STRT
(Note 2)
75
85
10
-
ns
R
Start Setup Time, t STRT
SU
(Note 2)
-
-
ns
Start Pulse Width, t STRT
(Note 2)
-
-
ns
W
Start to Data Ready Delay, t DRDY
D3
(Note 2)
65
60
20
80
105
-
120
-
ns
Clock Delay from Start, t STRT
(Note 2)
-
-
ns
D
Output Enable Delay, t
(Note 2)
-
30
95
-
50
120
ns
EN
Output Disabled Delay, t
(Note 2)
-
-
ns
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
NOTE:
+ I
AA
-
2.6
8
-
8.5
mA
DD
2. Parameter guaranteed by design or characterization, not production tested.
6-1780
HI5810
Timing Diagrams
5 - 14
4
15
1
3
1
2
2
3
CLK
(EXTERNAL
OR INTERNAL)
t
LOW
t
DRDY
D1
t
HIGH
STRT
DRDY
t
DRDY
D2
DATA N - 1
D0 - D11
DATA N
HOLD N
TRACK N
TRACK N + 1
V
IN
OEL = OEM = V
SS
FIGURE 1. CONTINUOUS CONVERSION MODE
2
2
3
15
2
4
1
5
CLK
(EXTERNAL)
t
STRT
t STRT
SU
R
t
STRT
W
STRT
t
DRDY
D3
DRDY
HOLD
HOLD
TRACK
V
IN
FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK
6-1781
HI5810
Timing Diagrams (Continued)
15
1
3
4
5
CLK
(INTERNAL)
2
t STRT
D
t STRT
R
t
STRT
W
STRT
DON’T CARE
t
DRDY
D3
DRDY
HOLD
HOLD
TRACK
V
IN
FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK
OEL OR OEM
t
DIS
t
EN
D0 - D3 OR
D4 - D11
90%
10%
50%
HIGH
TO
OUTPUT
PIN
IMPEDANCE
TO HIGH
HIGH
IMPEDANCE
TO LOW
50%
1.6mA
1.6mA
+2.1V
+2.1V
50pF
50pF
-400µA
-1.6mA
FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
FIGURE 5. TIMING LOAD CIRCUIT
Typical Performance Curves
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
2.0
V
= V + = 5V, V + = 4.608V, CLK = 1.5MHz
AA REF
V
= V + = 5V, V
AA REF
+ = 4.608V, CLK = 1.5MHz
DD
DD
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 6. NL vs TEMPERATUREI
FIGURE 7. OFFSET ERROR vs TEMPERATURE
6-1782
HI5810
Typical Performance Curves (Continued)
-1.0
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2.0
-2.1
-2.2
-2.3
-2.4
-2.5
1.75
1.70
V
= V + = 5V, V + = 4.608V, CLK = 1.5MHz
AA REF
V
= V + = 5V, V + = 4.608V, CLK = 1.5MHz
AA REF
DD
DD
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 8. DNL vs TEMPERATURE
FIGURE 9. FULL SCALE ERROR vs TEMPERATURE
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
INPUT FREQUENCY = 1kHz
SAMPLING RATE = 100kHz
SNR = 64.92dB
SINAD = 63.82dB
EFFECTIVE BITS = 10.30
THD = -69.44dBc
PEAK NOISE = -70.1dB
SFDR = 70.1dB
FREQUENCY
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
TEMPERATURE ( C)
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. FFT SPECTRUM
500
V
= V + = 5V, V + = 4.608V
AA REF
DD
450
400
350
300
250
200
150
-60
-20
0
20
40
60
80 100 120 140
-40
o
TEMPERATURE ( C)
FIGURE 12. INTERNAL CLOCK FREQUENCY vs TEMPERATURE
6-1783
HI5810
During the first three clock periods of a conversion cycle, the
TABLE 1. PIN DESCRIPTIONS
switchable end of every capacitor is connected to the input
and the comparator is being auto balanced at the capacitor
common node.
PIN NO. NAME
DESCRIPTION
1
DRDY Output flag signifying new data is available.
Goes high at end of clock period 15. Goes low
when new conversion is started.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V
+ terminal; and the remaining
REF
-. The capacitor common node, after the
2
3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Bit-0 (Least Significant Bit, LSB).
capacitors to V
REF
charges balance out, will indicate whether the input was
Bit 1.
1
above
period, the comparator output is stored and the MSB
capacitor is either left connected to V + (if the comparator
/
of (V
+ - V
-). At the end of the fourth
2
REF
REF
4
Bit 2.
5
Bit 3.
REF
-. This allows the next
was high) or returned to V
comparison to be at either / or / of (V
REF
6
Bit 4.
3
1
+ - V
-).
4
4
REF
REF
7
Bit 5.
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V
8
Bit 6.
+ or at V
-.
REF
REF
9
Bit 7.
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data ready output goes active. The conversion cycle is
now complete.
10
11
12
13
14
15
Bit 8.
Bit 9.
V
Digital Ground, (0V).
SS
D10 Bit 10.
Analog Input
D11 Bit 11 (Most Significant Bit, MSB)
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.
OEM Three-State Enable for D4-D11. Active low
input.
16
17
18
19
V
-
Analog Ground, (0V).
AA
V
+
Analog Positive Supply. (+5V) (See text.)
Analog Input.
AA
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have low
enough impedance to dissipate the current spike by the end of
the tracking period as shown in Figure 13. The amount of
charge is dependent on supply and input voltages. The
average current is also proportional to clock frequency.
V
IN
V
+
Reference Voltage Positive Input, sets 4095
code end of input range.
REF
20
21
22
V
-
Reference Voltage Negative Input, sets 0
code end of input range.
REF
STRT Start Conversion Input active low, recognized
after end of clock period 15.
20mA
CLK CLK Input or Output. Conversion functions are
synchronized to positive going edge (see text).
I
IN
10mA
0mA
23
24
OEL Three-State Enable for D0 D3. Active low input.
V
Digital Positive Supply (+5V).
DD
5V
CLK
Theory of Operation
0V
5V
The HI5810 is a CMOS 12-bit, Analog-to-Digital Converter
that uses capacitor charge balancing to successively
approximate the analog input. A binarily weighted capacitor
network forms the A/D heart of the device. See the block
diagram for the HI5810.
DRDY
0V
200ns/DIV.
CONDITIONS: V
V
= V + = 5.0V, V
= 4.608V, CLK = 750kHz, T = 25 C
+ = 4.608V,
REF
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
DD
AA
o
IN
A
capacitor is individually switchable to the input, V
+ or
REF
FIGURE 13. TYPICAL ANALOG INPUT CURRENT
V
-.
REF
6-1784
HI5810
As long as these current spikes settle completely by end of The HI5810 is specified with a 4.608V reference, however, it
the signal acquisition period, converter accuracy will be will operate with a reference down to 3V having a slight
preserved. The analog input is tracked for 3 clock cycles. degradation in performance.
With an external clock of 1.5MHz the track period is 2µs.
Full Scale and Offset Adjustment
A simplified analog input model is presented in Figure 14.
During tracking, the A/D input (V ) typically appears as a
IN
380pF capacitor being charged through a 420Ω internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external “zero Ω” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time
constants or 1.4µs. The maximum source impedance
In many applications the accuracy of the HI5810 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
The V
+ and V - pins reference the two ends of the
REF
REF
analog input range and may be used for offset and full scale
(R
Max) for a 2µs acquisition time settling to within
adjustments. In a typical system the V - might be returned
SOURCE
REF
to a clean ground, and the offset adjustment done on an input
amplifier. V + would then be adjusted to null out the full
0.5 LSB is 164Ω.
REF
scale error. When this is not possible, the V
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
- input can be
REF
- must be well
adjusted to null the offset error, however, V
decoupled.
REF
V
IN
R
SW ≈ 420Ω
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V ).
IN
CSAMPLE ≈ 380pF
R
SOURCE
Control Signal
-t
ACQ
ln [2
- R
R
=
The HI5810 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.
SW
SOURCE (MAX)
-(N + 1)
C
]
SAMPLE
FIGURE 14. ANALOG INPUT MODEL IN TRACK MODE
Reference Input
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
The reference input V
REF
+ should be driven from a low
impedance source and be well decoupled.
place. After the start of the next period 1 (specified by t
data), the output is updated.
D
As shown in Figure 15, current spikes are generated on the
reference pin during each bit test of the successive approxi-
mation part of the conversion cycle as the charge balancing
The DRDY (Data Ready) status output goes high (specified
by t DRDY) after the start of clock period 1, and returns
D1
capacitors are switched between V
- and V
+ (clock
low (specified by t DRDY) after the start of clock period 2.
D2
REF
REF
periods 5 - 14). These current spikes must settle completely
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
during each bit test of the conversion to not degrade the
accuracy of the converter. Therefore V
REF
+ and V
-
REF
- is normally
- is
should be well bypassed. Reference input V
REF
enables the four least significant bits (D0 - D3). t
specify the output enable and disable times.
and t
connected directly to the analog ground plane. If V
REF
EN
DIS
biased for nulling the converters offset it must be stable
during the conversion cycle.
If the output data is to be latched externally, either the trailing
edge of data ready or the next falling edge of the clock after
data ready goes high can be used.
20mA
When STRT input is used to initiate conversions, operation is
slightly different depending on whether an internal or
external clock is used.
I
+
10mA
0mA
REF
Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least t STRT) before clock
R
5V
0V
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.
CLK
5V
0V
DRDY
A low signal applied to STRT (at least t STRT wide) can
W
now initiate a new conversion. The STRT signal (after a
2µs/DIV.
delay of (t STRT)) causes the clock to restart.
D
CONDITIONS: V
= V + = 5.0V, V
AA REF
= 2.3V, CLK = 750kHz, T = 25 C
A
+ = 4.608V,
o
DD
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
V
IN
FIGURE 15. TYPICAL REFERENCE INPUT CURRENT
6-1785
HI5810
The input will continue to track until the end of period 3, the Except for V +, which is a substrate connection to V , all
AA
DD
and V
same as when free running.
pins have protection diodes connected to V
.
DD
SS
Input transients above V
the digital supplies.
or below V will get steered to
DD
SS
Figure 2 illustrates the same operation as above but with an
external clock. If STRT is removed (at least t STRT) before
R
clock period 2, a low signal applied to STRT will drop the The V + and V - terminals supply the charge balancing
AA AA
DRDY flag as before, and with the first positive going clock comparator only. Because the comparator is autobalanced
edge that meets the (t STRT) setup time, the converter will between conversions, it has good low frequency supply
SU
continue with clock period 3.
rejection. It does not reject well at high frequencies however;
V
- should be returned to a clean analog ground and V
+
AA AA
Clock
should be RC decoupled from the digital supply as shown in
Figure 17.
The HI5810 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are synchro-
nized with the rising edge of the clock signal.
There is approximately 50Ω of substrate impedance
between V
part of a low pass RC filter to attenuate switching supply
and V +. This can be used, for example, as
DD
AA
noise. A 10µF capacitor from V + to ground would
attenuate 30kHz noise by approximately 40dB. Note that
Figure 16 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.
AA
back-to-back diodes should be placed from V
to V + to
DD
AA
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.
Fast Fourier Transform (FFT) techniques are used to evalu-
ate the dynamic performance of the A/D. A low distortion
sine wave is applied to the input of the A/D converter. The
input is sampled by the A/D and its output stored in RAM.
The data is than transformed into the frequency domain with
a 4096 point FFT and analyzed to evaluate the converters
dynamic performance such as SNR and THD. See Typical
Performance Characteristics.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minium frequency shown in the specifications.
Signal-To-Noise Ratio
In the above two cases, a further restriction applies in that The signal to noise ratio (SNR) is the measured RMS signal to
the clock should not be shut off during the third sample RMS sum of noise at a specified input and sampling frequency.
period for more than 1ms. This might cause an internal The noise is the RMS sum of all except the fundamental and
charge pump voltage to decay.
the first five harmonic signals. The SNR is dependent on the
number of quantization levels used in the converter. The theo-
retical SNR for an N-bit converter with no differential or integral
linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 12-bit
converter the SNR is 74dB. Differential and integral linearity
errors will degrade SNR.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum t
and
times shown in the specifications. A violation may
LOW
t
HIGH
cause an internal miscount and invalidate the results.
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
Signal-To-Noise + Distortion Ratio
INTERNAL
ENABLE
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following.
CLOCK
CLK
OPTIONAL
EXTERNAL
CLOCK
Sinewave Signal Power
SINAD = 10 Log
100kΩ
18pF
Noise + Harmonic Power (2nd - 6th)
Effective Number of Bits
FIGURE 16. INTERNAL CLOCK CIRCUITRY
The effective number of bits (ENOB) is derived from the
SINAD data;
Power Supplies and Grounding
and V are the digital supply pins: they power all
V
DD
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V and V
SS
SINAD - 1.76
ENOB =
6.02
DD
SS
lines, V
should have a low impedance path to digital
SS
ground and V
should be well bypassed.
DD
6-1786
HI5810
Total Harmonic Distortion
Spurious-Free Dynamic Range
The total harmonic distortion (THD) is the ratio of the RMS The spurious-free dynamic range (SFDR) is the ratio of the
sum of the second through sixth harmonic components to fundamental RMS amplitude to the RMS amplitude of the
the fundamental RMS signal for a specified input and next largest spur or spectral component. If the harmonics
sampling frequency.
are buried in the noise floor it is the largest peak.
Total Harmonic Power (2nd - 6th Harmonic)
Sinewave Signal Power
SFDR = 10Log
THD = 10Log
Sinewave Signal Power
Highest Spurious Signal Power
TABLE 2. CODE TABLE
INPUT
BINARY OUTPUT CODE
VOLTAGE†
REF
V
+ = 4.608V
MSB
LSB
CODE
DESCRIPTION
V
- = 0V
DECIMAL
COUNT
REF
(V)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Full Scale (FS)
4.6069
4.6058
3.4560
2.3040
1.1520
4095
4094
3072
2048
1024
1
1
1
1
1
0
0
0
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
FS - 1 LSB
3
/
/
/
FS
FS
FS
4
2
4
1
1
1 LSB
Zero
0.001125
0
0
†The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
+5V
0.1µF
4.7µF
10µF
0.1µF
0.1µF
0.01µF
V
+
V
DD
AA
D11
.
.
.
OUTPUT
DATA
D0
V
REF
V
+
REF
4.7µF
0.001µF
DRDY
OEM
OEL
ANALOG
INPUT
V
V
IN
STRT
CLK
1.5MHz CLOCK
-
V
-
V
SS
REF
AA
FIGURE 17. GROUND AND SUPPLY DECOUPLING
6-1787
HI5810
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3200µm x 3940µm
Type: PSG
Thickness: 13kÅ ±2.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: AlSi
Thickness: 11kÅ ±1kÅ
5
2
1.84 x 10 A/cm
Metallization Mask Layout
HI5810
DRDY
D0
(LSB)
D1
V
OEL
DD
CLK
D2
D3
STRT
V
-
REF
D4
D5
D6
V
V
+
REF
D7
D8
IN
V
+
-
AA
V
AA
D9
V
D10
D11
(MSB)
OEM
SS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6-1788
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