HIP5020DB [INTERSIL]
Integrated-Power Buck Converter Controller with Synchronous Rectification; 集成的功率降压转换器与控制器同步整流
| 型号： | HIP5020DB |
| 厂家： | 
Intersil |
| 描述： | Integrated-Power Buck Converter Controller with Synchronous Rectification |
| 文件： | 总15页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP5020
Data Sheet
January 1997
File Number 4243
Integrated-Power Buck Converter
Features
Controller with Synchronous Rectification
• High Efficiency - Above 95%
The HIP5020 is a high-efficiency, buck converter controller
with synchronous rectification and integral power MOSFETs.
Integrated current sensing eliminates the external resistor
and saves power. The controller combines two methods of
regulation: Current mode control for outstanding regulation
response to large signal load transients, and Hysteretic
mode control for high efficiency at low output currents.
• Integrated N-Channel Synchronous Rectifier
and Upper MOSFETs - 75mΩ Each
• Wide Input Voltage and Load Range
- 4.5VDC to 18VDC (5 to 12 NiCd Battery Cells)
- Up to 3.5ADC
• Automatically Switches Regulation Mode
- Current Mode Control for Excellent Performance at
High Load Currents
The HIP5020 controller offers a high degree of flexibility.
Small components set the switching frequency, the soft-start
interval and the load current boundary between Run and
Hysteretic modes. These adjustments enable the designer
to best optimize the trade-offs of cost, efficiency and size.
The example application guide section illustrates these
trade-offs with component and vendor suggestions for three
circuit designs. These designs are suitable for use without
modification. However, the block diagram, detailed
- Hysteretic Control for High Efficiency at Light Load
Currents
• Flexible and Easy to Use
- Ready-to-Use Example Applications
- Custom Optimization with Small Components
- Design and Simulation Software Available
• Integrated, Low-Loss Current Sensing
• Over-Current Protection
description and HIP5020 component specifications enable
further optimization to meet specific requirements.
• Adaptive Dead-Time - Eliminates Shoot-Through
• 100kHz to 1MHz PWM Switching Frequency
• Thermally Enhanced SOIC Package
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER
RANGE ( C)
PACKAGE
HIP5020DB
0 to 70
28 Ld SOIC
M28.3
Applications
• Notebook Computers
• Portable Telecommunications
• Portable Instruments
Pinout
Typical Application
HIP5020 (SOIC)
TOP VIEW
100
95
90
85
80
HIP5020
V
V
= 6V
= 5V
IN
O
MODE
CONTROL AND
PROTECTION
VIN
VIN
1
2
3
4
5
6
7
8
9
28 PHASE
27 PHASE
V
IN
V
V
= 5V
= 3.3V
IN
O
26
VIN
SD
INTERNAL
SUPPLY
25 SOFT
PHASE
PHASE
OVLD
24
23
22
21
20
0.001 0.01
0.1
1
10
L1
LOAD CURRENT (A)
PGND
(WEB)
PGND
(WEB)
14µH
440µF
V
OUT
C1
GND 10
FB 11
19 CP-
18 CP+
17 VCC
16 BOOT
15 CT
REGULATION
AND CONTROL
VINF 12
HMI 13
SLOPE 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-13
HIP5020
Functional Block Diagram
VCC
VIN
CP+
CHARGE PUMP
BOOT
REGULATOR
CP-
PWM
S
PWM
LATCH
UPPER GATE
DRIVE
CT
OSCILLATOR
R
SLOPE
GENERATOR
SLOPE
SD
PWM
CURRENT
SENSOR
+
-
PHASE
MODE
CONTROL
LOGIC
∑
-
RUN
PHASE
+
+
-
OVER-CURRENT
PROTECTION
SOFT-
START
SOFT
VINF
LOWER GATE
DRIVE AND
LOGIC
ERROR
AMP
REFERENCE
+∆ 1.26V -∆
+
PGND
GND
+
-
V
+
CC
20µA
HYSTERETIC
-
12pF
OVLD
FB
HMI
Pin Description
PIN NO
DESIGNATOR
FUNCTION
Input Voltage
Switch Node
DESCRIPTION
1, 2, 3
VIN
Connection to the power source (Battery). Operates from 4.5VDC to 18VDC.
Connect to output Inductor.
4, 5, 27, 28
PHASE
PGND
6, 7, 8, 9, 20,
21, 22, 23
Power Ground
Power Return and thermal interface. Solder these pins to a large copper ground plane.
10
11
12
13
14
15
16
17
18
19
24
25
26
GND
FB
Signal Ground
Voltage Sense
Filtered Input
Hysteretic Current
Ramp Set
Connect to the output load return.
A divider network scales the output voltage to 1.26VDC.
VINF
HMI
Connect a low-pass (R-C) filter from V .
IN
A resistor to the HMI pin sets the peak inductor current level during hysteretic mode.
A capacitor to ground sets the compensation ramp for current mode control.
A capacitor to ground sets the oscillator frequency.
SLOPE
CT
Frequency Set
Bootstrap Bias
Bias Voltage
BOOT
VCC
CP+
A capacitor to Phase pin stores energy for the upper MOSFET drive.
Output of charge pump regulator. Use bypass capacitor to ground.
Charge Pump
Capacitor
Connect a capacitor between these pins for the charge pump to generate bias power. The
internal charge pump inverter is synchronized to the oscillator.
CP-
OVLD
SOFT
SD
Over-Load
Soft Start
Shutdown
A high level on this pin signals activation of the current limit protection.
A capacitor to ground sets the soft start interval.
A low level suspends operation for a low-dissipation shutdown mode.
2-14
HIP5020
Absolute Maximum Ratings
Thermal Information
o
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20.0V
IN
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
Supply Voltage, V
Shutdown Voltage . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V +0.3V
Voltage on PGND. . . . . . . . . . . . . . . . . . . . . . -2V to +2V (Transient)
All voltages are relative to GND, unless otherwise specified.
. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20.0V
CC
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . .
51
42
39
2
CC
Plastic SOIC Package (with 1in copper). . . . . . . . .
2
Plastic SOIC Package (with 3in copper). . . . . . . . .
o
Maximum Junction Temperature (Plastic Package) . . . . . . . .125 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
(SOIC - Lead Tips Only)
o
o
o
Operating Conditions
Voltage Range, V . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to +18.0V
IN
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
o
Oscillator Frequency Range. . . . . . . . . . . . . . . . . . 100kHz to 1MHz
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
V
= 6.3VDC, Components referenced from Figure 1. TYP values at T = 25 C and MIN, MAX limits are for T
J J
IN
from 0 C to 125 C; Unless Otherwise Specified
o
o
T
25 C
=
J
o
o
o
0 C < T < 125 C
J
PARAMETER
REFERENCE
SYMBOL
TEST CONDITIONS
TYP
MIN
MAX
UNITS
Reference Voltage
V
Total Variation, I > I
HMI
1.26
-
1.235
1.285
0.2
V
FB
O
Temperature Stability
-
mV
mV
Hysteresis Width
2∆
Hysteresis Mode; I < I
HMI
20
10
30
O
MODE CONTROL LOGIC
Under-Voltage Lockout Threshold
Under-Voltage Lockout Hysteresis
Shutdown Threshold
VCC
7.6
0.3
1.2
20
7.2
-
7.9
-
V
V
UV
∆VCC
UV
V
0.9
16
1.5
29
V
SD
HMI Current Source
I
µA
HMI
POWER MOSFETs
Drain Leakage Current
On State Resistance
I
V
V
= 20V, V
= 0
= 12.6V; I
0.35
75
-
60
-
10
125
-
µA
mΩ
ns
DSS
DSS
PHASE
r
- V
= 2A
PHASE
DS(ON)
BOOT
PHASE
Phase Rise and Fall Time
CHARGE PUMP REGULATOR
t , t
I = 2ADC
O
10
r
f
V
Regulation
V
V
= 8.65V; F = 100kHz;
14.8
14.0
16.0
V
CC
CC
IN
S
C4 = C5 = 1.0µF
Charge Pump Disable
V
9.8
4
-
-
-
-
-
-
V
INCPN
VCC Current - Run Mode
VINF Current - Hysteretic Mode
VCC Current - Shutdown
I
F
= 100kHz
S
mA
µA
µA
CC
I
- Idle
V
= 5V, V = 0
CT
78
2
110
17
CC
I
FB
SD
V
= GND, V = 12V
IN
CC
2-15
HIP5020
o
Electrical Specifications
V
= 6.3VDC, Components referenced from Figure 1. TYP values at T = 25 C and MIN, MAX limits are for T
J J
IN
from 0 C to 125 C; Unless Otherwise Specified (Continued)
o
o
T
25 C
=
J
o
o
o
0 C < T < 125 C
J
PARAMETER
ERROR AMPLIFIER
Internal Integration Capacitor
Open-Loop Voltage Gain
Gain-Bandwidth Product
Input Bias Current
SYMBOL
TEST CONDITIONS
TYP
MIN
MAX
UNITS
12
89
7.2
3
-
-
-
-
pF
dB
AV
GBW
-
-
MHz
nA
I
V
FB
= 1.26VDC
-70
70
FB
SOFT START
Current Source
I
10
6
14
µA
SOFT
OSCILLATOR
CT Charging Current
Initial Frequency Accuracy
Total Frequency Variation
PROTECTIVE FUNCTION
Current Limit Threshold
PWM MODULATOR
Modulator Gain
126
±3
110
140
-
µA
%
-
-
V
IN
= 4.5 to 18V
±7
±10
%
I
4.5
4
-
A
O PK
1.7
100
115
-
-
-
-
-
-
A/V
ns
Minimum On Time
Minimum Off Time
ns
HYSTERETIC COMPARATOR
Propagation Delay
Step V
FB
3
-
-
-
-
µs
SLOPE GENERATOR
Slope Capacitor Charge Current
I
80
µA
SLOPE
Example Application Guide
The HIP5020 provides the flexibility to meet differing needs.
This section illustrates the trade-off of component selection
for three DC-DC converter circuit designs. Each circuit is
optimized for a specific goal: Circuit 1 is optimized for high
efficiency, Circuit 2 is optimized for small size, and Circuit 3
is optimized for low cost. Figure 1 shows the schematic
common to all three converter designs. Table 1 shows the
expected performance parameters for each circuit. Table 2
gives the value of each component referenced in Figure 1.
Table 3 provides a listing of suggested vendors for the major
(or critical) components. Figures 2, 3 and 4 show the
efficiency and transient performance of each circuit.
2-16
HIP5020
VIN
VCC
D1
C4
BOOT
+
-
CP+
R5
C2
C12
C5
V
IN
HIP5020
C3
L1
V
PHASE
O
CP-
R6
D2
C1
VINF
PGND
FB
R1
R2
C9
C10
ON/OFF
SD
CT
OVLD
HMI
SLOPE
SOFT
C6
GND
C7
C8
R4
FIGURE 1. EXAMPLE APPLICATION CIRCUIT
TABLE 1. EXAMPLE APPLICATION PERFORMANCE PARAMETERS
These characteristics are for the circuit shown in Figure 1 with the components given in Tables 2 and 3.
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
PARAMETER
Input Voltage
- Typical
- Range
CONDITIONS
HIGH EFFICIENCY
SMALL SIZE
LOW COST
UNITS
VDC
kHz
3 Li-Ion Cells:
11.1
8.1 to 16
2 Li-Ion Cells:
7.4
5.4 to 12
9 Nicd Cells:
10.8
8.1 to 16
Switching Frequency
200 ±15%
625 ±15%
120 ±20%
Output Voltage Variation
Line Regulation
Load Regulation
Initial Setting
Input Voltage Range; I = 1ADC
3.3 ±3.5%
±0.1
3.3 ±2.2%
±0.1
3.3 ±3.5%
±0.1
V
%
%
O
I
= 0.1 to 3ADC, V = Typical
±0.3
±0.3
±0.4
O
IN
Output Voltage Ripple
- Full Load
- Light Load
Bandwidth < 20MHz
I
I
= 3ADC, V = Typical
= 50mADC, V = Typical
IN
18
50
30
80
20
70
mV
O
O
IN
Efficiency
- Full load
- Peak
I
= 3ADC, V = Typical
IN
86
92
88
86
89
84
86
90
72
%
%
%
O
0.5 < I < 2ADC, V = Typical
O
IN
- Light Load
I
= 50mADC, V = Typical
O
IN
2
Estimated Circuit Area
Tallest Component
3.5
0.45
2.1
0.24
3.6
0.68
in
in
Normalized Circuit Cost
Ratio of total circuit cost to Circuit 2
1.1
1
0.75
TABLE 2. COMPONENT SUGGESTIONS FOR EXAMPLE APPLICATION CIRCUITS
COMPONENT
CIRCUIT 1
MBR0540
MBR0540
CIRCUIT 2
MBR0540
Not Used
CIRCUIT 3
1N4148
D1
D2
L1
Not Used
16µH, R
< 15mΩ
5µH, R
< 22mΩ
26µH, R < 25mΩ
DC
DC
DC
C1
2x - 220µF, 10V OS-CON
3x - 220µF, 10V Tantalum
ESR (100kHz) < 100mΩ
MAX
3x - 390µF, 25V, Aluminum
ESR (100kHz) < 65mΩ
ESR
(100kHz) < 35mΩ
MAX
100µF, 20V OS-CON
ESR (100kHz) < 30mΩ
MAX
2x - 390µF, 25V Aluminum
ESR (100kHz) < 65mΩ
C2
C3
2x - 100µF, 16V Tantalum
ESR (100kHz) < 100mΩ
MAX
MAX
0.1µF ±10% - Ceramic
MAX
0.1µF ±20% - Ceramic
0.1µF ±20% - Ceramic
2-17
HIP5020
TABLE 2. COMPONENT SUGGESTIONS FOR EXAMPLE APPLICATION CIRCUITS (Continued)
COMPONENT
CIRCUIT 1
1µF ±20% - Ceramic
1µF ±20% - Ceramic
470pF ±5% - Ceramic
680pF ±5% - Ceramic
0.1µF ±20% - Ceramic
220pF ±5% - Ceramic
0.1µF ±20% - Ceramic
0.1µF ±20% - Ceramic
562K ±1%
CIRCUIT 2
0.22µF ±10% - Ceramic
0.22µF ±10% - Ceramic
150pF ±5% - Ceramic
390pF ±5% - Ceramic
0.033µF ±10% - Ceramic
Not Used
CIRCUIT 3
1µF ±20% - Ceramic
1µF ±20% - Ceramic
820pF ±10% - Ceramic
1200pF ±5% - Ceramic
0.01µF ±10% - Ceramic
Not Used
C4
C5
C6
C7
C8
C9
C10
C12
R1
R2
R4
R5
R6
0.1µF ±20% - Ceramic
0.1µF ±20% - Ceramic
20K (Note)
0.1µF ±20% - Ceramic
0.1µF ±20% - Ceramic
100K ±1%
348K ±1%
12.4K (Note)
61.9K ±1%
33.2K
37.4K
49.9K
200K
2K
2K
49.9K
Not Used
Not Used
NOTE: Both resistors available in one SOT-23 from California Micro Devices part # PAC27A01
TABLE 3. SUGGESTED SUPPLIERS
PHONE
PHONE
COMPONENT
Capacitors -
SUPPLIER
NUMBER
COMPONENT
SUPPLIER
NUMBER
Sanyo
501-633-5030
Inductors -
Coiltronics
407-241-7876
Aluminum and Os Con
OCTA-PAC
Inductors -
Capacitors -
Aluminum and Ceramic
Panasonic
Sprague
AVX
0774-32-1111
207-324-4140
207-282-5111
708-696-2000
Pulse
Engineering
619-674-8100
607-785-1109
714-630-7420
412-282-8282
201-581-7653
Capacitors -
Tantalum and Os Con
Inductors -
GB
International
Capacitors -
Ceramic and Tantalum
Magnetic Cores -
Powdered Iron
Micrometals
Capacitors -
Aluminum
United
Chemi-Con
Magnetic Cores -
Kool Mu
Magnetics
Magnetic Cores -
Microlite
AlliedSignal Inc.
2-18
HIP5020
Typical Performance Curves
100
V
= 3.3VDC
O
3.46
3.34
3.32
3.30
3.28
1.5
95
90
85
80
75
70
V
= 8.1V
IN
V
= 12.6V
IN
1.0
0.5
0
0.001
0.01
0.1
1
10
0
40
80
120
160
200
0.200
0.5
LOAD CURRENT (A)
TIME (ms)
FIGURE 2A.
FIGURE 2B.
FIGURE 2. HIGH-EFFICIENCY CIRCUIT 1 MEASURED PERFORMANCE EFFICIENCY vs LOAD CURRENT AND HYSTERETIC MODE
OPERATION (V = 11.1VDC, LO = 0.1ADC
IN
100
95
3.32
3.31
3.30
3.29
3.28
3.27
4
V
= 3.3VDC
O
V
= 5.4V
IN
90
85
80
V
= 12V
IN
3
2
75
70
1
0
0.001
0.01
0.1
1
10
0.000
0.040
0.080
0.120
0.160
LOAD CURRENT (A)
TIME (ms)
FIGURE 3A.
FIGURE 3B.
FIGURE 3. SMALL-SIZE CIRCUIT 2 MEASURED PERFORMANCE EFFICIENCY vs LOAD CURRENT AND 50% TO FULL LOAD
TRANSIENT (1A/µs)
3.34
100
3.32
95
3.30
90
85
80
75
70
3.28
3.26
3
V
= 8.1V
IN
V
= 14.4V
IN
2
1
0
0
0.1
0.2
0.3
TIME (ms)
0.4
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
FIGURE 4A.
FIGURE 4B.
FIGURE 4. LOW-COST CIRCUIT 3 PERFORMANCE PREDICTIONS EFFICIENCY vs LOAD CURRENT AND 50% TO FULL LOAD
TRANSIENT (100A/ms)
2-19
HIP5020
Design Information
The HIP5020 is optimized for battery power systems with a
lower gate drive to turn-off the lower MOSFET when the
inductor current reaches zero by monitoring the phase
4.5V to 18V input. The integrated MOSFETs along with an
LC output filter form a synchronous rectified, step-down
(buck) converter. The output is regulated at high output
current by peak-current-mode PWM control. At light loads,
the control automatically transitions to hysteretic mode to
regulate the output.
voltage (r
* I).
DS(ON)
The HIP5020 regulates the output voltage with peak-current
PWM control in Run mode. The peak-current-mode
feedback, the MOSFETs and output inductor, L1 are all parts
of the peak-current control loop. An outer voltage regulation
loop then programs the peak current to the level required.
Detailed Operating Description
When averaged over many switching cycles, the entire peak-
current control loop can be simplified and described as a
voltage controlled current source. Figure 5 shows a
The following description refers to symbols and components
in the Functional Block Diagram and Figure 1. Figure 1
shows the HIP5020 in a DC/DC converter.
simplified diagram of this operation. The current source
supplies the output capacitor and load. The outer voltage
regulation loop consists of an error amplifier and
compensation components. The error amplifier programs the
inductor current (as described above) to the value required
to regulate the output voltage. Both the error amplifier and
hysteretic comparator monitor the feedback (FB) pin. During
Operating Modes
The HIP5020 has 4 modes of operation; Shutdown, Start-up,
Run and Hysteretic modes. The controller draws only 2µA
from the input supply in the Shutdown mode. This mode is
activated when the SD pin is high. The controller enters the
Start-up mode by releasing the SD pin, and the charge pump
turns-on to increase V
above the under-voltage lockout
the Run mode, the feedback node voltage (V ) is held to
CC
FB
threshold. In the Start-up mode, the voltage on the SOFT pin
increases at a rate set by the capacitor on the SOFT pin. The
SOFT voltage limits the rate-of-rise of output voltage. The
output voltage is regulated with peak current control in the
Run mode at high output current. For low output currents, the
controller automatically transitions to Hysteretic mode for
output regulation. In this mode, the hysteretic comparator
cycles the control on (RUN = High) and off (RUN = Low) as a
function of the output voltage level. When off (RUN = Low),
bias power is removed from most of the control’s functions
(only the reference and hysteretic comparator operate with
RUN = Low). The converter replenishes the output capacitor
charge with short duration power cycles (RUN = High) and the
converter dissipates very little average power. A resistor (R4)
programs the load current boundary (HMI) between the Run
and Hysteretic modes.
the reference voltage (REF) by the voltage feedback loop.
V
is related to V , R1 and R2.
o
FB
CURRENT
LIMIT
PEAK-CURRENT
CONTROL LOOP
V
O
ERROR
AMP
REF+∆
HYSTERETIC
COMPARATOR
LOAD
REF
+
+
OUTPUT
CAPACITOR
RUN
-
-
REF-∆
LOWER
LIMIT
HMI
HIP5020
FB
R2
R1
Run Mode
FIGURE 5. SIMPLIFIED DIAGRAM OF OUTPUT VOLTAGE
REGULATION AND MODE SWITCHING
The HIP5020 operates in Run mode at high output currents.
Each clock cycle of the oscillator sets the PWM Latch and
turns-on the high side MOSFET (See the Functional Block
Diagram). The current sensor supplies a voltage
Limiting the error amplifier output voltage range provides
both current-limit protection and a mechanism for setting
the load current boundary between the Run and Hysteretic
modes. Figure 6 shows the modes of operation as a
function of the error amplifier output and load current. The
error amplifier output voltage tracks the inductor current.
The upper error amplifier clamp limits the peak inductor
current which reduces the pulse-width (or duty factor). This
reduces the output voltage with a constant current
characteristic. The lower error amplifier limit sets the
minimum inductor current. For load current demand below
the minimum inductor current, the excess current adds
charge to the output capacitor and the output voltage
increases. The voltage on the feedback (FB) pin also
proportional to the current in the high side MOSFET. The
PWM Comparator resets the PWM latch once the current
signal exceeds the summation of the error amplifier and
slope signals. The upper MOSFET turns off and the PWM
latch enables the lower gate drive and logic. The current in
the output inductor continues to flow, reducing the PHASE
voltage (by displacing charge on the capacitances of the
PHASE pin). The lower MOSFET turns-on after the voltage
on the PHASE pin falls to ground as monitored by the phase
comparator. The lower MOSFET remains ‘on’ for continuous
output inductor current until the next cycle. For discontinuous
inductor current operation, the phase comparator signals the
2-20
HIP5020
increases and the converter operates in Hysteretic mode.
The lower error amplifier limit is the voltage on the HMI
inductor current is regulated to a level proportional to V
.
HMI
With very light loads, the converter replenishes the output
(Hysteretic Mode Current) pin. The HMI level (V
the Run-to-Hysteretic mode load current boundary.
) sets
capacitor charge in a few switching cycles (RUN = High) and
the converter dissipates very little average power. Operation
automatically transitions to Run mode as the load increases
above the Run-to-Hysteretic mode load current boundary;
the RUN signal simply stays High.
HMI
The output voltage ripple during Hysteretic Mode is a
function of the HMI (Hysteretic Mode Current) setting, output
capacitor ESR, and the hysteretic voltage trip points. The
approximate ripple voltage is:
HYSTERETIC
RUN
MODE
CURRENT
LIMIT
MODE
V
HMI
V
• 1.7 • ESR + 2 • ∆ • (R ⁄ R + 1)
1 2
HMI
OUTPUT LOAD
FIGURE 6. OPERATING MODES WITH THE ERROR
AMPLIFIER CLAMPS
Where 2 ∆ is the hysteresis width (~20mV) and the 1.7 (A/V)
factor is the error amplifier output voltage to peak current
control gain (modulator gain).
Hysteretic Mode
Protective Modes
The HIP5020 operates in the hysteretic mode with low
output current. In this mode, the hysteretic comparator
cycles the control on (RUN = High) and off (RUN = Low) as a
function of the output voltage and the FB voltage level.
Figure 7 illustrates the averaged Hysteretic Mode operation
with reference to Figure 5. At light load, the error amplifier
The HIP5020 provides cycle-by-cycle current limiting and
protects against over-current. The cycle-by-cycle current
limit reduces the pulse width (duty factor) for peak inductor
current levels exceeding the current limit (4A minimum). This
results in a constant current output characteristic. The OVLD
pin toggles high to indicate an overload condition. Should
the current limit cause a small pulse width due to a
output voltage is held to the HMI voltage (V
commands an inductor current that exceeds the load
). This level
HMI
saturating output inductor, over-current protection activates a
soft-start cycle. The simultaneous occurrence of a minimum
pulse width and a current limit signals an over-current
condition. The converter enters the start-up mode by fully
discharging the soft-start capacitor and inhibiting PWM
operation. With a continuous overload, the over-current
protection triggers the soft-start function which inhibits PWM
operation until after the soft-start capacitor first fully charges
current. The excess current flows into the output capacitor
which increases the output voltage (V ). The voltage
O
feedback loop no longer holds V at the reference voltage.
FB
When V increases to the Upper Hysteretic Trip Level, the
FB
RUN signal transitions Low to power-down most of the
control’s functions, and the load is supplied by the output
capacitor. After V (and the equivalent output voltage)
FB
drops below the Lower Hysteretic Trip Level, RUN transitions
High, turning on the controller. The converter replenishes the
charge on the output capacitor (C1). This cycle repeats to
regulate the output voltage.
to V
and then fully discharges. This results in a very low
CC
average input current.
Soft-Start
The soft-start function is programmed by a capacitor on the
SOFT pin (C10). This capacitor is initially discharged.
V
O
Releasing the SD pin, or increasing V
above the under-
2∆
V
CC
O
REF
voltage lockout threshold initiates a soft-start interval. As the
internal 10µA source charges C10, the converter output
follows the capacitor voltage, V
. The control establishes
SOFT
closed loop regulation when the output voltage approaches
the level set by R1, R2 and the reference.
RUN
Initiating shutdown mode rapidly discharges capacitor C10.
Releasing the SD pin initiates another start-up mode which
TIME
FIGURE 7. TYPICAL HYSTERETIC MODE OPERATION
charges up the capacitor C10 to V
.
CC
The HIP5020 maintains peak-current control during
Should the V exceed the upper hysteretic trip level, the
FB
internal 10µA source stops charging C . The soft-start
Hysteretic mode. When the RUN signal transitions High, the
control functions reenergize and the oscillator sets the PWM
Latch which turns-on the high side MOSFET. The inductor
current increases and resets the PWM latch to turn off the
MOSFET. This cycle-by-cycle operation is identical to the
Run mode operation. However, in hysteretic mode, the
10
interval will resume when V drops below the lower
FB
hysteretic trip level.
2-21
HIP5020
Switching Frequency
Detailed Component Selection
The oscillator produces a sawtooth wave on the CT pin with
an amplitude of 1.26V. The switching frequency is set by C6.
Select the closest standard capacitance value according to
The application circuits shown in Figure 1 and described by
Tables 1 and 2 illustrate component trade-off to achieve size,
cost and efficiency goals. A design and simulation software
program is available that simplifies the small signal
component selection (http://www.semi.harris.com). This
section provides additional guidance for selecting alternate
components.
the following formula:
–4
–11
10
F
C6 = ------------ – 10
S
Higher switching frequency decreases the size of output
filter L1 and C1 and enables a higher bandwidth converter
for faster response to a load transient. However, higher
frequencies dissipate more power for a less efficient
converter.
Output Capacitor
The output capacitor, C1 smooths the output voltage ripple
of the DC-DC converter. The size and value depend upon
the output ripple requirement, the dielectric characteristics,
the value of output inductance and the switching frequency.
Choose a capacitor with a low impedance at the switching
frequency to meet the output voltage ripple requirement.
Use only specialized low-ESR capacitors intended for
switching-regulator applications.
Control Loop Design
The HIP5020 realizes excellent transient response with
proper control loop design. The device utilizes peak-current
control with the entire current loop integrated within the
HIP5020. Additionally, the HIP5020 includes a 12pF
integration capacitor across the error amplifier. (See the
Detailed Operating Description above.) Some applications
need only add the resister R1 and capacitor C7 for a
complete design.
Capacitor impedance above the switching frequency should
also be minimized. During Hysteretic mode operation, the
transition of RUN from low to high causes inductor current to
ramp from zero to the HMI set level in a very short time. This
rate of current change across the output capacitor’s the
equivalent series inductance (ESL) causes a voltage spike
that appears (attenuated) on the FB pin. The ESL or the rate
of current change must be limited to prevent the hysteretic
comparator from toggling RUN between high and low.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance at the switching frequency (and the first few
harmonics of the switching frequency) to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
The capacitor, C7 adds a compensation slope to the peak
current control loop (see Slope Compensation below). C7
shows up in the closed loop transfer function as peaking
around half of the switching frequency. For a stable design,
make sure the closed loop gain at half of the switching
frequency is below -10dB.
The error amplifier and compensation components regulate
the output voltage by controlling the current loop (as shown
in Figure 5). The compensation components shown in
Figure 8 realize a lead-lag circuit. The resistor R1 adjusts
the loop gain of the converter and resistor R6 and capacitor
C9 set the pole and zero. The resistor R2 does not appear in
the lead-lag transfer function. R2 sets the output voltage
level. First stabilize control loop by selecting R1 and then
determine R2 for the desired output voltage level.
Output Inductor
The output inductor, L1 sets the ripple current and influences
the converter efficiency. The ripple current, ∆I is related to
the inductance and switching frequency (F ), for continuous
S
inductor current. Increasing the inductance or the switching
frequency lowers the ripple current and the output ripple volt-
age. The inductance can be determined by:
V
O
REFERENCE
1.26V
ERROR
AMP
TO
PWM
R6
+
-
COMPARATOR
V
–V
V
O
V
IN
IN
O
--------------------- ---------
L1 =
•
∆I • F
S
C9
R1
R2
Inductance is a function of the core permeability, core size,
and the square of number of turns. The power dissipation of
the inductor is also dependent upon the number of turns and
the core. In general, most of the power dissipation is in the
inductor’s winding. Therefore, use high permeability core
material to minimize the number of turns. Be sure the flux at
full load current does not saturate the core. Recommended
core materials include: Microlite™ from Allied Signal, ferrite,
Kool-Mu™, molypermalloy (MMP), and powdered iron.
12pF
HIP5020
FB
FIGURE 8. LEAD-LAG COMPENSATION CIRCUIT
2-22
HIP5020
Using the built-in 12pF integration capacitor across the error
amplifier, the transfer function, G(s) for the lead-lag network is:
The output voltage regulation improves with the use of
integrated resistor network. By integrating the resistors, the
variations of R1 track the variations of R2. The ratio of R1 to
R2 remains constant and this minimizes the output voltage
variation to improve regulation. Integrated resistor networks
are available in small SOT-23 packages such as the one
used in Circuit 2.
1 + s ⁄ ω
K
s
z
--- -----------------------
G(s) =
•
1 + s ⁄ ω
p
1
where K = -----------------------------------------
–12
R1 • 12 • 10
1
ω
= ----------------------------------------
Slope Compensation
z
(R1 + R6) • C9
Slope compensation is necessary to avoid current loop
instability for duty ratios above 50%. Select C7 to set the
amount of slope compensation according to the following:
1
and ω = ---------------------
p
R6 • C9
–6
The HIP5020 design and simulation software (available at
the Harris WEB site) computes these values and greatly
simplifies the following compensation design process. To
design a DC-DC converter for stable operation:
L1 • 272 • 10
C7
= ----------------------------------------
MAX
V
O
This value of capacitance provides a compensation ramp that is
1/2 of the reflected output inductor decreasing current slope.
1. Determine the output capacitor’s ESR zero frequency,
f
which is given by: 1 ⁄ (2 • π • C1 • ESR)
Charge Pump and Bootstrap Design
ESR
2. Place the compensation pole (ω /2π) at the ESR zero fre-
p
The charge pump and bootstrap circuit supply the internal
bias power for the HIP5020. The majority of the bias power
goes to gate drives. The charge pump operates at the
switching frequency for input voltage below 9.8V. Select
quency, f
ESR
.
3. Determine the desired converter bandwidth (or the fre-
quency where the loop gain is unity). Bandwidth must be
below 1/2 the switching frequency. A reasonable band-
width is approximately 1/10 the switching frequency.
capacitors C and C according to the following:
4
5
–6
0.088
C4, C5
= -------------- + 0.12 • 10
4. Select the compensation zero (ω ) well below the desired
MIN
z
F
S
bandwidth frequency and adjust as necessary to achieve
o
the desired phase margin (40 Minimum).
The gate of the upper N-Channel MOSFET is driven above
the input voltage by the internal gate drive with power
supplied by the bootstrap circuit D1 and C3. A fast recovery,
low leakage diode is recommended for D1. C3 should be a
high quality ceramic capacitor.
5. Adjustthegain(viaR1)anditeratethecompensationzero
and gain as needed to achieve the desired bandwidth
and phase margin.
6. Measure the closed-loop transfer function at both mini-
mum and maximum input voltage and at both full load
and the Run-to-Hysteretic mode load current boundary.
Hysteretic Mode Current Setting
The voltage on the HMI pin sets the load current boundary
between Run mode and Hysteretic mode. This setting
enables the designer to trade-off efficiency and output
voltage ripple at low output current. The output voltage ripple
is higher in Hysteretic mode as compared with Run mode.
Many systems can tolerate higher power supply ripple at
light loads because the reduced load induced ripple. The
designer should select the load current boundary based
upon converter efficiency characteristics and known load
characteristics. For example, a HIP5020 converter powering
a microprocessor load might select the HMI boundary
between the sleep and active states of operation.
Be sure to note the phase margin and the gain margin.
The single component R1 can compensate the control loop if
the detailed characteristics of the output capacitor, bandwidth,
and switching frequency meet strict requirements. The
bandwidth (or unity gain frequency) must be much greater
than the ESR zero frequency (f
) and much less than twice
ESR
the switching frequency. Additionally the break frequency of
output capacitor’s ESL must be much greater than the
switching frequency. If these conditions exist, the ESR zero
provides the necessary phase boost. However, note that the
ESR is not a well controlled parameter and is variable with
temperature and aging. Select R1 for the proper
The ripple voltage is highest for load current just below the
mode boundary. The ripple voltage is a function of the
hysteresis width, the resistors R1 and R2, the hysteretic
current setting (HMI) and the output capacitor ESR as
described in the Hysteretic Mode section.
compensation gain and confirm the selection with closed-loop
measurements. Additionally determine the worst case ESR
variation and estimate this effect on converter stability.
Output Voltage Setting
The resistor divider R1 and R2 sets the output voltage as a
function of the reference voltage. Select R1 to achieve the
desired bandwidth then determine R2 from:
1.26
Figure 9 shows the efficiency versus load for two different
V
settings. The efficiency at light load current is higher
HMI
with a higher settings. The efficiency at light load current is
higher V setting. However, the more efficient design has
-------------------------
R2 = R1 •
HMI
V
– 1.26
O
2-23
HIP5020
a higher ripple voltage for load current between 0.2A and
0.6A. If the load is sensitive to power supply ripple during this
load range, the lower efficiency HMI setting should be used.
R5 and C10 form a low-pass filter for the bias supply (V ) of
INF
the reference and hysteretic comparator functions. A 2kΩ
resistor for R5 and a 0.1µF Capacitor for C10 is recommended.
Locate C10 directly across the VINF and GND pins.
100
Thermal Design
CIRCUIT 1: V = 6VDC
IN
o
T
= 25 C
A
The power ground (PGND) pins of the SOIC package
provide a thermal conduction path for removing heat from
the HIP5020. Inside the package, the HIP5020 die is
mounted on a copper structure with connections to PGND
(pins 6, 7, 8, 9, 20, 21, 22, and 23). Solder the SOIC to a
circuit board with a copper ground plane to remove heat
from the package. With good component layout and 3
square inches of copper ground plane, the junction-to-
95
90
85
80
75
70
V
= 0.5V
HMI
V
= 0.15V
HMI
o
ambient thermal resistance is 36 C/W. Most of the
converter’s power dissipation will be in the HIP5020 and the
output inductor, L1. The power dissipated in the HIP5020
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
can be estimated from the converter’s full load efficiency and
2
subtracting the inductor’s power dissipation (I • R DC ). The
O
junction temperature rise above ambient is this power
multiplied by the thermal resistance. Use the HIP5020
design and simulation software for more accurate thermal
simulations. Be sure to keep the junction temperature below
125 C for reliable operation. Careful component layout and
good thermal design maximized the efficiency and reliability
of the converter.
FIGURE 9. EFFICIENCY vs LOAD CURRENT
The voltage on the HMI pin is used to clamp the lower limit of
error amplifier output voltage and the minimum peak
inductor current. This voltage is set by a 20µA current source
and the resistor, R4.
o
Soft-Start
Set the Soft-Start capacitor, C8 so that the output voltage
ramps to its final value with a current between the hysteretic
mode current and the rated current. The minimum value for
C8 can be determined from:
Detailed Characteristics
Charge Pump Regulator
The charge pump regulator supplies control power (V ) to
CC
the internal functions of the HIP5020. The charge pump
operates for input voltage levels below 9.8V and is disabled
for input voltages above 9.8V. Figure 10 shows the charge
–5
--------------
REF
10
V
C8
= T
•
SOFT
MIN
pump output voltage (V ) as a function of the input voltage
(V ). For input voltages below 9.8V nominally, the charge
IN
C1 • V
CC
O
where T
= ---------------------
SOFT
3A
pump operates in two regions - as a voltage doubler and as
a voltage regulator. The charge pump operates as a normal
Larger values for C8 will extend the soft-start interval, T
Any loading during the Start-up mode lengthens T
.
SOFT
voltage doubler when V
is below approximately 14.8V.
to approximately 14.8V in the
regulation region. For input voltages above 9.8V, the charge
.
CC
SOFT
The charge pump limits V
CC
Bypass and Filter Capacitors
Capacitor C12 supplies the leading edge PWM current each
switching cycle. A high quality (X7R dielectric ceramic)
0.1µF surface-mount capacitor is recommended. Locate
C12 directly across the VIN and PGND pins.
pump is disabled and V
diode drop.
follows the input voltage less a
CC
Bypass the internal V
supply with a high quality (X7R
CC
dielectric ceramic) surface-mount capacitor (C4). Locate C4
directly across the VCC and GND pins.
The value for capacitor C5 should be selected as described in
the Charge Pump Regulator above. A single high quality (X7R
dielectric ceramic) capacitor is usually adequate. Some
applications may need a high capacitance, electrolytic for
charge-pump operation. For these applications, a high quality
capacitor in parallel with the electrolytic is recommended.
Locate C5 directly across the CP+ and CP- pins.
2-24
HIP5020
applications and external loads. Be sure that the load can
tolerate the V voltage variation with input voltage. During
20
15
CC
Hysteretic Mode, the external load should be removed when
the converter turns off. Note that the charge pump and
oscillator are disabled with RUN low (see Operating Modes).
The external load could cause an under-voltage lockout trip
and subsequent soft-start cycle.
REGULATION
REGION
VOLTAGE
DOUBLER
REGION
Light Load Power Dissipation
10
5
The converter efficiency and power dissipation at light load is
mainly a function of the bias supplied to the HIP5020. Figure
12 shows the input current as a function of the input voltage
CHARGE
PUMP
DISABLED
for the two states of the RUN signal. I is summation of both
IN
0
5
10
15
20
the current into the VIN and VINF pins. The curve for I with
IN
the RUN signal High does not include the gate drive power.
INPUT VOLTAGE (V)
FIGURE 10. CHARGE PUMP REGULATOR INPUT VOLTAGE
CHARACTERISTICS
The gate drive power is a function of the MOSFETs gate
charge, voltage and switching frequency. Figure 13 shows
the combined gate energy required by the internal
MOSFETs with the charge pump characteristics. To
determine the total bias power:
14
V
= 8.65VDC
IN
1. Multiply the value in Figure 13 by the switching frequency.
CIRCUIT 3
2. Add the product of the voltage and current from the RUN
= High curve in Figure 12.
12
10
8
V
= 12VDC
IN
3. Multiply by the ratio of RUN time to the Hysteretic period.
4. Add the product of the voltage and current from the RUN
= Low curve in Figure 12.
V
= 5VDC
IN
0.4
0.3
1
2
5
10
20
50
100
EXTERNAL LOAD (MADC)
0.2
0.1
0.0
FIGURE 11. BIAS VOLTAGE (V ) vs EXTERNAL LOAD
CC
CURRENT
100
RUN = HIGH
CT - GND
80
0
5
10
(V)
15
20
V
IN
60
40
20
FIGURE 13. MOSFET GATE ENERGY CHARACTERISTICS vs
INPUT VOLTAGE
MOSFET On-Resistance
Conduction losses are a significant portion of the power
dissipation in a DC-DC converter. The HIP5020 conduction
losses are the product of the square of the average output
RUN = LOW
0
current and the MOSFET on-resistance - r
. The
DS(ON)
0
5
10
(V)
15
20
V
r
of the MOSFETs is a function of V and junction
IN
DS(ON)
temperature. V
CC
changes with the input voltage as shown
FIGURE 12. BIAS POWER CHARACTERISTICS
CC
in Figure 10 above. Figure 14 shows the maximum r
DS(ON)
The charge pump can be used to supply current for external
loads on the VCC pin. Figure 11 shows the regulation
characteristics of the charge pump in the various operating
regions. These characteristics are for a DC-DC converter
(Circuit 3) operating at 100kHz and with 1µF capacitors for C4
and C5. The charge pump may not be suitable for some
of both MOSFETs as a function of input voltage for a junction
o
temperature of 25 C. The junction temperature of the
HIP5020 also effects r
. Figure 15 shows the r
DS(ON)
DS(ON)
as a function of temperature for three gate voltage levels.
2-25
HIP5020
The r
can be estimated at a given input voltage and
Application Hints
DS(ON)
junction temperature as follows:
Short Duration RUN Interval
1. Assume that the gate voltage is equal to V . Find the
CC
Some converter designs may observe a series of short run
interval pulses (RUN = High) in hysteretic mode that can
reduce the light-load efficiency. The run interval is
interrupted by the voltage on the FB pin crossing over the
Upper Hysteretic Trip Level before the output capacitor gains
sufficient charge. This operation can be caused by a number
of factors:
o
gate voltage at 25 C from Figure 10.
2. Multiply this number by the r
Interpolate as necessary.
shown in Figure 15.
DS(ON)
0.10
0.09
0.08
0.07
0.06
0.05
o
T
= 25 C
J
1. Poor physical layout. Use wide traces to connect the pow-
er components.
2. Poor component choice. Use only power supply specific
electrolytic capacitors. Additionally use ceramic capaci-
tors in parallel with the bulk electrolytic capacitors.
3. Sudden voltage excursions across the output capacitor
and the error amplifier output.
Be sure to clear up any layout problems first. Poor layout not
only causes efficiency problems, but can be a source of
noise for surrounding circuits. If the short run interval is still
observed, a capacitor can be added across each R2 and R4.
2
4
6
8
10
12
14
16
18 20
INPUT VOLTAGE
During the transition of RUN from low to high, the voltage on
the FB pin starts at the Lower Hysteretic Trip Level. The error
FIGURE 14. r
vs INPUT VOLTAGE
DS(ON)
amplifier activates and its output slews to V
. This causes
HMI
an increase in V due to current in the compensation
FB
140
130
120
110
100
90
capacitor. Adding a capacitor across R4 slows the rate of HMI
voltage increase during the transition of RUN from low to high
and decreases error amplifier slew rate.
Voltage excursions across the output capacitor and circuit
board traces after the transition of RUN from low to high
V
= 8V
G-S
V
= 12V
G-S
results in an increase in V . As the inductor current ramps to
FB
the HMI level, the output voltage increases due to the output
capacitor’s ESR and ESL. This voltage spike is attenuated by
the resistor divider, R1 and R2 but still appears on the FB pin.
A small capacitor across R2 further attenuates any output
voltage spikes. The small capacitor eliminates the short
duration RUN interval, but will not reduce the output voltage
spikes. A better solution may be a better, higher quality output
capacitor with low ESR and ESL.
80
V
= 18V
G-S
70
60
0
20
40
60
80
100
120
o
TEMPERATURE ( C)
FIGURE 15.
r
vs JUNCTION TEMPERATURE
DS(ON)
Bootstrap and Phase Diodes
The bootstrap function requires a diode D1 to supply gate
drive power for the upper N-Channel MOSFET. A Schottky is
recommended for most applications due to its fast switching
speed and low forward voltage. A fast-recovery diode can be
used in low switching frequency, cost sensitive applications.
Many applications will not need a Schottky diode from phase
to ground. The internal body diode of the integrated
MOSFET is sufficiently fast. A small Schottky diode can be
added to improve the light load efficiency. This diode only
conducts during the short intervals (< 50ns) before and after
the lower MOSFET conducts. In most cases, a Schottky
rated for 0.5A is sufficient.
2-26
HIP5020
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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2-27
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