HS-1840BEH_技术文档

Rad-Hard 16 Channel BiCMOS Analog Multiplexer with

High-Z Analog Input Protection

HS-1840ARH, HS-1840AEH,

HS-1840BRH, HS-1840BEH

Features

• Electrically Screened to SMD # 5962-95630

• QML Qualified per MIL-PRF-38535 Requirements

• Pin-to-Pin for Intersil’s HS-1840RH and HS-1840/883S

• Improved Radiation Performance

The HS-1840ARH, HS-1840AEH, HS-1840BRH and HS-1840BEH are

radiation hardened, monolithic 16 channel multiplexers constructed

with the Intersil Rad-Hard Silicon Gate, bonded wafer, Dielectric

Isolation process. They are designed to provide a high input impedance

to the analog source if device power fails (open), or the analog signal

voltage inadvertently exceeds the supply by up to ±35V, regardless of

whether the device is powered on or off. Excellent for use in redundant

applications, since the secondary device can be operated in a standby

unpowered mode affording no additional power drain. More

significantly, a very high impedance exists between the active and

inactive devices preventing any interaction. One of sixteen channel

selections is controlled by a 4-bit binary address plus an Enable-Inhibit

input which conveniently controls the ON/OFF operation of several

multiplexers in a system. All inputs have electrostatic discharge

protection. The HS-1840ARH, HS-1840AEH, HS-1840BRH and

HS-1840BEH are processed and screened in full compliance with

MIL-PRF-38535 and QML standards. The devices are available in a

28 Ld SBDIP and a 28 Ld Ceramic Flatpack.

5

- Gamma Dose (γ) 3x10 RAD(Si)

• Improved r

DS(ON)

Linearity

• Improved Access Time 1.5µs (Max) Over Temp and Post Rad

• High Analog Input Impedance 500MΩ During Power Loss (Open)

• ±35V Input Overvoltage Protection (Power On or Off)

• Dielectrically Isolated Device Islands

• Excellent in Hi-Rel Redundant Systems

• Break-Before-Make Switching

• No Latch-Up

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are contained in

SMD 5962-95630. A “hot-link” is provided on our homepage for

downloading:

http://www.landandmaritime.dla.mil/Downloads/MilSpec/Smd/956

30.pdf

April 6, 2012

FN4355.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Ordering Information

INTERNAL

MKT. NUMBER

(Note)

ORDERING

NUMBER

TEMP. RANGE

(°C)

PART

MARKING NO.

PACKAGE

(RoHS Compliant)

5962F9563002QXC

HS1-1840ARH-8

-55 to +125

Q 5962F95 63002QXC

Q 5962F95 63002QYC

Q 5962F95 63002VXC

Q 5962F95 63002VYC

HS1- 1840ARH /PROTO

HS9- 1840ARH /PROTO

Q 5962R95 63002TXC

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

5962F9563002QYC

5962F9563002VXC

5962F9563002VYC

HS1-1840ARH/PROTO

HS9-1840ARH/PROTO

HS1-1840ARH-T

HS9-1840ARH-8

HS1-1840ARH-Q

HS9-1840ARH-Q

HS1-1840ARH/PROTO

HS9-1840ARH/PROTO

HS1-1840ARH-T

HS0-1840ARH-Q

HS0-1840AEH-Q

HS1-1840AEH-Q

HS9-1840AEH-Q

HS0-1840BEH-Q

HS1-1840BEH-Q

HS9-1840BEH-Q

HS1-1840BRH-8

HS9-1840BRH-8

HS1-1840BRH-Q

HS9-1840BRH-Q

HS1-1840BRH/PROTO

HS9-1840BRH/PROTO

HS0-1840BRH-Q

5962F9563002V9A

5962F9563004V9A

5962F9563004VXC

5962F9563004VYC

5962F9563005V9A

5962F9563005VXC

5962F9563005VYC

5962F9563003QXC

5962F9563003QYC

5962F9563003VXC

5962F9563003VYC

HS1-1840BRH/PROTO

HS9-1840BRH/PROTO

5962F9563003V9A

Q 5962F95 63004VXC

Q 5962F95 63004VYC

28 Ld SBDIP

28 Ld Flatpack

Q 5962F95 63005VXC

Q 5962F95 63005VYC

Q 5962F95 63003QXC

Q 5962F95 63003QYC

Q 5962F95 63003VXC

Q 5962F95 63003VYC

HS1- 1840BRH /PROTO

HS9- 1840BRH /PROTO

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

28 Ld Flatpack

28 Ld SBDIP

28 Ld Flatpack

NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with

both SnPb and Pb-free soldering operations.

Pin Configurations

HS1-1840ARH, HS1-1840AEH, HS1-1840BRH

(28 LD SBDIP) CDIP2-T28

TOP VIEW

HS9-1840ARH, HS9-1840AEH, HS9-1840BRH

(28 LD FLATPACK) CDFP3-F28

TOP VIEW

+V

1

2

3

4

5

6

7

8

9

28 OUT

S

+V

S

NC

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OUT

NC

27 -V

S

-V

S

IN 8

2

3

26 IN 8

25 IN 7

24 IN 6

23 IN 5

22 IN 4

21 IN 3

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

IN 7

4

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 6

5

IN 5

6

IN 4

7

IN 3

8

IN 2

9

IN 1

10

11

12

13

14

20

IN 2

ENABLE

ADDR A0

ADDR A1

ADDR A2

IN 10 10

IN 9 11

GND 12

19 IN 1

GND

18 ENABLE

17 ADDR A0

16 ADDR A1

15 ADDR A2

(+5V ) V

S

REF

ADDR A3

(+5V ) V

13

ADDR A3 14

S

REF

FN4355.5

April 6, 2012

2

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Functional Diagram

V

DD

IN1

A0

1

MAINSWITCH 1

A1

A2

A3

DIGITAL

ADDRESS

OUT

IN16

16

EN

MAINSWITCH 16

ADDRESS INPUT

BUFFER AND

LEVEL SHIFTER

DECODERS

MULTIPLEX

SWITCHES

NOTE: MAINSWITCH INXX: SWITCH ON, BODY TIED TO SOURCE

SWITCH OFF, BODY TIED TO VCC-0.7V

TABLE 1. TRUTH TABLE

A3

A2

A1

X

L

A0

X

L

EN

H

L

“ON” CHANNEL

X

L

X

L

None

1

L

H

L

2

L

H

L

3

L

H

L

4

L

H

L

5

L

H

L

6

L

H

L

7

L

H

L

8

H

9

L

H

L

10

11

12

13

14

15

16

L

H

L

H

L

H

L

H

L

H

FN4355.5

April 6, 2012

3

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Burn-In/Life Test Circuits

R

+V

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+V

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

S

-V

S

R

3

R

3

R

4

5

6

7

8

9

10

11

12

13

14

10

11

12

13

14

F5

F2

GND

F1

F3

GND

F4

V

R

NOTE:

R = 1kΩ ±5%, 1/4W.

= C = 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.

NOTE:

V + = +15.5V ±0.5V, V - = -15.5V ±0.5V.

S

C

1

2

R = 1kΩ ±5%.

V + = 15.5V ±0.5V, V - = -15.5V ±0.5V, V = 15.5 ±0.5V

S

R

C

D

= C = 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM.

1

2

= D = 1N4002, 1 EACH PER BOARD, MINIMUM.

2

INPUT SIGNALS:

SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%.

F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.

FIGURE 2. .STATIC BURN-IN TEST CIRCUIT

FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT

NOTES:

1. The above test circuits are utilized for all package types.

2. The Dynamic Test Circuit is utilized for all life testing.

Irradiation Circuit

HS-1840ARH, HS-1840AEH, HS-1840BRH

+15V

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

-15V

NC

1kΩ

3

+1V

4

5

6

7

8

9

10

11

12

13

14

+5V

NOTE:

3. All irradiation testing is performed in the 28 lead CERDIP package.

FN4355.5

April 6, 2012

4

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Die Characteristics

DIE DIMENSIONS:

ASSEMBLY RELATED INFORMATION:

(2820µmx4080µm x 483µm ±25.4μm)

111 milsx161 milsx19 mils ±1 mil

Substrate Potential:

Unbiased (DI)

INTERFACE MATERIALS:

Glassivation:

ADDITIONAL INFORMATION:

Worst Case Current Density:

Type: PSG (Phosphorus Silicon Glass)

Thickness: 8.0kÅ ±1kÅ

Modified SEM

Transistor Count:

Top Metallization:

407

Type: AlSiCu

Thickness: 16.0kÅ ±2kÅ

Process:

Radiation Hardened Silicon Gate,

DI Wafer, Dielectric Isolation

Backside Finish:

Silicon

Metallization Mask Layout

HS-1840ARH, HS-1840BRH

IN8

ENABLE

A0

-V

A1

OUT

+V

A2

A3

V

REF

IN16

GND

FN4355.5

April 6, 2012

5

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

c1 LEAD FINISH

D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)

28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

-A-

-D-

E

INCHES

MIN

MILLIMETERS

BASE

(c)

METAL

SYMBOL

MAX

0.232

0.026

0.023

0.065

0.045

0.018

0.015

1.490

0.610

MIN

-

MAX

5.92

NOTES

b1

A

b

-

2

3

-

M

A

M

(b)

0.014

0.045

0.023

0.008

-

0.36

1.14

0.58

0.20

-

0.66

-B-

b1

b2

b3

c

0.58

SECTION A-A

S

D

bbb

C

A - B

1.65

D

1.14

4

2

3

-

BASE

S2

Q

PLANE

0.46

-C-

SEATING

PLANE

c1

D

0.38

L

37.85

15.49

S1

b2

eA

A A

E

0.500

12.70

-

e

eA/2

aaa M C A - B S D S

b

c

e

0.100 BSC

2.54 BSC

-

eA

eA/2

L

0.600 BSC

0.300 BSC

15.24 BSC

7.62 BSC

-

ccc

M

C A - B S D S

-

NOTES:

0.125

0.200

3.18

5.08

-

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

Q

0.015

0.005

0.060

0.38

0.13

1.52

5

6

7

-

S1

S2

α

-

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

o

90

105

90

105

aaa

bbb

ccc

M

-

0.015

0.030

0.010

0.0015

-

0.38

0.76

0.25

0.038

-

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

-

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

-

2

8

N

28

5. Dimension Q shall be measured from the seating plane to the

base plane.

Rev. 0 5/18/94

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN4355.5

April 6, 2012

6

HS-1840ARH, HS-1840AEH, HS-1840BRH, HS-1840BEH

Ceramic Metal Seal Flatpack Packages (Flatpack)

K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)

A

28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A

e

INCHES

MIN

MILLIMETERS

PIN NO. 1

ID AREA

SYMBOL

MAX

0.115

0.022

0.019

0.009

0.006

0.740

0.520

0.550

-

MIN

1.14

0.38

0.10

-

MAX

2.92

0.56

0.48

0.23

0.15

18.80

13.21

13.97

-

NOTES

D

A

b

0.045

0.015

0.004

-

-A-

-B-

S1

b1

c

-

b

c1

D

-

E1

3

-

0.004

Q

H

A - B

D

0.036

H

A - B

D

S

M

S

M

S

C

E

0.460

-

11.68

-

E

E1

E2

E3

e

3

-

-D-

A

0.180

0.030

4.57

0.76

-H-

-C-

-

7

-

L

E2

L

E3

0.050 BSC

1.27 BSC

SEATING AND

BASE PLANE

c1

LEAD FINISH

k

0.008

0.250

0.026

0.00

-

0.015

0.370

0.045

-

0.20

6.35

0.66

0.00

-

0.38

9.40

1.14

-

2

-

L

BASE

METAL

Q

S1

M

N

8

6

-

(c)

b1

0.0015

0.04

M

(b)

28

-

SECTION A-A

Rev. 0 5/18/94

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark. Alternately, a tab (dimension k)

may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the lim-

its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass

overrun.

4. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness. The maximum lim-

its of lead dimensions b and c or M shall be measured at the cen-

troid of the finished lead surfaces, when solder dip or tin plate

lead finish is applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric mate-

rials shall be molded to the bottom of the package to cover the

leads.

8. Dimension Q shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension Q minimum

shall be reduced by 0.0015 inch (0.038mm) maximum when sol-

der dip lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

FN4355.5

April 6, 2012

7


型号：	HS-1840BEH
厂家：	Intersil
描述：	Rad-Hard 16 Channel BiCMOS Analog Multiplexer with High-Z Analog Input Protection 抗辐射16通道的BiCMOS模拟多路复用器具有高阻抗模拟输入保护复用器
文件：	总7页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HS-1840BEH [INTERSIL]

相关型号：

HS-1840BRH

HS-1840RH

HS-1840RH/883S

HS-1840RH883S

HS-2

HS-201HSRH

HS-201HSRH_06

HS-201HSRH_13

HS-210-40-75

HS-210-40-75-W

HS-2100RH

HS-22620RH