HS-3374RH [INTERSIL]
Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter; 抗辐射的8位双向CMOS / TTL电平转换器
| 型号： | HS-3374RH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter |
| 文件： | 总6页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-3374RH
Radiation Hardened
8-Bit Bidirectional CMOS/TTL Level Converter
March 1996
Features
Pinout
HS-3374RH
MIL-STD-1835, CDIP2-T22
(SBDIP)
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-9XXXX and Intersil’ QM Plan
TOP VIEW
• Radiation Hardened EPI-CMOS
- Total Dose 1 x 105 RAD(Si)
VDD
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
22
21
VCC
B0
- Latch-Up Immune > 1 x 1012 RAD (Si)/s (Note 1)
• Low Propagation Delay Time
20 B1
19 B2
18 B3
- Typical CMOS to TTL Pre-RAD 40ns
- Typical CMOS to TTL Post 100K RAD 40ns
- Typical TTL to CMOS Pre-RAD 50ns
- Typical TTL to CMOS Post 100K RAD 50ns
TTL
CMOS
INPUT/OUTPUT
INPUT/OUTPUT
17
B4
• Low Standby Power
16 B5
15 B6
• +10V CMOS and +5V TTL Power Supply Inputs
• Eight Non-inverting Three-State Input/Output Channels
• No External TTL Input Pull-Up Resistors Required
• High TTL Sink Current
14
13
12
B7
ENABLE 10
11
DISABLE
NC
GND
• Equivalent to Sandia SA2996
• Military Temperature Range -55oC to +125oC
Description
Functional Diagram
The Intersil HS-3374RH is
a radiation hardened 8-bit
bidirectional level converter designed to interface CMOS logic
levels with TTL logic levels in radiation hardened bus oriented
systems. The HS-3374RH is fabricated using a radiation
hardened EPI-CMOS process and features eight parallel
bidirectional buffer/level converters.
VDD = 1
VCC = 22
GND = 11
DISABLE
13
8
8
Two control inputs, ENABLE and DISABLE, are used to deter-
mine the direction of data flow, and to set both the in puts and
outputs in the high impedance state. The control inputs may be
driven by either TTL or CMOS logic drivers capable of sinking
one standard TTL load.
TTL
OUT (IN)
14-21
CMOS
IN/OUT
2-9
LEVEL
SHIFTER
ENABLE
10
The HS-3374RH is a non-inverting version of the industry
standard CD40116. The non-inverting outputs of the
HS-3374RH reduce PC board chip count by eliminating the
need to restore data back to a non-inverted format.
NOTE:
10
1. For operation at 10V and transient levels above 1 x 10 RAD (Si)/s,
please refer to Application Note 401.
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
HS1-3374 (SAMPLE)
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
22 Lead SBDIP
o
o
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
-55 C to +125 C
o
o
-55 C to +125 C
22 Lead SBDIP
22 Lead SBDIP
o
+25 C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Spec Number 518052
File Number 3038.1
1
Specifications HS-3374RH
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+11.0V
I/O Voltage Applied. . . . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JC
JA
SBDIP Package. . . . . . . . . . . . . . . . . .
74.8
12.3
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
Maximum Package Power Dissipation at +125 C
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.67W
If Device Power Exceeds Package Dissipation Capability, Provide
Heat Sinking or Derate Linearly at the Following Rate:
o
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4mW/ C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range
VDD . . . . . . . . . . . . . +9.5V to +10.5V Input Low Voltage (CMOS) . . . . . . . . . . . . . . . . . . . . . . . GND to 1V
VCC . . . . . . . . . . . . +4.75V to +5.25V Input High Voltage (CMOS). . . . . . . . . . . . . . . . . .VDD-1.0V to VDD
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input Voltage Range
Input Low Voltage (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V
Input High Voltage (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V
Data Inputs (CMOS) . . . . . . . . . . . . . . . . . . .GND-0.3 to VDD+0.3
Data Inputs (TTL) . . . . . . . . . . . . . . . . . . . . .GND-0.3 to VCC+0.3
Enable, Disable Inputs . . . . . . . . . . . . . . . . .GND-0.3 to VDD+0.3
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
ENABLE AND DISABLE IINPUTS
o
o
Input Leakage Current
IIH CMOS VDD = 10.5V, VCC = 5.25V,
VIN = 10.5V, Floating Outputs
1, 2, 3
-55 C, +25 C,
-
1
µA
o
+125 C
TTL INPUT TO CMOS OUTPUTS
o
o
Input Leakage Current
IIL IIH
VDD = 10.5V, VCC = 5.25V,
VIN = 0.8V, Other Inputs at 2.8V
1, 2, 3
1, 2, 3
1, 2, 3
-55 C, +25 C,
-1
-
-
1
-
µA
µA
V
o
+125 C
o
o
VDD = 10.5V, VCC = 5.25V,
VIN = 2.8V, other Inputs = 0.8V
-55 C, +25 C,
o
+125 C
o
o
High Level Output
Voltage
VOH
VOL
VDD = 9.5V, VCC = 4.75V,
VIH = 2.8V, VIL = 0.8V,
IOH = -2.0mA
-55 C, +25 C,
9
o
+125 C
o
o
Low level output
Voltage
VDD = 10.5V, VCC = 5.25V,
VIH = 2.8V, VIL 0.8V,
IOL = 2.0mA
1, 2, 3
-55 C, +25 C,
-
0.5
V
o
+125 C
CMOS to TTL OUTPUTS
o
o
High Level Output
Voltage
VOH
VOL
VDD = 9.5, VCC = 4.75V,
VIH = 8.5V, VIL = 1.0V,
IOH = -2.0mA
1, 2, 3
1, 2, 3
-55 C, +25 C,
3
-
-
V
V
o
+125 C
o
o
Low Level Output
Voltage
VDD = 10.5V, VCC = 5.25V,
VIH = 9.5V, VIL = 1.0V,
IOL = 11mA
-55 C, +25 C,
0.4
o
+125 C
o
o
Output Leakage
Current
IOZL
IOZH
VDD = 10.5V, VCC = 5.25V,
VIN = 0V, All other pins high
1, 2, 3
1, 2, 3
-55 C, +25 C,
-10
-
-
µA
µA
o
+125 C
o
o
VDD = 10.5V, VCC = 5.25V,
VIN = 2.8V, All other pins at
GND
-55 C, +25 C,
10
o
+125 C
Spec Number 518052
2
Specifications HS-3374RH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
o
Functional Tests
FT
CMOS:
7, 8A, 8B
-55 C, +25 C,
-
-
-
o
1.) VDD = 10.5V, VCC = 5.25V
2.) VDD = 9.5V, VCC = 4.75V,
VIH = VDD-1V, VIL = 1V
TTL:
+125 C
1.) VDD = 10.5V, VCC = 5.25V
2.) VDD = 9.5V, VCC = 4.75V,
VIH = 2.8V, VIL = 0.8V
o
o
Static Current 1
Static Current 2
Static Current
SIDD1
SIDD2
SICC
VDD = 10.5V, VCC = 5.25V,
EN = 2.8V, DISABLE = 2.8V,
Floating Outputs
1, 2, 3
1, 2, 3
1, 2, 3
-55 C, +25 C,
-
-
-
300
100
5
µA
µA
µA
o
+125 C
o
o
VDD = 10.5V, VCC = 5.25V, EN
= 0V, DISABLE = 2.8V, Floating
Outputs
-55 C, +25 C,
o
+125 C
o
o
VDD = 10.5, VCC = 5.25V,
EN = 0V, DISABLE = 2.8V,
Floating Output, Measure VCC
pin
-55 C, +25 C,
o
+125 C
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A SUB-
LIMITS
PARAMETER
SYMBOL
GROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
o
Propagation Delay Times CMOS/TTL
Data In to Data Out
TPHLCT
9, 10, 11
-55 C, +25 C, +125 C
-
-
-
-
-
-
-
-
-
-
-
40
ns
o
o
o
Propagation Delay Times CMOS Data
In to Data Out
TPLHCT
TPHLTC
TPLHTC
TTHLCT
TTLHCT
TTHLTC
TTLHTC
TPHZTC
TPZHTC
TPLZTC
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
50
85
70
20
70
50
50
90
90
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
o
o
Propagation Delay Times CMOS/TTL
Data In to Data Out
-55 C, +25 C, +125 C
o
o
o
Propagation Delay Time TTL/CMOS
Data In to Data Out
-55 C, +25 C, +125 C
o
o
o
Transition Time CMOS/TTL
Input/Output
-55 C, +25 C, +125 C
o
o
o
Transition Time CMOS/TTL
Input/Output
-55 C, +25 C, +125 C
o
o
o
Transition Time CMOS/TTL
Input/Output
-55 C, +25 C, +125 C
o
o
o
Transition Time CMOS/TTL
Input/Output
-55 C, +25 C, +125 C
o
o
o
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
-55 C, +25 C, +125 C
o
o
o
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
-55 C, +25 C, +125 C
o
o
o
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
-55 C, +25 C, +125 C
Spec Number 518052
3
Specifications HS-3374RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
GROUP A SUB-
PARAMETER
SYMBOL
GROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
o
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
TPZLTC
9, 10, 11
-55 C, +25 C, +125 C
-
-
-
-
-
90
ns
o
o
o
Propagation Delay Time CMOS/TTL
Disable to TTL Out
TPHZCT
TPZHCT
TPLZCT
TPZLCT
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
70
ns
ns
ns
ns
o
o
o
Propagation Delay Time CMOS/TTL
Disable to TTL Out
-55 C, +25 C, +125 C
130
120
125
o
o
o
Propagation Delay Time CMOS/TTL
Disable to TTL Out
-55 C, +25 C, +125 C
o
o
o
Propagation Delay Time CMOS/TTL
Disable to TTL Out
-55 C, +25 C, +125 C
NOTE: Timings are measured with the following conditions: CL = 100pF, VDD = 9.5V, VCC = 4.75V, VIH = 8.5V (2.8V), VIL = 1.0V (0.8V).
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
o
Input, Output Capacitance
CMOS
CI/O
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
+25 C
-
13
pF
o
Input Capacitance
CIN
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
+25 C
-
-
15
17
pF
pF
o
Input, Output Capcitance
TTL
CI/O
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
+25 C
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters
are characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number 518052
4
HS-3374RH
Functional Block Diagram
1 OF 8 IDENTICAL CIRCUITS
VDD
VDD
VCC
DISABLE
LEVEL
SHIFTER
D
E
VCC
13
B1 TTL
OUTPUT
(INPUT)
2 (3, 4, 5, 6, 7, 8, 9)
A1 CMOS
INPUT (OUTPUT)
VDD
GND
GND
VDD
D
ENABLE
10
21 (20, 19,
18, 17, 16,
15, 14)
LEVEL
SHIFTER
LEVEL
SHIFTER
E
GND
GND
NOTES:
1. Enable and disable are TTL type inputs
2. D and E outputs are common to all 8 channels
TRUTH TABLE
INPUT (OUTPUT)
TERMINAL
OUTPUT (INPUT)
TERMINAL
ENABLE
DISABLE
FUNCTION
DATA
NUMBER
DATA
NUMBER
X
1
0
0
1
1
Convert CMOS Level to TTL Level
Convert TTL Level to CMOS Level
High Impedance (Z)
A0
2
3
4
5
6
7
8
9
B0
21
20
19
18
17
16
15
14
A1
B1
A2
B2
0 = Low Level 1 = High Level X = Don’t Care
Z = High Impedance on Both CMOS and TTL sides.
A3
B3
NOTE: An important caveat that is applicable to CMOS devices in
general is that unused inputs should never be left floating. This rule
applies to inputs connected to a three-state bus. The need for
external pull-up resistors during three-state bus conditions is
eliminated by the presence of regenerative latches on the following
HS-3374RH pins: A0 - 7.
A4
B4
A5
B5
A6
B6
A7
B7
The functional block diagram depicts one of these pins with the
regenerative latch. When the CMOS driver assumes the high
impedance state, the latch holds the bus in whatever logic state
(high or low) it was before the three-state condition. A transient
drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required to
switch the latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
* WARNING: Do not activate the Disable input by hardwiring to any
TTL input pins. This is an incorrect mode of operation.
Spec Number 518052
5
HS-3374RH
Metallization Topology
DIE DIMENSIONS:
89.4 mils x 76.0 mils x 14 mils ±1 mil
METALLIZATION:
Type: AlSi
Thickness: 8kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 11kÅ ±2kÅ
Metallization Mask Layout
HS-3374RH
(20) B1
(19) B2
A2 (4)
A3 (5)
(18) B3
(17) B4
(16) B5
(15) B6
(14) B7
A4 (6)
A5 (7)
A6 (8)
A7 (9)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518052
6
相关型号：
©2020 ICPDF网 联系我们和版权申明