HS-80C86RH_00_技术文档

HS-80C86RH

TM

Data Sheet

August 2000

File Number 3035.2

Radiation Hardened 16-Bit CMOS

Microprocessor

Features

• Electrically Screened to SMD # 5962-95722

The Intersil HS-80C86RH high performance radiation

hardened 16-bit CMOS CPU is manufactured using a

hardened ﬁeld, self aligned silicon gate CMOS process. Two

modes of operation, MINimum for small systems and

MAXimum for larger applications such as multiprocessing,

allow user conﬁguration to achieve the highest performance

level. Industry standard operation allows use of existing

NMOS 8086 hardware and software designs.

• QML Qualiﬁed per MIL-PRF-38535 Requirements

• Radiation Performance

- Latch Up Free EPl-CMOS

- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

8

- Transient Upset. . . . . . . . . . . . . . . . . . . . >10 rad(Si)/s

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 500µA (Max)

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . 12mA/MHz (Max)

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

• Pin Compatible with NMOS 8086 and Intersil 80C86

• Completely Static Design DC to 5MHz

• 1MB Direct Memory Addressing Capability

• 24 Operand Addressing Modes

Detailed Electrical Speciﬁcations for these devices are

contained in SMD 5962-95722. A “hot-link” is provided

on our homepage for downloading.

www.intersil.com/spacedefense/space.asp

• Bit, Byte, Word, and Block Move Operations

Ordering Information

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary or Decimal

INTERNAL

TEMP. RANGE

o

ORDERING NUMBER

5962R9572201QQC

5962R9572201QXC

5962R9572201VQC

5962R9572201VXC

HS1-80C86RH/Proto

HS9-80C86RH/Proto

MKT. NUMBER

( C)

- Multiply and Divide

HS1-80C86RH-8

HS9-80C86RH-8

HS1-80C86RH-Q

HS9-80C86RH-Q

HS1-80C86RH/Proto

HS9-80C86RH/Proto

-55 to 125

• Bus-Hold Circuitry Eliminates Pull-up Resistors for CMOS

Designs

• Hardened Field, Self-Aligned, Junction-Isolated CMOS

Process

• Single 5V Power Supply

o

• Military Temperature Range . . . . . . . . . . . -35 C to 125 C

• Minimum LET for

Single Event Upset . . . . . . . . . . . . . 6MEV/mg/cm (Typ)

2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HS-80C86RH

Pinout

HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

MAX

MIN

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

1

2

40 VDD

39 AD15

3

38 AD16/S3

4

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MX

RD

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

RQ/GT0

RQ/GT1

LOCK

S2

(HOLD)

(HLDA)

(WR)

(M/IO)

(DT/R)

(DEN)

(ALE)

(INTA)

S1

S0

QS0

QS1

INTR

CLK

GND

TEST

READY

RESET

HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

MAX

VDD

MIN

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NC

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

2

AD15

NC

3

A16/S3

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MX

RD

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

(HOLD)

RQ/GT0

RQ/GT1 (HLDA)

LOCK

S2

(WR)

(M/IO)

(DT/R)

(DEN)

(ALE)

(INTA)

S1

S0

QS0

NMI

QS1

INTR

CLK

GND

TEST

READY

RESET

2

HS-80C86RH

Functional Diagram

BUS INTERFACE UNIT

EXECUTION UNIT

REGISTER FILE

RELOCATION

REGISTER FILE

DATA POINTER

AND

INDEX REGS

(8 WORDS)

SEGMENT REGISTERS

AND

INSTRUCTION POINTER

(5 WORDS)

BHE/S7

A19/S6

A16/S3

16-BIT ALU

FLAGS

4

16

3

AD15-AD0

BUS INTERFACE UNIT

INTA, RD, WR

DT/R, DEN, ALE, M/IO

4

6-BYTE

INSTRUCTION

QUEUE

TEST

INTR

NMI

LOCK

2

QS0, QS1

CONTROL AND TIMING

RQ/GT0, 1

2

HOLD

HLDA

3

S2, S1, S0

3

CLK RESET READY MN/MX GND

VDD

MEMORY INTERFACE

C-BUS

INSTRUCTION

STREAM BYTE

B+BUS

QUEUE

ES

CS

SS

BUS

INTERFACE

UNIT

DS

IP

EXECUTION UNIT

CONTROL SYSTEM

A-BUS

AH

AL

BL

CL

DL

ARITHMETIC/

LOGIC UNIT

BH

CH

DH

EXECUTION

UNIT

SP

BP

SI

FLAGS

DI

3

HS-80C86RH

Pin Descriptions

SYMBOL

NUMBER

TYPE

DESCRIPTION

The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these descriptions

is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).

AD15-AD0

2-16, 39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data

(T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW

during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.

Eight-bit oriented devices tied to the lower half would normally use AD0 to condition chip select functions

(See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

A19/S6

A18/S5

A17/S4

A16/S3

35-38

O

ADDRESS/STATUS: During T1, these are the four most signiﬁcant address lines for memory operations.

During I/O operations these lines are low. During memory and I/O operations, status information is

available on these lines during T2, T3, TW, T4. S6 is always zero. The status of the interrupt enable FLAG

bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are encoded.

This information indicates which segment register is presently being used for data accessing. These lines

are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant

sequence”.

S4

0

S3

0

Extra Data

Stack

0

1

0

Code or None

Data

1

BHE/S7

34

O

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable data

onto the most signiﬁcant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper

half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read,

write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus.

The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is held at high

impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or

“grant sequence”; it is LOW during T1 for the ﬁrst interrupt acknowledge cycle.

BHE

A0

0

1

Whole Word

1

Upper Byte from/to Odd Address

Lower Byte from/to Even Address

None

0

1

RD

32

O

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending

on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the HS-80C86RH

local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH

in T2 until the 80C86 local bus has ﬂoated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY

INTR

22

18

I

READY: is the acknowledgment from the addressed memory or I/O device that will complete the data

transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock Generator to

form READY. This signal is active HIGH. The HS-80C86RH READY input is not synchronized. Correct

operation is not guaranteed if the Setup and Hold Times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each

instruction to determine if the processor should enter into an interrupt acknowledge operation. If so, an

interrupt service routine is called via an interrupt vector lookup table located in system memory. INTR is

internally synchronized and can be internally masked by software resetting the interrupt enable bit. This

signal is active HIGH.

TEST

23

I

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock

cycle on the leading edge of CLK.

4

HS-80C86RH

Pin Descriptions (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

NMI

17

I

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An interrupt

service routine is called via an interrupt vector lookup table located in system memory. NMI is not

maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the

current instruction. This input is internally synchronized.

RESET

CLK

21

19

I

RESET: causes the processor to immediately terminate its present activity. The signal must change from

LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts execution, as described in the

Instruction Set description, when RESET returns LOW. RESET is internally synchronized.

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty

cycle to provide optimized internal timing.

VDD

GND

40

VDD: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for decoupling.

1, 20

GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is

recommended for decoupling.

MN/MX

33

I

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discussed

in the following sections.

The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are

unique to maximum mode are described below.

S0, S1, S2

26-28

O

STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during

TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and

I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a

bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These

status lines are encoded. These signals are held at a high impedance logic one state during “grant

sequence”.

S2

0

S1

0

S0

0

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

0

1

0

1

0

1

0

Code Access

Read Memory

Write Memory

Passive

1

0

1

0

1

5

HS-80C86RH

Pin Descriptions (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

RQ/GT0

RQ/GT1

31, 30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local

bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher

priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left unconnected. The

request/grant sequence is as follows (see RQ/GT Sequence Timing.)

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the

HS-80C86RH (pulse 1).

2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the HS-80C86RH to the requesting master

(pulse 2) indicates that the HS-80C86RH has allowed the local bus to float and that it will enter the

“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logically from

the local bus during “grant sequence”.

3. A pulse 1 CLK wide from the requesting master indicates to the HS-80C86RH (pulse 3) that the “hold”

request is about to end and that the HS-80C86RH can reclaim the local bus at the next CLK. The

CPU then enters T4 (or T1 if no bus cycles pending).

Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one idle

CLK cycle after each bus exchange. Pulses are active low.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during

T4 of the cycle when all the following conditions are met:

1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next cycle.

2. A memory cycle will start within 3 CLKs. Now the four rules for a currently active memory cycle

apply with condition number 1 already satisfied.

LOCK

29

O

LOCK: output indicates that other system bus masters are not to gain control of the system bus while LOCK

is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the

completion of the next instruction. This signal is active LOW, and is held at a HIGH impedance logic one

state during “grant sequence”. In MAX mode, LOCK is automatically generated during T2 of the first INTA

cycle and removed during T2 of the second INTA cycle.

QS1, QS0

24, 25

QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is

performed.

QS1 and QS2 provide status to allow external tracking of the internal HS-80C86RH instruction queue.

Note that QS1, QS0 never become high impedance.

QS1

QS0

0

1

0

1

0

1

No Operation

First Byte of Opcode from Queue

Empty the Queue

Subsequent Byte from Queue

The following pin function descriptions are for the HS-80C86RH in minimum mode (i.e., MN/MX = VDD). Only the pin functions which are unique

to minimum mode are described; all other pin functions are as described below.

M/IO

28

O

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a memory

access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains valid until

the ﬁnal T4 of the cycle (M = HIGH, IO = LOW). M/IO is held to a high impedance logic zero during local

bus “hold acknowledge”.

WR

29

24

O

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending on the

state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active LOW, and is held

to high impedance logic one during local bus “hold acknowledge”.

INTA

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is active

LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never ﬂoated.

6

HS-80C86RH

Pin Descriptions (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

ALE

25

O

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82 latch. It is

a HIGH pulse active during clock LOW of T1 of any bus cycle. Note that ALE is never ﬂoated.

DT/R

DEN

27

26

O

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus transceiver.

It is used to control the direction of data ﬂow through the transceiver. Logically, DT/R is equivalent to S1

in maximum mode, and its timing is the same as for M/IO (T = HlGH, R = LOW). DT/R is held to a high

impedance logic one during local bus “hold acknowledge”.

DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which uses the

transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or

INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from

the beginning of T2 until the middle of T4. DEN is held to a high impedance logic one during local bus

“hold acknowledge”.

HOLD

HLDA

31

30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be a acknowledged, HOLD must

be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge” (HLDA) in the middle

of a T4 or T1 clock cycle. Simultaneously with the issuance of HLDA, the processor will ﬂoat the local bus

and control lines. After HOLD is detected as being LOW, the processor will lower HLDA, and when the

processor needs to run another cycle, it will again drive the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system cannot

otherwise guarantee the setup time.

AC Test Circuit

AC Testing Input, Output Waveform

INPUT

VIH

VIL - 0.4V

OUTPUT

VOH

OUTPUT FROM

DEVICE UNDER TEST

TEST POINT

1.5V

C

(NOTE)

VOH

L

NOTE: All inputs signals (other than CLK) must switch between VIL

Max -0.4V and VIH Min +0.4. CLK must switch between 0.4V and

VDD -0.4V. TR and TF must be less than or equal to 15ns. CLK TR

and TF must be less than or equal to 10ns.

NOTE: Includes stray and jig capacitance.

Timing Diagrams

F5

READY

4T

READY TIMING AS COMPARED TO F5

F14

F16

PULSE

RESET

NMI

RESET, NMI, AND MN/MX TIMING AS COMPARED TO F14 AND F16

NOTES:

4. F0 = 100kHz, 50% duty cycle square wave.

F1 = F0/2, F2 = F1/2 . . . F16 = F15/2.

5. READY, RESET, and NMI timing are as shown: T = 10µs.

6. All signals have rise/fall time limits: 100ns < t-rise, t-fall < 500ns.

7. RESET has a pulse width = 8T and occurs every two cycles of F16.

8. NMI has a pulse width = 4T and occurs every two cycles of F16.

9. MN/MX is a 50% duty cycle square wave and changes every eight cycles of F16.

7

HS-80C86RH

Irradiation Circuit

VDD

1

2

VSS

VCC 40

R2

LOAD

39

38

37

36

35

34

R2

LOAD

3

R2

LOAD

2.7kΩ

4

5

6

R2

LOAD

R2

7

2.7kΩ

33

8

MN/MX

R3

LOAD

R2

32

9

31

10

11

12

13

14

15

16

17

18

19

HOLD

30

LOAD

HLDA

29

28

27

26

25

24

R2

R3

LOAD

R3

NMI

23

22

21

TEST

READY

RESET

INTR

CLK

R3

CLOCK

20 GND

RESET

NOTES:

10. VDD = 5.0V ±0.5V

11. R2 = 3.3kΩ, R3 = 47kΩ

12. Pins Tied to GND: 1-18, 20, 23, 39

Pins Tied to VCC: 22, 31, 33, 40

Pins With Loads: 24-29, 30, 32, 34-38

Pins Brought Out: 19 (Clock), 21 (Reset)

13. Clock and reset should be brought out separately so they can be toggled before irradiation.

14. Group E Sample Size is 2 Die/Wafer.

8

HS-80C86RH

Burn-In Circuits

HS-80C86RH 40 LEAD DIP

VDD

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

F15

F14

F13

F12

F11

F10

F9

F16

3

LOAD

MN/MX

LOAD

3

4

5

6

7

8

9

F8

9

10

11

12

13

14

15

16

17

18

19

20

F7

10

11

12

13

14

15

16

17

18

19

20

F6

F5

LOAD

F4

F3

F2

F1

NMI

F0

CLK

READY

RESET

VDD

2.7kΩ

LOAD

≥ 5.0µs

T

2.7kΩ

STATIC

DYNAMIC

NOTES:

15. VDD = +6.5V ±10%.

21. VDD = 6.5V ±5% (Burn-In).

o

16. T = 125 C Minimum.

A

22. VDD = 6.0V ±5% (Life Test).

o

17. Part is Static Sensitive.

23. T = 125 C.

A

18. Voltages Must Be Ramped.

19. Package: 40 Lead DIP.

24. Package: 40 Lead DIP.

25. Part is Static Sensitive.

26. Voltage Must Be Ramped.

20. Resistors:

10kΩ ±10%

27. Resistors:

(Pins 17, 18, 21-23, 31, 33)

2.7kΩ ±5% (Pins 2-16, 39)

1.0kΩ ±5% 1/10W Min (Pin 19)

Minimum of 5 CLK Pulses

After Initial Pulses, CLK is Left High

Pulses are 50% Duty Cycle Square Wave

10kΩ (Pins 17, 18, 21, 22, 23, 33)

3.3kΩ (Pins 2-16, 19, 30, 31, 39)

2.7kΩ Loads As Indicated

All Resistors Are At Least 1/8W, ±10%

F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .

RESET, NMI low after initialization.

READY pulsed low every 320ms

MN/MX changes state every 5.24s

9

HS-80C86RH

Burn-In Circuits (Continued)

HS-80C86RH 42 LEAD FLATPACK

VDD

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

F15

F16

F14

F13

F12

F11

F10

F9

3

OPEN

LOAD

3

4

5

6

7

8

F8

9

MN/MX

LOAD

9

F7

10

11

12

13

14

10

11

12

13

14

F6

F5

F4

LOAD

F3

F2

15

16

17

18

19

20

21

15

16

17

18

19

20

21

F1

NMI

F0

OPEN

READY

RESET

CLK

VDD

2.7kΩ

LOAD

2.7kΩ

STATIC

DYNAMIC

NOTES:

28. VDD = +6.5V ±10%.

34. VDD = 6.5V ±5% (Burn-In).

o

29. T = 125 C Minimum.

A

35. VDD = 6.0V ±5% (Life Test).

o

30. Part is Static Sensitive.

36. T = 125 C.

A

31. Voltages Must Be Ramped.

32. Package: 42 Lead Flatpack.

37. Package: 42 Lead Flatpack.

38. Part is Static Sensitive.

39. Voltage Must Be Ramped.

33. Resistors:

10kΩ ±10%

40. Resistors:

(Pins 18, 19, 22-24, 32, 34)

2.7kΩ ±5% (Pins 2-16, 41)

1.0kΩ ±5% 1/10W Min (Pin 20)

Minimum of 5 CLK Pulses

After Initial Pulses, CLK is Left High

Pulses are 50% Duty Cycle Square Wave

10kΩ (Pins 17, 18, 19, 22, 23, 24, 34)

3.3kΩ (Pins 2-16, 20, 31, 32, 41)

2.7kΩ Loads As Indicated

All Resistors Are At Least 1/8W, ±10%

F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .

RESET, NMI low after initialization.

READY pulsed low every 320µs

MN/MX changes state every 5.24s

10

HS-80C86RH

Waveforms

T1

T2

T3

T4

TCL2CL1

TCH1CH2

TW

CLK (HS-82C85RH OUTPUT)

TCLDV

TCLAX

TCLAV

TCLDX2

AD15-AD0

DATA OUT

AD15-AD0

DEN

TWHDX

TCVCTV

TCVCTX

WRITE CYCLE

(NOTE 41)

(RD, INTA,

TCVCTV

TCLAZ

DT/R = VOH)

TWLWH

WR

TCVCTX

TCLDX1

TDVCL

POINTER

AD15-AD0

TCHCTV

DT/R

INTA

INTA CYCLE

(NOTES 41, 43)

(RD, WR = VOH

BHE = VOL)

TCVCTV

TCVCTX

TCVCTV

DEN

SOFTWARE

HALT -

INVALID ADDRESS

SOFTWARE HALT

AD15-AD0

DEN, RD,

WR, INTA = VOH

TCLAV

DT/R = INDETERMINATE

FIGURE 1. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

41. All signals switch between VOH and VOL unless otherwise specified.

42. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

43. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are shown for

the second INTA cycle.

44. Signals at HS-82C85RH are shown for reference only.

45. All timing measurements are made at 1.5V unless otherwise noted.

11

HS-80C86RH

Waveforms (Continued)

T1

T2

T3

TCL2CL1

T4

TCH1CH2

TW

TCLCL

CLK (HS-82C85RH OUTPUT)

TCHCTV

TCLAV

TCHCL

TCHCTV

TCLCH

M/IO

TCLDV

TCLAX

TCLAV

TCLLH

BHE, A19-A16

TLHLL

S7-S3

BHE/S7, A19/S6-A16/S3

TLLAX

ALE

TCHLL

TAVLL

TR1VCL

VIH

VIL

RDY (HS-82C85RH INPUT)

SEE NOTE 49

TCLRIX

TRYLCL

READY (HS-80C86RH INPUT)

TCHRYX

TCLDX1

TRYHCH

TCLAZ

TDVCL

DATA IN

TCLRH

AD15-AD0

TAZRL

AD15-AD0

TRHAV

RD

READ CYCLE

TCHCTV

(NOTE 46)

TCLRL

TCHCTV

TRLRH

(WR, INTA = VOH)

DT/R

DEN

TCVCTX

TCVCTV

FIGURE 2. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

46. All signals switch between VOH and VOL unless otherwise specified.

47. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

48. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are shown for

the second INTA cycle.

49. Signals at HS-82C85RH are shown for reference only.

50. All timing measurements are made at 1.5V unless otherwise noted.

12

HS-80C86RH

Waveforms (Continued)

T1

TCLCL

T2

TCH1CH2

T3

T4

TW

TCL2CL1

CLK

TCLAV

TCHCL

TCLCH

QS0, QS1

TCHSV

TCLSH

S2, S1, S0 (EXCEPT HALT)

(SEE NOTE 58)

TCLAV

TCLDV

TCLAX

TCLAV

BHE/S7, A19/S6-A16/S3

BHE, A19-A16

S7-S3

TSVLH

TCLLH

TCHLL

ALE (82C88 OUTPUT)

NOTE 55

TR1VCL

RDY

(HS-82C85RH INPUT)

TCLR1X

TRYLCL

TCHRYX

TCLDX1

READY (HS-80C86RH INPUT)

TRYHSH

TCLAX

TRYHCH

READ CYCLE

AD15-AD0

TDVCL

DATA IN

TCLRH

TCLAV

TCLAZ

AD15-AD0

TAZRL

TRHAV

RD

TCHDTL

TCHDTH

TRLRH

TCLRL

DT/R

TCLML

TCLMH

82C88

OUTPUTS

SEE NOTES

55, 56

MRDC OR IORC

DEN

TCVNV

TCVNX

FIGURE 3. BUS TIMING - MAXIMUM MODE SYSTEM

NOTES:

51. All signals switch between VOH and VOL unless otherwise specified.

52. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

53. Cascade address is valid between first and second INTA cycle.

54. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer address is

shown for the second INTA cycle.

55. Signals at HS-82C85RH or 82C88 are shown for reference only.

56. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high

82C88 CEN.

57. All timing measurements are made at 1.5V unless otherwise noted.

58. Status inactive in state just prior to T4.

13

HS-80C86RH

Waveforms (Continued)

T1

T2

T3

T4

TW

CLK

TCHSV

(SEE

NOTE 66)

S2, S1, S0 (EXCEPT HALT)

TCLSH

TCLDV

TCLAX

TCLDX2

TCLAV

WRITE CYCLE

AD15-AD0

TCVNV

TCLML

DEN

TCLMH

82C88

OUTPUTS

TCVNX

SEE NOTES

63, 64

AMWC OR AIOWC

TCLMH

TCLML

MWTC OR IOWC

INTA CYCLE

AD15-AD0

(SEE NOTES 61, 62)

RESERVED FOR

CASCADE ADDR

TDVCL

TCLDX1

TCLAZ

AD15-AD0

POINTER

TCLMCL

TSVMCH

MCE/PDEN

TCLMCH

DT/R

TCHDTH

TCHDTL

82C88 OUTPUTS

SEE NOTES 63, 64

TCLML

INTA

DEN

TCLMH

TCVNV

TCVNX

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

INVALID ADDRESS

TCLAV

AD15-AD0

S2

TCLSH

TCHSV

FIGURE 4. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88)

NOTES:

59. All signals switch between VOH and VOL unless otherwise specified.

60. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

61. Cascade address is valid between first and second INTA cycle.

62. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer address is

shown for the second INTA cycle.

63. Signals at HS-82C85RH or 82C88 are shown for reference only.

64. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high

82C88 CEN.

65. All timing measurements are made at 1.5V unless otherwise noted.

66. Status inactive in state just prior to T4.

14

HS-80C86RH

Waveforms (Continued)

CLK

ANY CLK CYCLE

TINVCH (SEE NOTE)

NMI

CLK

INTR

TEST

SIGNAL

TCLAV

LOCK

NOTE: Setup Requirements for asynchronous signals only to

guarantee recognition at next CLK.

FIGURE 5. ASYNCHRONOUS SIGNAL RECOGNITION

FIGURE 6. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

TCLGL

TCLGH

ANY

CLK

CYCLE

≥ 0-CLK

CYCLES

CLK

TCLGH

TGVCH

TCHGX

TCLCL

PULSE 2

HS-80C86RH

RQ/GT

PREVIOUS GRANT

GT

PULSE 3

COPROCESSOR

RELEASE

PULSE 1

COPROCESSOR

TCLAZ

RQ

AD15-AD0

HS-80C86RH

(SEE NOTE) TCHSV

TCHSZ

RD, LOCK

BHE/S7, A19/S6-A16/S3

S2, S1, S0

NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.

FIGURE 7. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

≥ 1CLK

CYCLE

1 OR 2

CYCLES

CLK

THVCH

HOLD

HLDA

TCLHAV

TCLAZ

COPROCESSOR

TCHSZ

80C86

AD15-AD0

BHE/S7, A19/S6-A16/S3

RD, WR, M/IO, DT/R, DEN

FIGURE 8. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

15

HS-80C86RH

Memory Organization

Functional Description

The processor provides a 20-bit address to memory, which

locates the byte being referenced. The memory is

organized as a linear array of up to 1 million bytes,

addressed as 00000(H) to FFFFF(H). The memory is

logically divided into code, data, extra and stack segments

of up to 64K bytes each, with each segment falling on 16

byte boundaries. (See Figure 9).

Static Operation

All HS-80C86RH circuitry is of static design. Internal

registers, counters and latches are static and require no

refresh as with dynamic circuit design. This eliminates the

minimum operating frequency restriction placed on other

microprocessors. The CMOS HS-80C86RH can operate

from DC to 5MHz. The processor clock may be stopped in

either state (HIGH/LOW) and held there indeﬁnitely. This

type of operation is especially useful for system debug or

power critical applications.

FFFFFH

64K BIT

CODE SEGMENT

XXXXOH

The HS-80C86RH can be single stepped using only the CPU

clock. This state can be maintained as long as is necessary.

Single step clock operation allows simple interface circuitry to

provide critical information for bringing up your system.

STACK SEGMENT

DATA SEGMENT

Static design also allows very low frequency operation

(down to DC). In a power critical situation, this can provide

extremely low power operation since HS-80C86RH power

dissipation is directly related to operating frequency. As the

system frequency is reduced, so is the operating power until,

ultimately, at a DC input frequency, the HS-80C86RH power

requirement is the standby current, (500µA maximum).

+ OFFSET

SEGMENT

REGISTER FILE

CS

SS

DS

ES

Internal Architecture

EXTRA SEGMENT

00000H

The internal functions of the HS-80C86RH processor are

partitioned logically into two processing units. The ﬁrst is the

Bus Interface Unit (BIU) and the second is the Execution

Unit (EU) as shown in the CPU functional diagram.

FIGURE 9. HS-80C86RH MEMORY ORGANIZATION

These units can interact directly but for the most part

perform as separate asynchronous operational processors.

The bus interface unit provides the functions related to

instruction fetching and queuing, operand fetch and store,

and address relocation. This unit also provides the basic bus

control. The overlap of instruction pre-fetching provided by

this unit serves to increase processor performance through

improved bus bandwidth utilization. Up to 6 bytes of the

instruction stream can be queued while waiting for decoding

and execution.

TABLE 1.

DEFAULT

TYPE OF MEMORY SEGMENT

ALTERNATE

SEGMENT

BASE

REFERENCE

Instruction Fetch

Stack Operation

BASE

OFFSET

IP

CS

None

SS

SP

Variable

(Except Following)

DS

CS, ES, SS

Effective

Address

The instruction stream queuing mechanism allows the BlU to

keep the memory utilized very efﬁciently. Whenever there is

space for at least 2 bytes in the queue, the BlU will attempt a

word fetch memory cycle. This greatly reduces “dead-time”

on the memory bus. The queue acts as a First-In-First-Out

(FlFO) buffer, from which the EU extracts instruction bytes

as required. If the queue is empty (following a branch

instruction, for example), the ﬁrst byte into the queue

immediately becomes available to the EU.

String Source

DS

ES

SS

CS, ES, SS

None

SI

DI

String Destination

BP Used as Base

Register

CS, DS, ES

Effective

Address

All memory references are made relative to base addresses

contained in high speed segment registers. The segment

types were chosen based on the addressing needs of

programs. The segment register to be selected is

automatically chosen according to the speciﬁc rules of

Table 1. All information in one segment type share the same

logical attributes (e.g., code or data). By structuring memory

The execution unit receives pre-fetched instructions from the

BlU queue and provides un-relocated operand addresses to

the BlU. Memory operands are passed through the BlU for

processing by the EU, which passes results to the BlU for

storage.

16

HS-80C86RH

into relocatable areas of similar characteristics and by

automatically selecting segment registers, programs are

shorter, faster and more structured. (See Table 1).

FFFFFH

FFFFOH

RESET BOOTSTRAP

PROGRAM JUMP

Word (16-bit) operands can be located on even or odd

3FFH

address boundaries and are thus not constrained to even

boundaries as is the case in many 16-bit computers. For

address and data operands, the least signiﬁcant byte of the

word is stored in the lower valued address location and the

most signiﬁcant byte in the next higher address location. The

BlU automatically performs the proper number of memory

accesses, one if the word operand is on an even byte

boundary and two if it is on an odd byte boundary. Except for

the performance penalty, this double access is transparent to

the software. The performance penalty does not occur for

instruction fetches; only word operands.

INTERRUPT POINTER

FOR TYPE 255

3FCH

7H

INTERRUPT POINTER

FOR TYPE 1

4H

3H

INTERRUPT POINTER

FOR TYPE 0

0H

FIGURE 10. RESERVED MEMORY LOCATIONS

Minimum and Maximum Operation Modes

Physically, the memory is organized as a high bank (D15-

D6) and a low bank (D7-D0) of 512K bytes addressed in

parallel by the processor’s address lines.

The requirements for supporting minimum and maximum

HS-80C86RH systems are sufﬁciently different that they

cannot be met efﬁciently using 40 uniquely deﬁned pins.

Consequently, the HS-80C86RH is equipped with a strap pin

(MN/MX) which deﬁnes the system conﬁguration. The

deﬁnition of a certain subset of the pins changes, dependent

on the condition of the strap pin. When the MN/MX pin is

strapped to GND, the HS-80C86RH deﬁnes pins 24 through

31 and 34 in maximum mode. When the MN/MX pin is

strapped to VDD, the HS-80C86RH generates bus control

signals itself on pins 24 through 31 and 34.

Byte data with even addresses is transferred on the D7-D0

bus lines while odd addressed byte data (A0 HIGH) is

transferred on the D15-D6 bus lines. The processor provides

two enable signals, BHE and A0, to selectively allow reading

from or writing into either an odd byte location, even byte

location, or both. The instruction stream is fetched from

memory as words and is addressed internally by the

processor at the byte level as necessary.

Bus Operation

In referencing word data, the BlU requires one or two

memory cycles depending on whether the starting byte of

the word is on an even or odd address, respectively.

Consequently, in referencing word operands performance

can be optimized by locating data on even address

boundaries. This is an especially useful technique for using

the stack, since odd address references to the stack may

adversely affect the context switching time for interrupt

processing or task multiplexing.

The HS-80C86RH has a combined address and data bus

commonly referred to as a time multiplexed bus. This

technique provides the most efficient use of pins on the

processor while permitting the use of a standard 40-lead

package. This “local bus” can be buffered directly and used

throughout the system with address latching provided on

memory and I/O modules. In addition, the bus can also be

demultiplexed at the processor with a single set of 82C82

latches if a standard non-multiplexed bus is desired for

the system.

Certain locations in memory are reserved for speciﬁc CPU

operations (See Figure 10). Locations from address FFFF0H

through FFFFFH are reserved for operations including a

jump to the initial program loading routine. Following RESET,

the CPU will always begin execution at location FFFF0H

where the jump must be located. Locations 00000H through

003FFH are reserved for interrupt operations. Each of the

256 possible interrupt service routines is accessed through

its own pair of 16-bit pointers - segment address pointer and

offset address pointer. The ﬁrst pointer, used as the offset

address, is loaded into the 1P and the second pointer, which

designates the base address is loaded into the CS. At this

point program control is transferred to the interrupt routine.

The pointer elements are assumed to have been stored at

the respective places in reserved memory prior to

Each processor bus cycle consists of at least four CLK

cycles. These are referred to as T1, T2, T3 and T4 (see

Figure 11). The address is emitted from the processor

during T1 and data transfer occurs on the bus during T3 and

T4. T2 is used primarily for changing the direction of the bus

during read operations. In the event that a “NOT READY”

indication is given by the addressed device, “Wait” states

(TW) are inserted between T3 and T4. Each inserted wait

state is the same duration as a CLK cycle. Idle periods occur

between HS-80C86RH driven bus cycles whenever the

processor performs internal processing.

During T1 of any bus cycle, the ALE (Address Latch Enable)

signal is emitted (by either the processor or the 82C88 bus

controller, depending on the MN/MX strap). At the trailing

edge of this pulse, a valid address and certain status

information for the cycle may be latched.

occurrence of interrupts.

17

HS-80C86RH

Status bits S0, S1 and S2 are used by the bus controller, in

maximum mode, to identify the type of bus transaction

according to Table 2.

TABLE 3.

CHARACTERISTICS

S4

0 (Low)

0

S3

0

Alternate Data (extra segment)

TABLE 2.

1

Stack

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt Acknowledge

1 (High)

1

0

Code or None

Data

1

0

1

Read I/O Port

S5 is a reﬂection of the PSW interrupt enable bit. S6 is

always zero and S7 is a spare status bit.

0

1

0

Write I/O Port

I/O Addressing

0

1

Halt

In the HS-80C86RH, I/O operations can address up to a

maximum of 64K I/O byte registers or 32K I/O word

registers. The I/O address appears in the same format as

the memory address on bus lines A15-A0. The address lines

A19-A16 are zero in I/O operations. The variable I/O

instructions which use register DX as a pointer have full

address capability while the direct I/O instructions directly

address one or two of the 256 I/O byte locations in page 0 of

the I/O address space.

1

0

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

1

0

1

0

1

Status bits S3 through S7 are time multiplexed with high order

address bits and the BHE signal, and are therefore valid

during T2 through T4. S3 and S4 indicate which segment

register (see Instruction Set Description) was used for this bus

cycle in forming the address, according to Table 3.

I/O ports are addressed in the same manner as memory

locations. Even addressed bytes are transferred on the

D7-D0 bus lines and odd addressed bytes on D15-D8. Care

must be taken to ensure that each register within an 8-bit

peripheral located on the lower portion of the bus be

addressed as even.

18

HS-80C86RH

(4 + NWAIT) = TCY

T3 TWAIT

T1

T2

T3

TWAIT

T4

T1

T2

T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

ALE

S2-S0

BHE,

A19-A16

ADDR/

STATUS

S7-S3

D15-D0

VALID

A15-A0

DATA OUT (D15-D0)

ADDR/DATA

RD, INTA

READY

WAIT

DT/R

DEN

WP

MEMORY ACCESS TIME

FIGURE 11. BASIC SYSTEM TIMING

HIGH-to-LOW transition of RESET must occur no sooner

than 50µs (or 4 CLK cycles, whichever is greater) after

power-up, to allow complete initialization of the

HS-80C86RH.

External Interface

Processor RESET and lnitialization

Processor initialization or start up is accomplished with

activation (HIGH) of the RESET pin. The HS-80C86RH

RESET is required to be HIGH for greater than 4 CLK

cycles. The HS-80C86RH will terminate operations on the

high-going edge of RESET and will remain dormant as long

as RESET is HIGH. The low-going transition of RESET

triggers an internal reset sequence for approximately 7 CLK

cycles. After this interval, the HS-80C86RH operates

normally beginning with the instruction in absolute location

FFFFOH. (See Figure 10). The RESET input is internally

synchronized to the processor clock. At initialization, the

NMl will not be recognized prior to the second clock cycle

following the end of RESET. If NMI is asserted sooner than

9 CLK cycles after the end of RESET, the processor may

execute one instruction before responding to the interrupt.

Bus Hold Circuitry

To avoid high current conditions caused by ﬂoating inputs to

CMOS devices and to eliminate need for pull- up/down

resistors, “bus-hold” circuitry has been used on the

HS-80C86RH pins 2-16, 26-32 and 34-39. (See Figures 12A

19

HS-80C86RH

and 12B). These circuits will maintain the last valid logic

Non-Maskable Interrupt (NMI)

state if no driving source is present (i.e., an unconnected pin

or a driving source which goes to a high impedance state).

To overdrive the “bus hold” circuits, an external driver must

be capable of supplying approximately 400µA minimum sink

or source current at valid input voltage levels. Since this “bus

hold” circuitry is active and not a “resistive” type element, the

associated power supply current is negligible and power

dissipation is signiﬁcantly reduced when compared to the

use of passive pull-up resistors.

The processor provides a single non-maskable interrupt pin

(NMl) which has higher priority than the maskable interrupt

request pin (INTR). A typical use would be to activate a

power failure routine. The NMl is edge-triggered on a LOW-

to-HIGH transition. The activation of this pin causes a type 2

interrupt.

NMl is required to have a duration in the HIGH state of

greater than 2 CLK cycles, but is not required to be

synchronized to the clock. Any positive transition of NMl is

latched on-chip and will be serviced at the end of the current

instruction or between whole moves of a block-type

instruction. Worst case response to NMl would be for

multiply, divide, and variable shift instructions. There is no

speciﬁcation on the occurrence of the low-going edge; it may

occur before, during or after the servicing of NMl. Another

positive edge triggers another response if it occurs after the

start of the NMl procedure. The signal must be free of logical

spikes in general and be free of bounces on the low-going

edge to avoid triggering extraneous responses.

EXTERNAL

BOND

PAD

OUTPUT

DRIVER

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 12A. BUS HOLD CIRCUITRY PIN 2-16, 34-39

Maskable Interrupt (INTR)

The HS-80C86RH provides a single interrupt request input

(INTR) which can be masked internally by software with the

resetting of the interrupt enable ﬂag (IF) status bit. The

interrupt request signal is level triggered. It is internally

synchronized during each clock cycle on the high-going

edge of CLK. To be responded to, INTR must be present

(HIGH) during the clock period preceding the end of the

current instruction or the end of a whole move for a block-

type instruction. INTR may be removed anytime after the

falling edge of the ﬁrst INTA signal. During the interrupt

response sequence further interrupts are disabled. The

enable bit is reset as part of the response to any interrupt

(INTR, NMl, software interrupt or single-step), although the

FLAGS register which is automatically pushed onto the stack

reﬂects the state of the processor prior to the interrupt. Until

the old FLAGS register is restored the enable bit will be zero

unless speciﬁcally set by an instruction.

EXTERNAL

BOND

PAD

VCC

P

OUTPUT

DRIVER

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 12B. BUS HOLD CIRCUITRY PIN 26-32

Interrupt Operations

Interrupt operations fall into two classes: software or

hardware initiated. The software initiated interrupts and

software aspects of hardware interrupts are speciﬁed in the

Instruction Set Description. Hardware interrupts can be

classiﬁed as non-maskable or maskable.

Interrupts result in a transfer of control to a new program

location. A 256-element table containing address pointers to

the interrupt service routine locations resides in absolute

locations 0 through 3FFH, which are reserved for this

purpose. Each element in the table is 4 bytes in size and

corresponds to an interrupt “type”. An interrupting device

supplies an 8-bit type number during the interrupt

acknowledge sequence, which is used to “vector” through

the appropriate element to the interrupt service routine

location. All ﬂags and both the Code Segment and

Instruction Pointer register are saved as part of the INTA

sequence. These are restored upon execution of an Interrupt

Return (lRET) instruction.

During the response sequence (Figure 13) the processor

executes two successive (back-to-back) interrupt

acknowledge cycles. The HS-80C86RH emits the LOCK

signal (Max mode only) from T2 of the ﬁrst bus cycle until T2

of the second. A local bus “hold” request will not be honored

until the end of the second bus cycle. In the second bus

cycle, a byte is supplied to the HS-80C86RH by the

HS-82C89ARH Interrupt Controller, which identiﬁes the

source (type) of the interrupt. This byte is multiplied by four

and used as a pointer into the interrupt vector lookup table.

An INTR signal left HIGH will be continually responded to

within the limitations of the enable bit and sample period.

The INTERRUPT RETURN instruction includes a FLAGS

pop which returns the status of the original interrupt enable

bit when it restores the FLAGS.

20

HS-80C86RH

If a local bus request occurs during WAIT execution, the

T1

T3

T1

T2

T3

T4 TI

T2

T4

HS-80C86RH three-states all output drivers while inputs and

I/O pins are held at valid logic levels by internal bus-hold

circuits. If interrupts are enabled, the HS-80C86RH will

recognize interrupts and process them when it regains control

of the bus. The WAIT instruction is then refetched, and

reexecuted.

ALE

LOCK

INTA

Basic System Timing

Typical system conﬁgurations for the processor operating in

minimum mode and in maximum mode are shown in Figures

14A and 14B, respectively. In minimum mode, the MN/MX

pin is strapped to VDD and the processor emits bus control

signals (e.g. RD, WR, etc.) directly. In maximum mode, the

MN/MX pin is strapped to GND and the processor emits

coded status information which the 82C88 bus controller

used to generate Multibus™ compatible bus control signals.

Figure 11 shows the signal timing relationships.

FLOAT

AD0-

AD15

TYPE

VECTOR

FIGURE 13. INTERRUPT ACKNOWLEDGE SEQUENCE

Halt

When a software “HALT” instruction is executed the

processor indicates that it is entering the “HALT” state in one

of two ways depending upon which mode is strapped. In

minimum mode, the processor issues one ALE with no

qualifying bus control signals. In maximum mode the

processor issues appropriate HALT status on S2, S1, S0

and the 82C88 bus controller issues one ALE. The

HS-80C86RH will not leave the “HALT” state when a local

bus “hold” is entered while in “HALT”. In this case, the

processor reissues the HALT indicator at the end of the local

bus hold. An NMl or interrupt request (when interrupts

enabled) or RESET will force the HS-80C86RH out of the

“HALT” state.

TABLE 4. HS-80C86RH REGISTER MODEL

AX

BX

CX

DX

AH

BH

CH

DH

AL

BL

CL

DL

ACCUMULATOR

BASE

COUNT

DATA

SP

BP

SI

STACK POINTER

BASE POINTER

SOURCE INDEX

DESTINATION INDEX

Read/Modify/Write (Semaphore)

DI

Operations Via Lock

IP

INSTRUCTION POINTER

STATUS FLAGS

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the

execution of an instruction. This gives the processor the

capability of performing read/modify/write operations on

memory (via the Exchange Register With Memory

instruction, for example) without another system bus master

receiving intervening memory cycles. This is useful in

multiprocessor system conﬁgurations to accomplish “test

and set lock” operations. The LOCK signal is activated

(forced LOW) in the clock cycle following decoding of the

software “LOCK” preﬁx instruction. It is deactivated at the

end of the last bus cycle of the instruction following the

“LOCK” preﬁx instruction. While LOCK is active a request on

a RQ/GT pin will be recorded and then honored at the end of

the LOCK.

FLAGSH

FLAGSL

CS

DS

SS

ES

CODE SEGMENT

DATA SEGMENT

STACK SEGMENT

EXTRA SEGMENT

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the

Address Latch Enable (ALE) signal. The trailing (low-going)

edge of this signal is used to latch the address information,

which is valid on the address/data bus (AD0-AD15) at this

time, into the 82C82 latches. The BHE and A0 signals

address the low, high or both bytes. From T1 to T4 the M/IO

signal indicates a memory or I/O operation. At T2, the

address is removed from the address/data bus and the bus

is held at the last valid logic state by internal bus hold

devices. The read control signal is also asserted at T2. The

read (RD) signal causes the addressed device to enable its

data bus drivers to the local bus. Some time later, valid data

will be available on the bus and the addressed device will

drive the READY line HIGH. When the processor returns the

read signal to a HIGH level, the addressed device will three-

External Synchronization Via TEST

As an alternative to interrupts, the HS-80C86RH provides a

single software-testable input pin (TEST). This input is

utilized by executing a WAIT instruction. The single WAIT

instruction is repeatedly executed until the TEST input goes

active (LOW). The execution of WAIT does not consume bus

cycles once the queue is full.

Multibus™ is a trademark of Intel Corporation.

21

HS-80C86RH

state its bus drivers. If a transceiver is required to buffer the

Bus Timing - Medium and Large Size Systems

HS-80C86RH local bus, signals DT/R and DEN are provided

by the HS-80C86RH.

For medium complexity systems the MN/MX pin is

connected to GND and the 82C88 Bus Controller is added to

the system as well as three 82C82 latches for latching the

system address, and a transceiver to allow for bus loading

greater than the HS-80C86RH is capable of handling. Bus

control signals are generated by the 82C88 instead of the

processor in this conﬁguration, although their timing remains

relatively the same. The HS-80C86RH status outputs (S2,

S1, and S0) provide type-of-cycle information and become

82C88 inputs. This bus cycle information speciﬁes read

(code, data or I/O), write (data or I/O), interrupt

acknowledge, or software halt. The 82C88 issues control

signals specifying memory read or write, I/O read or write, or

interrupt acknowledge. The 82C88 provides two types of

write strobes, normal and advanced, to be applied as

required. The normal write strobes have data valid at the

leading edge of write. The advanced write strobes have the

same timing as read strobes, and hence, data is not valid at

the leading edge of write. The transceiver receives the usual

T and 0E inputs from the 82C88 DT/R and DEN signals.

A write cycle also begins with the assertion of ALE and the

emission of the address. The M/IO signal is again asserted

to indicate a memory or I/O write operation. In T2,

immediately following the address emission, the processor

emits the data to be written into the addressed location. This

data remains valid until at least the middle of T4. During T2,

T3 and TW, the processor asserts the write control signal.

The write (WR) signal becomes active at the beginning of T2

as opposed to the read which is delayed somewhat into T2

to provide time for output drivers to become inactive.

The BHE and A0 signals are used to select the proper

byte(s) of the memory/IO word to be read or written

according to Table 5.

TABLE 5.

BHE

A0

0

CHARACTERISTICS

0

1

Whole word

For large multiple processor systems, the 82C89 bus arbiter

must be added to the system to provide system bus

management. In this case, the pointer into the interrupt

vector table, which is passed during the second INTA cycle,

can be derived from an HS-82C59ARH located on either the

local bus or the system bus. The processor’s INTA output

should drive the SYSB/RESB input of the 82C89 to the

proper state when reading the interrupt vector number from

the HS-82C59ARH during the interrupt acknowledge

sequence and software “poll”.

1

Upper byte from/to odd address

Lower byte from/to even address

None

0

1

I/O ports are addressed in the same manner as memory

location. Even addressed bytes are transferred on the D7-D0

bus lines and odd address bytes on D15-D6.

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge

signal (INTA) is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal

bus hold devices. (See Figures 12A, 12B). In the second of

two successive INTA cycles a byte of information is read

from the data bus (D7-D0) as supplied by the interrupt

system logic (i.e., HS-82CS9ARH Priority Interrupt

A Note on Radiation Hardened Product Availability

There are no immediate plans to develop the 82C88 Bus

Controller or the 82C89 Arbiter as radiation hardened

integrated circuits.

A Note on SEU Capability of the HS-80C86RH

Previous heavy ion testing of the HS-80C86RH has

indicated that the SEU threshold of this part is about

Controller). This byte identiﬁes the source (type) of the

interrupt. It is multiplied by four and used as a pointer into an

interrupt vector Iookup table, as described earlier.

2

6MEV/mg/cm . Based upon these results and other

analysis, a deep space galactic cosmic-ray environment will

result in an SEU rate of about 0.08 upsets/day.

22

HS-80C86RH

VDD

CLK

GND

MRDC

MN/MX

S0

HS-82C85RH

CLOCK

CONTROLLER/

GENERATOR

RDY

CLK

MWTC

S0

82C88

BUS

CTRLR

NC

AMWC

READY

RESET

S1

S2

S1

S2

RES

IORC

IOWC

AIOWC

INTA

DEN

DT/R

ALE

HS-80C86RH

CPU

WAIT

STATE

GENERATOR

NC

LOCK

GND

VDD

STB

OE

GND

ADDR/DATA

GND

1

AD0-AD15

A16-A19

ADDR

82C82

(2 OR 3)

C1

C2

BHE

GND

20

T/R

OE

HS-82C08RH

TRANSCEIVER

(2)

VDD

40

DATA

C1 = C2 = 0.1µF

A0

BHE

E

G

CS

RDWR

W

E

HS-6617RH

CMOS PROM (2)

2K x 8 2K x 8

CMOS

HS-82CXXRH

HS-65262RH

CMOS RAM (16)

16K x 1

PERIPHERALS

FIGURE 14A. MAXIMUM MODE HS-80C86RH TYPICAL CONFIGURATION

VDD

MN/MX

M/IO

HS-82C85RH

CLK

CLOCK

CONTROLLER/

GENERATOR

RDY

READY INTA

RES

RD

RESET

WR

DT/R

DEN

WAIT

STATE

GENERATOR

HS-80C86RH

CPU

GND

VDD

ALE

STB

OE

GND

ADDR/DATA

GND

1

AD0-AD15

A16-A19

ADDR

82C82

(2 OR 3)

C1

C2

BHE

GND

20

T/R

OE

HS-82C08RH

TRANSCEIVER

(2)

VDD

40

DATA

A0

C1 = C2 = 0.1µF

BHE

E

G

CS

RDWR

OPTIONAL

FOR INCREASED

DATA BUS DRIVE

W

E

HS-6617RH

CMOS PROM (2)

2K x 8 2K x 8

CMOS

HS-82CXXRH

PERIPHERALS

HS-65262RH

CMOS RAM (16)

16K x 1

FIGURE 14B. MINIMUM MODE HS-80C86RH TYPICAL CONFIGURATION

23

HS-80C86RH

Instruction Set Summary

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

DATA TRANSFER

7 6 5 4 3 2 1 0

MOV = MOVE:

Register/Memory to/from Register

Immediate to Register/Memory

Immediate to Register

Memory to Accumulator

Accumulator to Memory

Register/Memory to Segment Register ††

Segment Register to Register/Memory

PUSH = Push:

1 0 0 0 1 0 d w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

mod reg r/m

mod 0 0 0 r/m

data

data if w 1

addr-high

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

addr-low

mod 0 reg r/m

Register/Memory

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

mod 1 1 0 r/m

mod 0 0 0 r/m

Register

Segment Register

POP = Pop:

Register/Memory

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

Register

Segment Register

XCHG = Exchange:

Register/Memory with Register

Register with Accumulator

IN = Input from:

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

Fixed Port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

port

Variable Port

OUT = Output to:

Fixed Port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

port

Variable Port

XLAT = Translate Byte to AL

LEA = Load EA to Register 2

LDS = Load Pointer to DS

LES = Load Pointer to ES

LAHF = Load AH with Flags

SAHF = Store AH into Flags

PUSHF = Push Flags

POPF = Pop Flags

mod reg r/m

24

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

ARITHMETIC

7 6 5 4 3 2 1 0

data if s:w = 01

ADD = Add:

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

ADC = Add with Carry:

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

INC = Increment:

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

mod reg r/m

mod 0 1 0 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

Register

AAA = ASCll Adjust for Add

DAA = Decimal Adjust for Add

SUB = Subtract:

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

SBB = Subtract with Borrow:

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

DEC = Decrement:

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if s:w = 01

data if w = 1

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

mod 0 1 1 r/m

Register

NEG = Change Sign

1 1 1 1 0 1 1 w

CMP = Compare:

Register/Memory and Register

Immediate with Register/Memory

Immediate with Accumulator

AAS = ASCll Adjust for Subtract

DAS = Decimal Adjust for Subtract

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

AAM = ASCll Adjust for Multiply

DlV = Divide (Unsigned)

0 0 1 1 1 0 d w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 0

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

mod reg r/m

mod 1 1 1 r/m

data

data if s:w = 01

data if w = 1

mod 1 0 0 r/m

mod 1 0 1 r/m

0 0 0 0 1 0 1 0

mod 1 1 0 r/m

mod 1 1 1 r/m

0 0 0 0 1 0 1 0

IDlV = Integer Divide (Signed)

AAD = ASClI Adjust for Divide

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

25

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

LOGIC

7 6 5 4 3 2 1 0

NOT = Invert

1 1 1 1 0 1 1 w

1 1 0 1 0 0 v w

mod 0 1 0 r/m

mod 1 0 0 r/m

mod 1 0 1 r/m

mod 1 1 1 r/m

mod 0 0 0 r/m

mod 0 0 1 r/m

mod 0 1 0 r/m

mod 0 1 1 r/m

SHL/SAL = Shift Logical/Arithmetic Left

SHR = Shift Logical Right

SAR = Shift Arithmetic Right

ROL = Rotate Left

ROR = Rotate Right

RCL = Rotate Through Carry Flag Left

RCR = Rotate Through Carry Right

AND = And:

Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

TEST = And Function to Flags, No Result:

Register/Memory and Register

Immediate Data and Register/Memory

Immediate Data and Accumulator

OR = Or:

0 0 1 0 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

data if w = 1

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

XOR = Exclusive or:

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

STRING MANIPULATION

REP = Repeat

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

mod reg r/m

mod 1 1 0 r/m

data

data if w = 1

1 1 1 1 0 0 1 z

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

MOVS = Move Byte/Word

CMPS = Compare Byte/Word

SCAS = Scan Byte/Word

LODS = Load Byte/Word to AL/AX

STOS = Store Byte/Word from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

disp-low

mod 0 1 0 r/m

offset-low

disp-high

Indirect Within Segment

Direct Intersegment

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

26

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

JMP = Unconditional Jump:

Direct Within Segment

7 6 5 4 3 2 1 0

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

disp-low

disp

disp-high

Direct Within Segment-Short

Indirect Within Segment

mod 1 0 0 r/m

offset-low

seg-low

Direct Intersegment

offset-high

seg-high

Direct Intersegment

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

RET = Return from CALL:

Within Segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

1 1 1 0 0 0 1 1

Within Seg Adding lmmed to SP

Intersegment

data-low

data-high

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

data-low

disp

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/ Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overflow

JS = Jump on Sign

JNE/JNZ = Jump on Not Equal/Not Zero

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above or Equal

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overﬂow

JNS = Jump on Not Sign

LOOP = Loop CX Times

LOOPZ/LOOPE = Loop While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

type

Type 3

INTO = Interrupt on Overﬂow

IRET = Interrupt Return

27

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

PROCESSOR CONTROL

CLC = Clear Carry

7 6 5 4 3 2 1 0

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 0 1 1 x x x

1 1 1 1 0 0 0 0

CMC = Complement Carry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

ST = Set Interrupt

HLT = Halt

WAIT = Wait

ESC = Escape (to External Device)

LOCK = Bus Lock Prefix

NOTES:

mod x x x r/m

if s:w = 01 then 16 bits of immediate data form the operand.

if s:w. = 11 then an immediate data byte is sign extended

to form the 16-bit operand.

if v = 0 then “count” = 1; if v = 1 then “count” in (CL)

x = don't care

AL = 8-bit accumulator

AX = 16-bit accumulator

CX = Count register

DS= Data segment

z is used for string primitives for comparison with ZF FLAG.

ES = Extra segment

Above/below refers to unsigned value.

Greater = more positive;

SEGMENT OVERRIDE PREFIX

001 reg 11 0

Less = less positive (more negative) signed values

if d = 1 then “to” reg; if d = 0 then “from” reg

if w = 1 then word instruction; if w = 0 then byte instruction

if mod = 11 then r/m is treated as a REG ﬁeld

if mod = 00 then DISP = O†, disp-low and disp-high are absent

if mod = 01 then DISP = disp-low sign-extended 16-bits, disp-high is absent

if mod = 10 then DISP = disp-high:disp-low

if r/m = 000 then EA = (BX) + (SI) + DISP

if r/m = 001 then EA = (BX) + (DI) + DISP

if r/m = 010 then EA = (BP) + (SI) + DISP

if r/m = 011 then EA = (BP) + (DI) + DISP

if r/m = 100 then EA = (SI) + DISP

REG is assigned according to the following table:

16-BIT (w = 1)

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

8-BIT (w = 0)

000 AL

SEGMENT

00 ES

01 CS

10 SS

11 DS

00 ES

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

if r/m = 101 then EA = (DI) + DISP

if r/m = 110 then EA = (BP) + DISP †

if r/m = 111 then EA = (BX) + DISP

DISP follows 2nd byte of instruction (before data if required)

111 DI

†

except if mod = 00 and r/m = 110 then EA = disp-high: disp-low.

Instructions which reference the flag register file as a 16-bit object

use the symbol FLAGS to represent the file:

†† MOV CS, REG/MEMORY not allowed.

FLAGS =

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

Mnemonics ” Intel, 1978

28

HS-80C86RH

Die Characteristics

DIE DIMENSIONS:

Top Metallization:

6370µm x 7420µm x 485µm

Type: Al/Si

Thickness: 11kÅ ±2kÅ

INTERFACE MATERIALS:

ADDITIONAL INFORMATION:

Glassivation:

Worst Case Current Density:

Thickness: 8kÅ ±1kÅ

5

2

<2 x 10 A/cm

HS-80C86RH

Metallization Mask Layout

(36) A18/S5

(35) A19/S6

AD10 (6)

AD9 (7)

(34) BHE/S7

(33) MN/MX

AD8 (8)

AD7 (9)

(32) RD

(31) RQ/GT0

AD6 (10)

AD5 (11)

(30) RQ/GT1

AD4 (12)

AD3 (13)

(29) LOCK

(28) S2

AD2 (14)

AD1 (15)

(27) S1

(26) S0

AD0 (16)

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

29


型号：	HS-80C86RH_00
厂家：	Intersil
描述：	Radiation Hardened 16-Bit CMOS Microprocessor 抗辐射16位CMOS微处理器微处理器
文件：	总29页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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