HS0-303BRH-Q [INTERSIL]
Radiation Hardened CMOS Dual SPDT Analog Switch; 抗辐射CMOS双路SPDT模拟开关
| 型号： | HS0-303BRH-Q |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened CMOS Dual SPDT Analog Switch |
| 文件： | 总3页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-303ARH, HS-303BRH
®
Data Sheet
July 7, 2008
FN6411.1
Radiation Hardened
Features
CMOS Dual SPDT Analog Switch
• QML, Per MIL-PRF-38535
The HS-303ARH and HS-303BRH analog switches are
monolithic devices fabricated using Intersil’s dielectrically
isolated Radiation Hardened Silicon Gate (RSG) process
technology to insure latch-up free operation. They are pinout
compatible and functionally equivalent to the HS-303RH, but
offer improved 300kRAD(Si) total dose capability. These
switches offers low-resistance switching performance for
analog voltages up to the supply rails. “ON” resistance is low
and stays reasonably constant over the full range of
operating voltage and current. “ON” resistance also stays
reasonably constant when exposed to radiation.
• Radiation Performance
5
- Total Dose: 3x10 RAD(Si)
2
- SEE: For LET = 60MeV-mg/cm at 60° Incident Angle,
<150pC Charge Transferred to the Output of an Off
Switch
• No Latch-Up, Dielectrically Isolated Device Islands
• Pinout and Functionally Compatible with Intersil
HS-303RH and HI-303 Series Analog Switches
• Analog Signal Range Equal to the Supply Voltage Range
• Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad)
Break-before-make switching is controlled by 5V digital
inputs. The HS-303ARH should be operated with nominal
±15V supplies, while the HS-303BRH should be operated
with nominal ±12V supplies.
• Low r
ON
. . . . . . . . . . . . . . . . . . . . . . 70Ω (Max, Post-Rad)
• Low Standby Supply Current . . . . . . . . . . +150µA/-100µA
(Max, Post-Rad)
Specifications
Pinouts
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
HS1-303ARH, HS-303BRH (SBDIP), CDIP2-T14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
S4
D4
D2
S2
IN2
V-
NC
S3
Detailed Electrical Specifications for the HS-303ARH and
HS-303BRH are contained in SMD 5962-95813. A “hot-link”
is provided from our website for downloading
D3
D1
S1
IN1
GND
8
HS9-303ARH, HS-303BRH (FLATPACK) CDFP3-F14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
S4
D4
D2
S2
IN2
V-
NC
S3
D3
D1
S1
IN1
GND
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303BRH
Ordering Information
TEMP. RANGE
PKG.
ORDERING NUMBER
5962F9581304QCC
5962F9581304QXC
5962F9581304V9A
5962F9581304VCC
5962F9581304VXC
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
5962F9581305QCC
5962F9581305QXC
5962F9581305V9A
5962F9581305VCC
5962F9581305VXC
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
PART NUMBER
(°C)
PKG.
14 LD SBDIP
DWG. #
HS1-303ARH-8
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
D14.3
HS9-303ARH-8
14 LD Flatpack
14 Ld SBDIP
14 LD SBDIP
14 LD Flatpack
K14.A
D14.3
D14.3
K14.A
HS0-303ARH-Q
HS1-303ARH-Q
HS9-303ARH-Q
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
HS1-303BRH-8
14 LD SBDIP
14 LD Flatpack
14 LD SBDIP
14 LD Flatpack
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
D14.3
K14.A
D14.3
K14.A
D14.3
D14.3
K14.A
HS9-303BRH-8
HS0-303BRH-Q
HS1-303BRH-Q
HS9-303BRH-Q
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
14 LD SBDIP
D14.3
K14.A
14 LD Flatpack
FN6411.1
July 7, 2008
2
HS-303ARH, HS-303BRH
Functional Diagram
TRUTH TABLE
SW1 AND SW2
OFF
N
P
LOGIC
SW3 AND SW4
IN
0
1
ON
D
ON
OFF
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
2690µm x 5200µm (106 milsx205 mils)
Silicon
Thickness: 483µm ± 25.4µm (19 mils ± 1 mil)
INTERFACE MATERIALS:
Glassivation:
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ± 1.0kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
5
2
<2.0 x 10 A/cm
Type: AlSiCu
Thickness: 16.0kÅ ± 2kÅ
Transistor Count:
Substrate:
196
Radiation Hardened Silicon Gate,
Dielectric Isolation
Metallization Mask Layout
HS-303ARH, HS-303BRH
V-
V+
GND
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6411.1
July 7, 2008
3
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