HS0-303CEH-Q_技术文档

Radiation Hardened BiCMOS Dual SPDT Analog Switch

HS-303CEH

The HS-303CEH is an analog switch and a monolithic device

that is fabricated using Intersil’s dielectrically isolated

Features

• QML, per MIL-PRF-38535

• No latch-up, dielectrically isolated device islands

Radiation Hardened Silicon Gate (RSG) process technology to

insure latch-up free operation. It is pinout compatible and

functionally equivalent to the HS-303RH. This switch offers

low-resistance switching performance for analog voltages up

to the supply rails. ON-resistance is low and stays reasonably

constant over the full range of operating voltage and current.

ON-resistance also stays reasonably constant when exposed to

radiation. Break-before-make switching is controlled by 5V

digital inputs. The HS-303CEH can operate with rails of ±15V.

• Pinout and functionally compatible with intersil HS-303RH

series analog switches

• Analog signal range equal to the supply voltage range

• Low leakage . . . . . . . . . . . . . . . . . . . . . 150nA (max, post-rad)

• Low r . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω (max, post-rad)

ON

• Low standby supply current . . . . . . . ±150µA (max, post-rad)

• Radiation assurance

- High dose rate (50 to 300rad(Si)/s) . . . . . . . . 100krad(Si)

- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 50krad(Si)*

• Single event effects

Specifications

The Detailed Electrical Specifications for the HS-303CEH is

contained in SMD 5962-95813. A “hot-link” is provided from

our website for downloading.

2

- For LET = 60MeV-mg/cm at 60° incident angle,

<150pC charge transferred to the output of an off switch

* Product capability established by initial characterization. The

EH version is acceptance tested on a wafer-by-wafer basis to

50krad(Si) at low dose rate.

S

16

14

12

10

8

N

P

IN

D

6

4

2

FIGURE 1. LOGIC CIRCUIT

0

10

11

12

13

14

15

TABLE 1. TRUTH TABLE

NEGATIVE SUPPLY VOLTAGE (V

)

EE-

LOGIC

SW1 AND SW2

SW3 AND SW4

0

1

OFF

ON

FIGURE 2. RECOMMENDED OPERATING AREA IN GREY

OFF

April 19, 2013

FN8399.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

HS-303CEH

Pin Configuration

HS-303CEH

(14 LD FLATPACK)

TOP VIEW

1

2

3

4

5

6

7

14

13

V+

S4

D4

D2

S2

IN2

V-

NC

S3

12

11

10

9

D3

D1

S1

IN1

GND

8

Pin Descriptions

PIN NUMBER

PIN NAME

PIN DESCRIPTION

1

2

NC

Not Electrically Connected

S3

Analog Switch: Source connection

Analog Switch: Drain Connection

Analog Switch: Source connection

Digital Control Input for SW1 and SW3

Ground

3

D3

4

D1

5

S1

6

IN1

GND

V-

7

8

Negative Power Supply

9

IN2

S2

Digital Control Input for SW2 and SW4

Analog Switch: Source connection

Analog Switch: Drain Connection

Analog Switch: Source connection

Positive Power Supply

10

11

12

13

14

D2

D4

S4

V+

Ordering Information

ORDER

NUMBER

PART

NUMBER

TEMP. RANGE

PACKAGE

(Pb-free)

PKG.

DWG. #

(°C)

5962R9581308VXC

5962R9581308V9A

HS9-303CEH/PROTO

HS0-303CEH/SAMPLE

HS9-303CEH-Q

HS0-303CEH-Q

-55 to +125

14 Ld Flatpack

Die

K14.A

N/A

HS9-303CEH/PROTO

HS0-303CEH/SAMPLE

14 Ld Flatpack

Die

K14.A

N/A

NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with

both SnPb and Pb-free soldering operations.

FN8399.1

April 19, 2013

2

HS-303CEH

Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V

±V to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±17.5V

Analog Input Voltage

Thermal Resistance (Typical)

Flatpack Package (Notes 1, 2) . . . . . . . . . .

Package Power Dissipation at 125°C

θ

_JA(°C/W)

105

θ

_JC(°C/W)

17

SUPPLY

(+V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

+1.5V

-1.5V

Flatpack Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.48W/°C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C

S

SUPPLY

(-V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -V

S

SUPPLY

Digital Input Voltage

Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C

J

(+V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V

+4V

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

A

SUPPLY

(-V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-V

-4V

A

SUPPLY

Peak Current (S or D)

(Pulse at 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 40mA

Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Recommended Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Operating Supply Voltage Range (±V

) . . . . . . . . . . . . . . . . . . . . ±15V

SUPPLY

Analog Input Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

S

SUPPLY

Logic Low Level (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V

AL

Logic High Level (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0V to +V

AH SUPPLY

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. For θ , the “case temp” location is the center of the package underside.

JC

Electrical Specifications V

= ±15V unless otherwise specified. Boldface limits apply across the operating temperature range,

SUPPLY

-55°C to +125°C.

MIN

MAX

SYMBOL

PARAMETER

“Switch On” Resistance

TEST CONDITIONS

= 10V, I = -10mA

(Note 5) TYP (Note 5) UNITS

+r

V

35

75

Ω

DS(ON)

D

S

-r

+I

= -10V, I = 10mA

Ω

DS(ON)

S

Leakage Current into Source of an “OFF” Switch

Leakage Current into Drain of an “OFF” Switch

= +14V, V = -14V

-150

-20

0.05

150

20

nA

µA

nA

µA

nA

µA

nA

µA

nA

S(OFF)

D

= +15V, V = -15V

D

-I

= -14V, V = +14V

-150

-20

0.5

0.05

0.5

150

20

D

= -15V, V = +15V

D

+I

= +14V, V = -14V

-150

-20

150

20

D(OFF)

D

= +15V, V = -15V

D

-I

= -14V, V = +14V

-150

-20

150

20

D

= -15V, V = +15V

D

+I

Leakage Current from an “ON” Driver into the

Switch (Drain and Source)

= +14V, V = +14V

-100

-0.1

100

D(ON)

D

-I

Leakage Current from an “ON” Driver into the

Switch (Drain and Source)

V

= -14V, V = -14V

-100

0.01

100

nA

D(ON)

S

D

I

Low Level Input Address Current

High Level Input Address Current

Positive Supply Current

All Channels V = 0.8V

-1000 0.03 1000

nA

AL

A

I

All Channels V = 4.0V

A

AH

I+

All Channels V = 0.8V

45

150

0.6

µA

mA

A

V

= 0V, V = 4V

A2

0.15

A1

V

= 4V, V = 0V

A1

A2

I-

Negative Supply Current

All Channels V = 0.8V

-0.1

-100

µA

A

V

= 0V, V = 4V

A2

A1

V

= 4V, V = 0V

A1

A2

CIS(OFF) Switch Input Capacitance

From Source to GND (Notes 3, 4)

V = 0V (Notes 3, 4)

A

28

10

pF

CC1

Driver Input Capacitance

FN8399.1

April 19, 2013

3

HS-303CEH

Electrical Specifications V

= ±15V unless otherwise specified. Boldface limits apply across the operating temperature range,

SUPPLY

-55°C to +125°C. (Continued)

MIN

MAX

SYMBOL

CC2

PARAMETER

Driver Input Capacitance

TEST CONDITIONS

= 15V (Notes 3, 4)

(Note 5) TYP (Note 5) UNITS

V

10

28

pF

dB

mV

ns

A

COS

Switch Output

Off Isolation

Measured Drain to GND (Notes 3, 4)

V

= 1V , f = 1MHz (Notes 3, 4)

p-p

40

ISO

GEN

V

Cross Talk

= 1V , f = 1MHz (Notes 3, 4)

p-p

CR

GEN

V

Charge Transfer Error

= GND, C = 0.01µF (Notes 3, 4)

15

CTE

S

L

t

Break-Before-Make Time Delay

Switch Turn “ON” Time

R

= 300Ω, V = 3V, V = 5V, V = 0V

AH AL

10

50

300

500

450

OPEN

L

S

t

= 300Ω, V = 3V, V = 4V, V = 0V

AH AL

250

200

ns

ON

S

t

Switch Turn “OFF” Time

= 300Ω, V = 3V, V = 4V, V = 0V

AH AL

ns

OFF

S

NOTES:

3. Limits established by characterization and are not production tested.

4. VAL = 0V and VAH = 4V.

5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Post Radiation Characteristics V

= ±15V unless otherwise specified. This data is typical test data post radiation exposure at a

SUPPLY

rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to total ionizing dose (high dose radiation) T = +25°C.

A

SYMBOL

PARAMETER

TEST CONDITIONS

= 10V, I = -10mA

0k

34

100k UNITS

+r

“Switch On” Resistance

V

35

29

Ω

DS(ON)

D

S

-r

+I

= -10V, I = 10mA

28

Ω

DS(ON)

S

Leakage Current into Source of an “OFF” Switch

Leakage Current into Drain of an “OFF” Switch

= +14V, V = -14V

-0.20

-0.31

nA

µA

nA

µA

nA

µA

nA

µA

nA

S(OFF)

D

= +15V, V = -15V

-0.003 -0.47

D

-I

= -14V, V = +14V

0.30

0.001

-1.20

0.84

0.02

-0.90

D

= -15V, V = +15V

D

+I

= +14V, V = -14V

D

D(OFF)

= +15V, V = -15V

-0.001 -0.001

0.31 0.90

0.0003 0.001

D

-I

= -14V, V = +14V

D

= -15V, V = +15V

D

+I

Leakage Current from an “ON” Driver into the Switch (Drain

and Source)

= +14V, V = +14V

-0.2

-0.55

D(ON)

D

-I

Leakage Current from an “ON” Driver into the Switch (Drain

and Source)

V

= -14V, V = -14V

0.15

0.28

nA

D(ON)

S

D

I

Low Level Input Address Current

High Level Input Address Current

Positive Supply Current

All Channels V = 0.8V

0.35

1.98

55

0.25

1.47

53

nA

µA

AL

A

I

All Channels V = 4.0V

A

AH

I+

All Channels V = 0.8V

A

V

= 0V, V = 4V

A2

167.2 113.7

A1

V

= 4V, V = 0V

A1

A2

I-

Negative Supply Current

All Channels V = 0.8V

-0.01

-0.02

µA

A

V

= 0V, V = 4V

A2

A1

V

= 4V, V = 0V

A1

A2

t

Break-Before-Make Time Delay

Switch Turn “ON” Time

R = 300Ω, V = 3V, V = 5V, V = 0V

42

47

ns

OPEN

L

S

AH

AL

t

R

= 300Ω, V = 3V, V = 4V, V = 0V

224

192

213

173

ON

S

AH AL

t

Switch Turn “OFF” Time

= 300Ω, V = 3V, V = 4V, V = 0V

AH AL

OFF

S

FN8399.1

April 19, 2013

4

HS-303CEH

Post Radiation Characteristics V

= ±15V unless otherwise specified. This data is typical test data post radiation exposure

SUPPLY

at a rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to total ionizing dose (low dose radiation). T = +25°C.

A

SYMBOL

PARAMETER

“Switch On” Resistance

TEST CONDITIONS

= 10V, I = -10mA

0k

25k

50k

75k

100k UNITS

+r

V

33.57

27.56

-0.30

-0.006

0.32

34.39 34.37 34.75 34.65

Ω

DS(ON)

D

S

-r

+I

= -10V, I = 10mA

28.37 28.48 28.92

-0.26 -0.36 -0.55

28.77

-0.47

Ω

DS(ON)

S

Leakage Current into Source of an

“OFF” Switch

= +14V, V = -14V

nA

µA

nA

µA

nA

µA

nA

µA

nA

S(OFF)

D

= +15V, V = -15V

-0.002 -0.002 -0.003 -0.002

0.45 0.75 1.05 0.94

0.003 0.003 0.003 0.002

-0.22 -0.25 -0.46 -0.40

-0.001 -0.001 -0.001 -0.002

0.43 0.69 1.02 0.92

D

-I

Leakage Current into Source of an

“OFF” Switch

= -14V, V = +14V

D

= -15V, V = +15V

0.004

-0.36

-0.001

0.34

D

+I

Leakage Current into Drain of an “OFF”

Switch

= +14V, V = -14V

D

D(OFF)

= +15V, V = -15V

D

-I

Leakage Current into Drain of an “OFF”

Switch

= -14V, V = +14V

D

= -15V, V = +15V

0.0004 0.0008 0.0011 0.0014 0.0018

D

+I

Leakage Current from an “ON” Driver

into the Switch (Drain and Source)

= +14V, V = +14V

-0.25

-0.26

-0.36

-0.55

-0.65

D(ON)

D

-I

Leakage Current from an “ON” Driver

into the Switch (Drain and Source)

V

= -14V, V = -14V

0.17

0.15

0.26

0.45

0.40

nA

D(ON)

S

D

I

Low Level Input Address Current

High Level Input Address Current

Positive Supply Current

All Channels V = 0.8V

0.19

1.72

54

0.30

0.87

51

0.23

0.83

50

0.71

0.28

49

0.48

1.31

50

nA

µA

AL

A

I

All Channels V = 4.0V

A

AH

I+

All Channels V = 0.8V

A

V

= 0V, V = 4V

A2

185

146

129

116

106

A1

V

= 4V, V = 0V

A1

A2

I-

Negative Supply Current

All Channels V = 0.8V

-0.011

-0.013

-0.015 -0.011 -0.019 -0.022

-0.016 -0.017 -0.019 -0.014

µA

A

V

= 0V, V = 4V

A2

A1

V

= 4V, V = 0V

A1

A2

t

Break-Before-Make Time Delay

Switch Turn “ON” Time

R = 300Ω, V = 3V, V = 5V, V = 0V

AH AL

42.58

50.84 55.63 56.74

58.06

ns

OPEN

L

S

t

R = 300Ω, V = 3V, V = 4V, V = 0V

AH AL

221.03 229.24 240.85 249.79 256.37

188.62 184.65 182.27 184.06 182.45

ON

L

S

t

Switch Turn “OFF” Time

R = 300Ω, V = 3V, V = 4V, V = 0V

AH AL

OFF

L

S

FN8399.1

April 19, 2013

5

HS-303CEH

FIGURE 4. SWITCHING TEST CIRCUIT WAVEFORM

FIGURE 3. SWITCHING TEST CIRCUIT

FIGURE 5. BREAK-BEFORE-MAKE TEST CIRCUIT

FIGURE 6. BREAK-BEFORE-MAKE TEST CIRCUIT WAVEFORMS

FN8399.1

April 19, 2013

6

HS-303CEH

Backside Finish:

Die Characteristics

DIE DIMENSIONS:

Silicon

ASSEMBLY RELATED INFORMATION:

2815µm x 5325µm (106 milsx205 mils)

Thickness: 483µm ± 25.4µm (19 mils ± 1 mil)

Substrate Potential:

Unbiased (DI)

INTERFACE MATERIALS:

Glassivation:

ADDITIONAL INFORMATION:

Worst Case Current Density:

Type: PSG (Phosphorous Silicon Glass)

Thickness: 8.0kÅ ± 1.0kÅ

5

2

<2.0 x 10 A/cm

Top Metallization:

Transistor Count:

Type: AlSiCu

Thickness: 16.0kÅ ± 2kÅ

216

Package Lid Potential:

Substrate:

Floating

Radiation Hardened Silicon Gate,

Dielectric Isolation

Metallization Mask Layout

HS-303CEH

V+

S3

S4

D3

D4

D1

S1

D2

S2

IN1

IN2

GND

V-

ORIGIN

FN8399.1

April 19, 2013

7

HS-303CEH

Layout Characteristics

Step and Repeat: 2815µm x 5325µm

TABLE 2. LAYOUT X-Y COORDINATES

PAD NAME

S3

X (µm)

0

Y (µm)

4672.5

3861

1314

617.5

0

DX (µm)

109

DY (µm)

109

D3

-4.5

D1

-4.5

S1

0

IN1

GND

VEE

IN2

S2

0

878

0

1246

2124

2128.5

2124

1062

0

617.5

1314

3861

4672

4675

D2

D4

S4

VCC

NOTE: "Origin" as labeled in the Metallization Mask layout is the centroid

of the pad labeled "IN1".

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8399.1

April 19, 2013

8

HS-303CEH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that

you have the latest revision.

DATE

REVISION

FN8399.1

CHANGE

April 5, 2013

Title on page 1 changed CMOS to BiCMOS

Continuous Current in “Absolute Maximum Ratings” on page 3 changed from 30mA to 10mA

“Post Radiation Characteristics” on page 4 changed unit in positive supply current from mA to µA.

March 26, 2013

Updated throughout 300krad to 100krad.

Updated Ordering Information on page 2

Updated Electrical Spec Table MIN and MAX values for Leakage Current in Source and Drain for ±15V from

±5 to ±20

Updated in Post Radiation Characteristics Typical values on page 4 for Positive Supply Current for VA1, VA2

from 107.1 to 113.7 and Negative Supply Current for VA1, VA2 from -0.01 to -0.02

Added 100k column to Post Radiation Characteristics table on page 5

Removed negative symbol under 75k column IAL, IAH from 0.71, 0.28 and added negative symbol in I- to

0.019 in VA1, VA2

Removed the words exposed pad from Tjc note.

Updated numbers in Table 2 in X(µm) column.

Added Note to Table 2.

December 21, 2012

FN8399.0

Initial Release

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,

personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of

our winning team, visit our website and career page at www.intersil.com.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.

Also, please check the product information page to ensure that you have the most updated datasheet: HS-303CEH

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php

FN8399.1

April 19, 2013

9

HS-303CEH

Ceramic Metal Seal Flatpack Packages (Flatpack)

K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A

e

INCHES MILLIMETERS

MIN

PIN NO. 1

ID AREA

SYMBOL

MAX

0.115

0.022

0.019

0.009

0.006

0.390

0.260

0.290

-

MIN

1.14

0.38

0.10

-

MAX

2.92

0.56

0.48

0.23

0.15

9.91

6.60

7.11

-

NOTES

D

A

b

0.045

0.015

0.004

-

-A-

-B-

S1

b1

c

-

b

c1

D

-

E1

3

-

0.004

Q

H

A - B

D

0.036

H

A - B

D

S

M

S

M

S

C

E

0.235

-

5.97

-

E

E1

E2

E3

e

3

-

-D-

A

0.125

0.030

3.18

0.76

-H-

-C-

-

7

-

L

E2

L

E3

0.050 BSC

1.27 BSC

SEATING AND

BASE PLANE

c1

LEAD FINISH

k

0.008

0.270

0.026

0.005

-

0.015

0.370

0.045

-

0.20

6.86

0.66

0.13

-

0.38

9.40

1.14

-

2

-

L

BASE

METAL

Q

S1

M

N

8

6

-

(c)

b1

0.0015

0.04

M

(b)

14

-

SECTION A-A

Rev. 0 5/18/94

NOTES:

1. Index area: A notch or a pin one identification mark shall be located

adjacent to pin one and shall be located within the shaded area

shown. The manufacturer’s identification shall not be used as a pin

one identification mark. Alternately, a tab (dimension k) may be

used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the limits

of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass over-

run.

4. Dimensions b1 and c1 apply to lead base metal only. Dimension M

applies to lead plating and finish thickness. The maximum limits of

lead dimensions b and c or M shall be measured at the centroid of

the finished lead surfaces, when solder dip or tin plate lead finish is

applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric materi-

als shall be molded to the bottom of the package to cover the leads.

8. Dimension Q shall be measured at the point of exit (beyond the me-

niscus) of the lead from the body. Dimension Q minimum shall be

reduced by 0.0015 inch (0.038mm) maximum when solder dip lead

finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

FN8399.1

April 19, 2013

10


型号：	HS0-303CEH-Q
厂家：	Intersil
描述：	Radiation Hardened BiCMOS Dual SPDT Analog Switch 抗辐射的BiCMOS双路SPDT模拟开关开关光电二极管
文件：	总10页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HS0-303CEH-Q [INTERSIL]

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