HS9-565BEH-Q [INTERSIL]
Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter; 抗辐射高速，单片式数位类比转换器
| 型号： | HS9-565BEH-Q |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter |
| 文件： | 总9页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radiation Hardened High Speed, Monolithic
Digital-to-Analog Converter
HS-565BRH, HS-565BEH
Features
The HS-565BRH, HS-565BEH are fast, radiation hardened
12-bit current output, digital-to-analog converters. This part
replaces the HS-565ARH, which is no longer available. The
monolithic chips include a precision voltage reference,
thin-film R-2R ladder, reference control amplifier and twelve
high-speed bipolar current switches.
• Electrically Screened to SMD # 5962-96755
• QML Qualified per MIL-PRF-38535 Requirements
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
The Intersil Dielectric Isolation process provides latch-up free
operation while minimizing stray capacitance and leakage
currents, to produce an excellent combination of speed and
accuracy. Also, ground currents are minimized to produce a
low and constant current through the ground terminal, which
reduces error due to code-dependent ground currents.
• Low Gain Drift
(Max., DAC Plus Reference) . . . . . . . . . . . . . . . . . . 50ppm/°C
HS-565BRH, HS-565BEH die are laser trimmed for a
• ±0.75 LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at +25°C)
maximum integral nonlinearity error of ±0.25 LSB at +25°C. In
addition, the low noise buried zener reference is trimmed both
for absolute value and minimum temperature coefficient.
Applications
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
Specifications for Rad Hard QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755. A “hot-link” is provided on our
website for downloading.
BIP.
REF OUT VCC
OFF.
11
4
3
20V SPAN
8
+
5k
5k
10V
10
9
-
10V SPAN
OUT
9.95k
IO
IREF
DAC
0.5mA
19.95k
6
5
REF IN
+
-
3.5k
3k
2.5k
(4X IREF
X CODE)
REF GND
7
12
24 . . . 13
MSB LSB
-VEE PWR
GND
FIGURE 1. FUNCTIONAL DIAGRAM
May 7, 2012
FN4607.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2003, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
HS-565BRH, HS-565BEH
Pin Configurations
HS1-565BRH, HS1-565BEH
HS9-565BRH, HS9-565BEH
MIL-STD-1835 CDFP4-F24
(CERAMIC FLATPACK)
TOP VIEW
MIL-STD-1835 CDIP2-T24
(SBDIP)
TOP VIEW
BIT 1 IN
(MSB)
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
1
2
3
4
5
6
7
8
9
BIT 1 IN (MSB)
24
23 BIT 2 IN
22
NC
NC
2
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
3
VCC
VCC
BIT 3 IN
4
REF OUT
REF GND
REF IN
REF OUT
REF GND
REF IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
5
6
7
-VEE
8
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
-VEE
9
BIPOLAR RIN
IDAC OUT
10
11
12
BIT 12 IN
(LSB)
15
10V SPAN 10
20V SPAN 11
PWR GND 12
BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
Ordering Information
TEMP. RANGE
PACKAGE
(Pb-Free)
ORDERING NUMBER
5962R9675502V9A
5962R9675502VJC
5962R9675502VXC
HS9-565BRH/PROTO
5962R9675503V9A
5962R9675503VJC
5962R9675503VXC
PART NUMBER
PART MARKING
(°C)
PKG. DWG. #
HS0-565BRH-Q
HS1-565BRH-Q
HS9-565BRH-Q
HS9-565BRH/PROTO
HS0-565BEH-Q
HS1-565BEH-Q
HS9-565BEH-Q
+25
Q 5962R96 75502VJC
Q 5962R96 75502VXC
HS9- 565BRH /PROTO
-55 to +125
-55 to +125
-55 to +125
+25
24 Ld SBDIP
D24.6
K24.A
24 Ld Flatpack
Q 5962R96 75503VJC
Q 5962R96 75503VXC
-55 to +125
-55 to +125
24 Ld SBDIP
D24.6
K24.A
24 Ld Flatpack
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
FN4607.4
May 7, 2012
2
HS-565BRH, HS-565BEH
Definitions of Specifications
Burn-In Bias Circuit
Digital Inputs
1
NC
BIT 1 24
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
The HS-565BRH, HS-565BEH accepts digital input codes in
binary format and may be user connected for any one of three
binary codes. Straight binary, Two’s Complement (see note
below), or Offset Binary.
2
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 2
BIT 3
+15V
D1
3
VCC
C1
4
REF OUT
REF GND
REF IN
-VEE
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
5
DIGITAL
INPUT
ANALOG OUTPUT
6
-15V
D2
TWO’S
COMPLEMENT
(Note)
7
STRAIGHT
BINARY
OFFSET
BINARY
C2
C3
8
MSB...LSB
000.... 000
100.... 000
111.... 111
011.... 111
BIP OFF
OUT
9
Zero
-FS (Full Scale)
Zero
Zero
-FS
+10V
D3
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
0.50 FS
+FS - 1LSB
0.50 FS - 1LSB
+FS - 1LSB
Zero - 1LSB
Zero - 1LSB
+FS - 1LSB
F11
NOTE: Invert MSB with external inverter to obtain Two’s Complement
Coding
NOTES:
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11:
VIH = 5.0V ±0.5V
VIL = 0.0V ±0.5V
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an important
measure of its accuracy. It describes the deviation from an ideal
straight line transfer curve drawn between zero (all bits OFF) and
full scale (all bits ON).
F0 = 100kHz ±10% (50% Duty Cycle)
F1 = F0/2
F2 = F0/4
F3 = F0/8
F4 = F0/16
F5 = F0/32
F6 = F0/64
F7 = F0/128
F8 = F0/256
F9 = F0/512
F10 = F0/1024
F11 = F0/2048
Differential Nonlinearity - For a D/A converter, it is the difference
between the actual output voltage change and the ideal (1 LSB)
voltage change for a one bit change in code. A Differential
Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the
output always increases and never decreases for an increasing
input.
Radiation Bias Circuit
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
2
NC
Settling Time
+15V
3
VCC
Settling time is the time required for the output to settle to within
the specified error band for any input code transition. It is usually
specified for a full scale or major carry transition, settling to
within 0.50 LSB of final value.
4
REF OUT
REF GND
REF IN
-VEE
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
5
+5V
6
-15V
7
Drift
8
BIP OFF
OUT
Gain Drift - The change in full scale analog output over the
specified temperature range expressed in parts per million of full
scale range per °C (ppm of FSR/°C). Gain error is measured with
respect to +25°C at high (TH) and low (TL) temperatures. Gain
drift is calculated for both high (TH - +25°C) and low ranges
(+25°C - TL) by dividing the gain error by the respective change in
temperature. The specification is the larger of the two
representing worst case drift.
9
+10V
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
NOTE: Power Supply Levels are ±0.5V
Offset Drift - The change in analog output with all bits OFF over
the specified temperature range expressed in parts per million of
full scale range per °C (ppm of FSR/°C). Offset error is
measured with respect to +25°C at high (TH) and low (TL)
temperatures. Offset drift is calculated for both high (TH - +25°C)
and low (+25°C - TL) ranges by dividing the offset error by the
respective change in temperature. The specification given is the
larger of the two, representing worst case drift.
FN4607.4
May 7, 2012
3
HS-565BRH, HS-565BEH
Power Supply Sensitivity
No Trim Operation
Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in -15V or
+15V supplies. It is specified under DC conditions and expressed
as parts per million of full scale range per percent of change in
power supply (ppm of FSR/%).
The HS-565BRH, HS-565BEH will perform as specified without
calibration adjustments. To operate without calibration,
substitute 50Ω resistors for the 100Ω trimming
potentiometers: In Figure 2 replace R2 with 50Ω; also remove
the network on pin 8 and connect 50Ω to ground. For bipolar
operation in Figure 3, replace R3 and R4 with 50Ω resistors.
Typical unipolar zero will be ±0.50 LSB plus the op amp offset.
Compliance
Compliance Voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and makes
no claims to accuracy.
The feedback capacitor C must be selected to minimize settling
time.
R4
100Ω
R3
100Ω
VCC
Glitch
REF OUT
BIP.
OFF.
4
3
8
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half scale or the major carry code
transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example,
if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an
intermediate state of 000 . . . 0 exists, such that, the output
momentarily glitches toward zero output. Matched switching
times and fast switching will reduce glitches considerably.
11
10
20V SPAN
10V SPAN
HS-565BRH
+
-
5k
5k
10V
VO
IREF
9.95k
DAC
DAC
OUT
0.5mA
19.95k
6
5
C
-
IO
REF
IN
+
-
9
3.5k
3k
(4 x IREF
x CODE)
+
2.5k
REF
GND
R (SEE
TABLE 1)
Applying the HS-565BRH and
HS-565BEH
CODE
INPUT
7
. . . . .
13
24
MSB
OP AMP Selection
-VEE
LSB
PWR
GND
The HS-565BRH, HS-565BEH current output may be converted to
voltage using the standard connections shown in Figures 2 and 3.
The choice of operational amplifier should be reviewed for each
application, since a significant trade-off may be made between
speed and accuracy. Remember settling time for the
DAC-amplifier combination is:
FIGURE 3. BIPOLAR VOLTAGE OUTPUT
Calibration
Calibration provides the maximum accuracy from a converter by
adjusting its gain and offset errors to zero. For the HS-565BRH,
HS-565BEH, these adjustments are similar whether the current
output is used, or whether an external op amp is added to
convert this current to a voltage. Refer to Table 1 for the voltage
output case, along with Figure 2 or 3.
2
2
(t
) + (t )
D
A
where t , t are settling times for the DAC and amplifier.
D
A
+15V
100kΩ
100Ω
R1
50kΩ
Calibration is a two step process for each of the five output
ranges shown in Table 1. First adjust the negative full scale (zero
for unipolar ranges). This is an offset adjust which translates the
output characteristic, i.e., affects each code by the same
amount.
R2
100Ω
-15V
VCC
REF OUT
BIP.
OFF.
4
3
8
11
20V SPAN
HS-565BRH
+
-
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
5k
10V
10
VO
10V SPAN
IREF
9.95k
DAC
For the bipolar ranges, this approach leaves an error at the zero
code, whose maximum values is the same as for integral
nonlinearity error. In general, only two values of output may be
calibrated exactly; all others must tolerate some error. Choosing
the extreme end points (plus and minus full scale) minimizes this
distributed error for all other codes.
DAC
OUT
5k
0.5mA
19.95k
C
6
5
-
IO
REF
IN
+
-
9
3.5k
3k
(4 x IREF
x CODE)
+
2.5k
REF
GND
R (SEE
TABLE 1)
CODE
INPUT
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 2. UNIPOLAR VOLTAGE OUTPUT
FN4607.4
May 7, 2012
4
HS-565BRH, HS-565BEH
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 4A and 4B for
the measurement of case (d).
Settling Time
This is a challenging measurement, in which the result depends
on the method chosen, the precision and quality of test
equipment and the operating configuration of the DAC (test
conditions). As a result, the different techniques in use by
converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test method before using the specified
settling time as a basis for design.
Procedure
As shown in Figure 4B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of several
microseconds. This assures that the DAC output has settled to
its final wave.
The approach used for several years at Intersil calls for a strobed
comparator to sense final perturbations of the DAC output
waveform. This gives the LSB a reasonable magnitude (814mV)
for the HS-565BRH, HS-565BEH, which provides the comparator
with enough overdrive to establish an accurate ±0.50 LSB
window about the final settled value. Also, the required test
conditions simulate the DACs environment for a common
application - use in a successive approximation A/D converter.
Considerable experience has shown this to be a reliable and
repeatable way to measure settling time.
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at COMPARATOR
OUT. This is indicated by traces of equal brightness on the
oscilloscope display as shown in Figure 4B. Note DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before, and
note DVM reading. One LSB equals one tenth the difference in
the DVM readings noted above.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-to-off
(tOFF). The slower of the two cases is specified, as measured
from 50% of the digital input transition to the final entry within a
window of ±0.50 LSB about the settled value. Four
• Adjust the VLSB supply to reduce the DVM reading by 5 LSBs
(DVM reads 10X, so this sets the comparator to sense the final
settled value minus 0.50 LSB). Comparator output disappears.
• Reduce generator number 2 delay until comparator output
reappears, and adjust for “equal brightness”.
measurements characterize a given type of DAC:
• Measure tX from scope as shown in Figure 4B. Settling time
equals tX + tD, i.e., tX + 15ns.
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
CALIBRATION
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
MODE
ADJUST
TO SET VO
Unipolar (See Figure 2)
0 to +10V
0 to +5V
±10V
VO
VO
NC
VO
VO
Pin 10
Pin 9
VO
1.43k
1.1k
All 0’s
All 1’s
R1
R2
0V
+9.99756V
All 0’s
All 1’s
R1
R2
0V
+4.99878V
Bipolar (See Figure 3)
1.69k
1.43k
1.1k
All 0’s
All 1’s
R3
R4
-10V
+9.99512V
±5V
Pin 10
Pin 9
All 0’s
All 1’s
R3
R4
-5V
+4.99756V
±2.5V
All 0’s
All 1’s
R3
R4
-2.5V
+2.49878V
FN4607.4
May 7, 2012
5
HS-565BRH, HS-565BEH
SYNC
IN
PULSE
GENERATOR
NO. 1
PULSE
GENERATOR
NO. 2
OUT
OUT
TRIG
OUT
C
20V ± 20%
BIAS
A
HS-565BRH
TURN ON
8
24
TURN OFF
11
23
.
.
.
5k
+3V
.
9.95k
10
9
.
50%
A
NC
DIGITAL
INPUT
.
0V
.
.
-0.50LSB
5k
STROBE IN
.
.
DAC
OUTPUT
B
+
0V
D
.
~100
kHz
COMPARATOR
OUT
.
B
.
-
-400mV
(TURN OFF)
14
2.5k
SETTLING TIME
tD = COMPARATOR DELAY
P
5
13
2mA
tX
50%
5V
COMP.
STROBE
2V
C
12
LSB
90
200k
0.8V
“EQUAL BRIGHTNESS”
VLSB
SUPPLY
10
DVM
0.1µF
COMP.
OUT
4V
D
0V
.
FIGURE 4A.
FIGURE 4B.
Other Considerations
Grounds
Layout
The HS-565BRH, HS-565BEH has two ground terminals, pin 5 (REF
GND) and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point exists,
then separate paths are required to pins 5 and 12).
Connections to pin 9 (IOUT) on the HS-565BRH, HS-565BEH are
most critical for high speed performance. Output capacitance of
the DAC is only 20pF, so a small change of additional capacitance
may alter the op amp’s stability and affect settling time.
Connections to pin 9 should be short and few. Component leads
should be short on the side connecting to pin 9 (as for feedback
capacitor C). See the “Settling Time” section on page 5.
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits 1, 2,
and 3. The general rule is to connect pin 5 directly to the system
“quiet” point, usually called signal or analog ground. Connect pin
12 to the local digital or power ground. Then, of course, a single
path must connect the analog/signal and digital/power grounds.
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve the
HS-565BRH, HS-565BEH also. If no op amp is used, a 0.01µF
ceramic capacitor from each supply terminal to pin 12 is
sufficient, since supply current variations are small.
NOTE: Current cancellation is a two step process within the
HS-565BRH, HS-565BEH in which code dependent variations
are eliminated, the resulting DC current is supplied internally.
First an auxiliary 9-bit R-2R ladder is driven by the complement
of the DACs input code. Together, the main and auxiliary
ladders draw a continuous 2.25mA from the internal ground
node, regardless of input code. Part of the DC current is
supplied by the zener voltage reference, and the remainder is
sourced from the positive supply via a current mirror which is
laser trimmed for zero current through the external terminal
(pin 5).
FN4607.4
May 7, 2012
6
HS-565BRH, HS-565BEH
Die Characteristics
DIE DIMENSIONS:
ASSEMBLY RELATED INFORMATION
179 mils x 107 mils x 19 mils
Substrate Potential:
Tie Substrate to VREF GND
INTERFACE MATERIALS:
Glassivation:
ADDITIONAL INFORMATION:
Worst Case Current Density:
Type: AlCu
Thickness: 8kÅ ±1kÅ
5
2
2.0 x 10 A/cm
Top Metallization:
Transistor Count:
Type: Al/Copper
Thickness: 16kÅ ±2kÅ
200
Substrate:
Bipolar DI,
Backside Finish:
Silicon
Metallization Mask Layout
HS-565BRH, HS-565BEH
(MSB)
BIT 1
VCC NC NC
A
BIT 2
3
3
1
VREF OUT
BIT 3
VREF
GND
BIT 4
BIT 5
VREF IN
-VS
BIT 6
BIPOLAR
12
BIT 7
BIT 8
IDAC
OUT
BIT 9
10V
SPAN
BIT 10
20V
SPAN
POWER
GND
BIT 12
(LSB)
BIT 11
FN4607.4
May 7, 2012
7
HS-565BRH, HS-565BEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
LEAD FINISH
D24.6 MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C)
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-A-
-D-
E
INCHES
MIN
MILLIMETERS
BASE
METAL
(c)
SYMBOL
MAX
0.225
0.026
0.023
0.065
0.045
0.018
0.015
1.290
0.610
MIN
-
MAX
5.72
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
S
S
S
D
bbb
C
A - B
1.65
-
D
1.14
4
BASE
S2
Q
PLANE
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
32.77
15.49
-
S1
b2
eA
A A
E
0.500
12.70
-
e
eA/2
C A - B S D S
b
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
M
C A - B S D S
aaa
M
-
NOTES:
0.120
0.200
3.05
5.08
-
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark.
Q
0.015
0.005
0.005
0.075
0.38
0.13
0.13
1.91
5
S1
S2
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
o
o
o
o
90
105
90
-
105
0.38
0.76
0.25
0.038
-
aaa
bbb
ccc
M
N
-
-
-
-
0.015
0.030
0.010
0.0015
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
-
-
-
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b2.
-
2
24
24
8
5. Dimension Q shall be measured from the seating plane to the base plane.
6. Measure dimension S1 at all four corners.
Rev. 0 4/94
7. Measure dimension S2 from the top of the ceramic body to the nearest
metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4607.4
May 7, 2012
8
HS-565BRH, HS-565BEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K24.A MIL-STD-1835 CDFP4-F24 (F-6A, CONFIGURATION B)
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.640
0.420
0.450
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
16.26
10.67
11.43
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-A-
-B-
S1
-
b1
c
-
-
b
c1
D
E
-
E1
3
0.004
Q
H
A - B
D
0.036
H
A - B
D
S
M
S
S
M
S
0.350
-
9.14
-
-
C
E
E1
E2
E3
e
3
-D-
A
0.180
0.030
4.57
0.76
-
-H-
-C-
-
-
7
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
-
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.13
-
0.38
9.40
1.14
-
2
L
-
BASE
METAL
Q
S1
M
N
8
(c)
6
b1
0.0015
0.04
-
M
M
(b)
24
24
-
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark. Alternately, a tab (dimension k) may be used to identify
pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of
dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-
plies to lead plating and finish thickness. The maximum limits of lead
dimensions b and c or M shall be measured at the centroid of the fin-
ished lead surfaces, when solder dip or tin plate lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the menis-
cus) of the lead from the body. Dimension Q minimum shall be reduced
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is
applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN4607.4
May 7, 2012
9
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