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HS9-80C85RH [INTERSIL]

Radiation Hardened 8-Bit CMOS Microprocessor; 抗辐射的8位CMOS微处理器
HS9-80C85RH
型号： HS9-80C85RH
厂家： Intersil    Intersil
描述：

Radiation Hardened 8-Bit CMOS Microprocessor
抗辐射的8位CMOS微处理器

微处理器
文件： 总19页 (文件大小：162K)
中文：  中文翻译
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HS-80C85RH  
Radiation Hardened  
8-Bit CMOS Microprocessor  
February 1996  
Features  
Description  
• Devices QML Qualified in Accordance With  
MIL-PRF-38535  
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-  
cated using the Intersil radiation hardened self-aligned junc-  
tion isolated (SAJI) silicon gate technology. Latch-up free  
operation is achieved by the use of epitaxial starting material  
to eliminate the parasitic SCR effect seen in conventional  
bulk CMOS devices.  
• Detailed Electrical and Screening Requirements are  
Contained in SMD# 5962-95824 and Intersil’ QM Plan  
• Radiation Hardened EPI-CMOS  
- Parametrics Guaranteed 1 x 105 RAD(Si)  
- Transient Upset > 1 x 108 RAD(Si)/s  
- Latch-up Free > 1 x 1012 RAD(Si)/s  
• Low Standby Current 500µA Max  
The HS-80C85RH is a functional logic emulation of the  
HMOS 8085 and its instruction set is 100% software com-  
patible with the HMOS device. The HS80C85RH is designed  
for operation with a single 5 volt power supply. Its high level  
of integration allows the construction of a radiation hardened  
microcomputer system with as few as three ICs (HS-  
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/  
56RH RAM I/O.  
• Low Operating Current 5.0mA/MHz (X1 Input)  
• Electrically Equivalent to Sandia SA 3000  
• 100% Software Compatible with INTEL 8085  
• Operation from DC to 2MHz, Post Radiation  
• Single 5 Volt Power Supply  
• On-Chip Clock Generator and System Controller  
• Four Vectored Interrupt Inputs  
• Completely Static Design  
• Self Aligned Junction Isolated (SAJI) Process  
• Military Temperature Range -55oC to +125oC  
Pinouts  
40 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835, CDIP2-T40  
TOP VIEW  
42 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
INTERSIL OUTLINE K42.A  
TOP VIEW  
X1  
X2  
VDD  
1
2
40  
39  
38  
37  
36  
35  
34  
33  
X1  
X2  
1
2
3
4
42  
41  
40  
39  
VDD  
HOLD  
HOLD  
HLDA  
3
RESET OUT  
SOD  
RESET  
OUT  
SOD  
HLDA  
CLOCK  
OUT  
CLOCK OUT  
4
SID  
5
RESET IN  
READY  
SID  
5
6
38  
37  
RESET  
TRAP  
6
IN  
TRAP  
READY  
RST 7.5  
RST 6.5  
7
IO / M  
S1  
RST 7.5  
RST 6.5  
7
8
36  
35  
IO / M  
S1  
8
RST 5.5  
INTR  
INTA  
AD0  
9
32 RD  
31 WR  
RST 5.5  
INTR  
INTA  
AD0  
9
34  
33  
32  
31  
30  
29  
28  
27  
RD  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
15  
16  
WR  
ALE  
30  
29 S0  
ALE  
S0  
AD1  
A15  
28  
27  
26  
25  
24  
23  
AD1  
A15  
A14  
AD2  
A14  
A13  
A12  
A11  
AD2  
AD3  
AD3  
A13  
15  
16  
17  
18  
19  
20  
AD4  
A12  
A11  
AD4  
AD5  
AD6  
AD7  
GND  
NC  
NC  
17  
18  
19  
26  
25  
24  
A10  
A9  
A10  
AD5  
22 A9  
A8  
AD6  
AD7  
20  
21  
23  
22  
A8  
21  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518054  
File Number 3036.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
HS-80C85RH  
Ordering Information  
PART NUMBER  
5962R9582401QQC  
5962R9582401QXC  
5962R9582401VQC  
5962R9582401VXC  
HS1-80C85RH/SAMPLE  
HS9-80C85RH/SAMPLE  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
40 Lead SBDIP  
o
o
-55 C to +125 C  
MIL-PRF-38535 Level Q  
MIL-PRF-38535 Level Q  
MIL-PRF-38535 Level V  
MIL-PRF-38535 Level V  
Sample  
o
o
-55 C to +125 C  
42 Lead Ceramic Flatpack  
40 Lead SBDIP  
o
o
-55 C to +125 C  
o
o
-55 C to +125 C  
42 Lead Ceramic Flatpack  
40 Lead SBDIP  
o
+25 C  
o
+25 C  
Sample  
42 Lead Ceramic Flatpack  
Functional Diagram  
RST RST RST  
5.5 6.5 7.5 TRAP  
INTA  
INTR  
SID  
SOD  
INTERRUPT CONTROL  
SERIAL I/O CONTROL  
8-BIT  
INTERNAL DATA BUS  
ACCUMU-  
LATOR (8)  
TEMP REG  
(8)  
FLAG (5)  
FLIP FLOPS  
INSTRUCTION  
REGISTER (8)  
B REG (8)  
D REG (8)  
H REG (8)  
C REG (8)  
E REG (8)  
L REG (8)  
STACK POINTER (16)  
INSTRUCTION  
DECODER  
ARITHMETIC  
LOGIC  
UNIT  
(ALU) (8)  
PROGRAM COUNTER (16)  
AND MACHINE  
CYCLE  
ENCODING  
INCREMENTER  
DECREMENTER  
ADDRESS LATCH (16)  
VDD  
GND  
POWER  
SUPPLY  
X1  
X2  
CLK  
GEN  
TIMING AND CONTROL  
CONTROL STATUS  
RESET  
ADDRESS  
DATA ADDRESS  
BUFFER (8)  
DMA  
BUFFER (8)  
A15-A8  
ADDRESS  
BUS  
AD1-AD0  
ADDRESS  
BUS  
READY  
WR  
S0  
IO/M  
HLDA  
RESET  
OUT  
CLK  
OUT  
RD  
ALE  
S1  
RESET  
IN  
HOLD  
Spec Number 518054  
2
HS-80C85RH  
Pin Description  
PIN  
SYMBOL  
NUMBER  
TYPE  
DESCRIPTION  
A8 - A15  
21-28  
12-19  
O
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,  
3-stated during Hold and Halt modes and during RESET.  
AD0-7  
ALE  
I/O  
O
Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on  
the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus  
during the second and third clock cycles.  
32  
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the  
address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guar-  
antee setup and hold times for the address information. The falling edge of ALE can also be used  
to strobe the status information. ALE is never 3-stated.  
S0, S1, and  
IO/M  
31, 35,  
& 36  
O
Machine Cycle Status:  
IO/M  
0
S1  
0
S0  
1
Status  
Memory write  
Memory write  
I/O write  
0
1
0
1
0
1
1
1
0
I/O read  
0
1
1
Opcode fetch  
Opcode fetch  
Interrupt acknowledge  
Halt  
1
1
1
1
1
1
T
0
0
T
X
X
X
X
Hold  
T
Reset  
T = 3-State (high impedance)  
X = Unspecified  
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of  
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used  
to latch the state of these lines.  
RD  
WR  
34  
33  
35  
O
O
I
Read Control: A low level on RD indicates the selected memory or I/O device is to be read and  
that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and dur-  
ing RESET.  
Write Control: A low level on WR indicates the data on the Data Bus is to be written into the se-  
lected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and  
Halt modes and during RESET.  
READY  
Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral  
is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock  
cycles for READY to go high before completing the read or write cycle. READY must conform to  
specified setup and hold times.  
HOLD  
HLDA  
39  
38  
I
Hold: Indicates that another master is requesting the use of the address and data buses. The  
cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion  
of the current bus transfer. Internal processing can continue. The processor can regain the bus  
only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD,  
WR, and IO/M lines are 3-stated.  
O
Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relin-  
quish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu  
takes the bus one half clock cycle after HLDA goes low.  
Spec Number 518054  
3
HS-80C85RH  
Pin Description (Continued)  
PIN  
SYMBOL  
NUMBER  
TYPE  
DESCRIPTION  
INTR  
10  
I
Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to  
the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program  
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a  
RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR  
is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is  
accepted.  
INTA  
11  
O
I
Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-  
tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some  
other interrupt port.  
RST 5.5  
RST 6.5  
RST 7.5  
9
8
7
Restart Interrupts: These three inputs have the same timing as INTR except they cause an  
internal RESTART to be automatically inserted.  
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher  
priority than INTR. In addition, they may be individually masked out using the SIM instruction.  
TRAP  
6
I
I
Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as  
INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority  
of any interrupt. (See Table 6.)  
RESET IN  
36  
Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.  
The data and address buses and the control lines are 3-stated during RESET and because of  
the asynchronous nature of RESET the processor’s internal registers and flags may be altered  
by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec-  
tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN  
must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper  
reset operation after the power-up duration, RESET IN should be kept low a minimum of three  
clock periods. The CPU is held in the reset condition as long as RESET IN is applied.  
RESET OUT  
3
O
Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal  
is synchronized to the processor clock and lasts an integral number of clock periods.  
X1  
X2  
1
2
I
O
X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.  
X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to  
give the processor’s internal operating frequency.  
CLK  
SID  
37  
5
O
I
Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input  
period.  
Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM  
instruction is executed.  
SOD  
VCC  
GND  
4
O
I
Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.  
40  
20  
Power: +5V supply.  
Ground: Reference.  
I
RESET IN  
R1  
C1  
VDD  
TYPICAL POWER-ON RESET RC VALUES†  
R1 = 75KΩ  
C1 = 1µF  
† Values may have to vary due to applied power supply ramp up time.  
FIGURE 1. POWER-ON RESET CIRCUIT  
Spec Number 518054  
4
Specifications HS-80C85RH  
Absolute Maximum Ratings  
Reliability Information  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance  
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V SBDIP Package. . . . . . . . . . . . . . . . . . . .  
Ceramic Flatpack Package . . . . . . . . . . .  
θ
θ
JA  
JC  
o
o
45 C/W  
10 C/W  
o
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C  
77 C/W  
13 C/W  
o
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C  
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C  
Maximum Package Power Dissipation at +125 C Ambient  
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W  
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W  
o
Typical Derating Factor. . . . . . . . . . .2.0mA/MHz Increase in IDDOP  
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 If device power exceeds package dissipation capability, provide heat  
sinking or derate linearly at the following rate:  
o
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2mW/ C  
o
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 13.0mW/ C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Operating Conditions  
Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V  
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V  
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD  
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C  
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS  
LIMITS  
MAX  
GROUP A  
SUBGROUPS TEMPERATURE  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
UNITS  
o
o
Input Leakage  
Current  
IIH or  
IIL  
VDD = 5.25V, VI = VDD  
or GND  
1, 2, 3  
-55 C, +25 C, or  
-1.0  
1.0  
µA  
o
+125 C  
o
o
High Level Output  
Voltage  
VOH  
VDD = 4.75V, IOH = -1.0mA  
1, 2, 3  
-55 C, +25 C, or VDD -0.5  
-
V
o
+125 C  
o
o
Low Level Output  
Voltage  
VOL  
VDD = 5.25V, IOL = 1.0mA,  
1, 2, 3  
-55 C, +25 C, or  
-
-
-
-
0.5  
500  
5.0  
-
V
o
+125 C  
o
o
Static Current  
IDDSB  
IDDOP  
FT  
VDD = 5.25V, Clock Out = Hi  
and Low  
1, 2, 3  
-55 C, +25 C, or  
µA  
mA/MHz  
-
o
+125 C  
o
o
Operating Supply  
Current (Note 2)  
VDD = 5.25V, f = 1MHz  
(Note 2)  
1, 2, 3  
-55 C, +25 C, or  
o
+125 C  
o
o
Functional Tests  
VDD = 4.75V and 5.25V,  
TCYC = 500ns,  
7, 8A, 8B  
-55 C, +25 C, or  
o
+125 C  
VOL ≤ VDD/2, VOH ≥ VDD/2  
NOTES:  
1. All devices guaranteed at worst case limits and over radiation.  
2. Operating supply current (IDDOP) is proportional to crystal frequency. Parts are tested at 1MHz  
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS  
GROUP A  
LIMITS  
PARAMETER  
CLK Low Time (Standard CLK Loading)  
CLK High Time (Standard CLK Loading)  
CLK Rise Time  
SYMBOL SUBGROUPS  
TEMPERATURE  
MIN  
MAX  
UNITS  
ns  
o
o
o
T1  
T2  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
40  
100  
-
-
-
o
o
o
-55 C, +25 C, +125 C  
ns  
o
o
o
Tr  
-55 C, +25 C, +125 C  
115  
115  
250  
275  
-
ns  
o
o
o
CLK Fall Time  
Tf  
-55 C, +25 C, +125 C  
-
ns  
o
o
o
X1 Rising to CLK Rising  
TXKR  
TXKF  
TAC  
TACL  
TAD  
TAFR  
-55 C, +25 C, +125 C  
30  
50  
300  
300  
875  
-
ns  
o
o
o
X1 Rising to CLK Falling  
-55 C, +25 C, +125 C  
ns  
o
o
o
A8-15 Valid to Leading Edge of Control (Note 5)  
A0-7 Valid to Leading Edge of Control  
A0-15 Valid to Valid Data In  
-55 C, +25 C, +125 C  
ns  
o
o
o
-55 C, +25 C, +125 C  
-
ns  
o
o
o
-55 C, +25 C, +125 C  
-
ns  
o
o
o
Address Float After Leading Edge of READ  
(INTA)  
-55 C, +25 C, +125 C  
70  
ns  
Spec Number 518054  
5
Specifications HS-80C85RH  
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)  
LIMITS  
GROUP A  
PARAMETER  
SYMBOL SUBGROUPS  
TEMPERATURE  
MIN  
MAX  
UNITS  
ns  
o
o
o
A8-15 Valid Before Trailing Edge of ALE (Note 5)  
A0-7 Valid Before Trailing Edge of ALE  
TAL  
tALL  
9, 10, 11  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
75  
-
-
-
o
o
o
-55 C, +25 C, +125 C  
125  
250  
ns  
o
o
o
READY Valid from Address  
Valid  
TARY  
-55 C, +25 C, +125 C  
ns  
o
o
o
Address (A8-15) Valid After Control  
TCA  
TCC  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
150  
575  
-
-
ns  
ns  
o
o
o
Width of Control Low (RD, WR, INTA) Edge of  
ALE  
-55 C, +25 C, +125 C  
o
o
o
Trailing Edge of Control to Leading Edge of ALE  
Data Valid to Trailing Edge of WRITE  
HLDA to Bus Enable  
TCL  
TDW  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
60  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
o
o
o
-55 C, +25 C, +125 C  
575  
o
o
o
THABE  
THABF  
THACK  
THDH  
THDS  
TINH  
-55 C, +25 C, +125 C  
-
-
375  
375  
-
o
o
o
Bus Float After HLDA  
-55 C, +25 C, +125 C  
o
o
o
HLDA Valid to Trailing Edge of CLK  
HOLD Hold Time  
-55 C, +25 C, +125 C  
90  
-
o
o
o
-55 C, +25 C, +125 C  
0
o
o
o
HOLD Setup Time to Trailing Edge of CLK  
INTR Hold Time  
-55 C, +25 C, +125 C  
-
300  
0
o
o
o
-55 C, +25 C, +125 C  
-
o
o
o
INTR, RST and TRAP Setup Time to Falling  
Edge of CLK  
TINS  
-55 C, +25 C, +125 C  
-
375  
o
o
o
Address Hold Time After ALE  
Trailing Edge of ALE to Leading Edge of Control  
ALE Low During CLK High  
ALE to Valid Data During Read  
ALE to Valid Data During Write  
ALE Width  
TLA  
TLC  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
75  
150  
125  
675  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
o
o
o
-55 C, +25 C, +125 C  
-
o
o
o
TLCK  
TLDR  
TLDW  
TLL  
-55 C, +25 C, +125 C  
-
o
o
o
-55 C, +25 C, +125 C  
-
350  
-
o
o
o
-55 C, +25 C, +125 C  
o
o
o
-55 C, +25 C, +125 C  
200  
-
o
o
o
ALE to READY Stable  
TLRY  
TRAE  
-55 C, +25 C, +125 C  
175  
-
o
o
o
Trailing Edge of READ to Re-Enabling the Ad-  
dress  
-55 C, +25 C, +125 C  
120  
o
o
o
READ (or INTA) to Valid Data  
TRD  
TRV  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
375  
550  
-
-
ns  
ns  
o
o
o
Control Trailing Edge to Leading Edge of Next  
Control  
-55 C, +25 C, +125 C  
o
o
o
Data Hold Time After READ INTA  
READY Hold Time  
TRDH  
TRYH  
TRYS  
TWD  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
9, 10, 11  
-55 C, +25 C, +125 C  
-
-
0
0
ns  
ns  
ns  
ns  
ns  
o
o
o
-55 C, +25 C, +125 C  
o
o
o
READY Setup Time to Leading Edge of CLK  
Data Valid After Trailing Edge of WRITE  
LEADING Edge of WRITE to Data Valid  
NOTES:  
-55 C, +25 C, +125 C  
250  
150  
-
-
o
o
o
-55 C, +25 C, +125 C  
-
o
o
o
TWDL  
-55 C, +25 C, +125 C  
50  
1. Output timings are measured with a purely capacitive load, CL = 150pF  
2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V  
3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.  
4. The AC table is tested as shown above to guarantee the processor system timing.  
5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,  
So, and S1 are stable.  
Spec Number 518054  
6
Specifications HS-80C85RH  
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS  
LIMITS  
(NOTE 1)  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
CONDITIONS  
VDD = Open, f = 1MHz  
VDD = Open, f = 1MHz  
VDD = Open, f = 1MHz  
TEMPERATURE  
MIN  
MAX  
12  
UNITS  
pF  
o
T
= +25 C  
-
-
-
A
o
I/O Capacitance  
Output Capacitance  
NOTE:  
CI/O  
T
= +25 C  
13  
pF  
A
o
COUT  
T
= +25 C  
12  
pF  
A
1. All measurements referenced to device ground.  
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS  
NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.  
o
TABLE 5. BURN-IN DELTA PARAMETERS (+25 C; In Accordance With SMD)  
TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY  
ADDRESS BRANCHED TO (1)  
NAME  
PRIORITY  
WHEN INTERRUPT OCCURS  
TYPE TRIGGER  
TRAP  
RST 7.5  
RST 6.5  
RST 5.5  
INTR  
1
2
3
4
5
24H  
3CH  
Rising edge and high level until sampled.  
Rising edge (latched)  
34CH  
High level until sampled.  
2CH  
High level until sampled.  
See Note 2  
High level until sampled.  
NOTES:  
1. The processor pushes the PC on the stack before branching to the indicated address.  
2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.  
TABLE 7. BUS TIMING SPECIFICATION AS A t  
DEPENDENT  
CYC  
SYMBOL  
tAL  
HS-8OC85RH  
(1/2)T- 175  
SYMBOL  
tCC  
HS-8OC85RH  
Minimum  
Minimum  
Minimum  
Minimum  
Minimum  
Maximum  
Maximum  
Minimum  
Minimum  
Minimum  
Minimum  
(3/2 + N)T - 175  
(1/2)T - 190  
(3/2)T - 500  
(1/2)T - 160  
(1/2)T +125  
(1/2)T +125  
(2/2)T - 200  
(1/2)T-210  
Minimum  
tLA  
(1/2)T- 175  
tCL  
Minimum  
Maximum  
Minimum  
Maximum  
Maximum  
Minimum  
Minimum  
Minimum  
Minimum  
Maximum  
tLL  
(1/2)T-50  
tARY  
tHACK  
tHABF  
tHABE  
tAC  
tLCK  
tLC  
(1/2)T- 125  
(1/2)T- 100  
tAD  
(5/2 + N)T - 375  
(3/2 + N)T - 375  
(1/2)T- 130  
tRD  
tRAE  
tCA  
t1  
(1/2)T - 100  
(3/2 + N)T - 175  
(1/2)T-100  
t2  
(1/2)T- 150  
(3/2)T - 200  
(4/2)T - 325  
tDW  
tWD  
tRV  
tLDR  
NOTE: N is equal to the total WAIT states T = tCYC  
Spec Number 518054  
7
HS-80C85RH  
Waveforms  
X
1 INPUT  
t2  
tr  
tf  
CLK  
OUTPUT  
t1  
tXKR  
tXKF  
tCYC  
FIGURE 2. CLOCK  
T1  
T2  
T3  
T1  
CLK  
tLCK  
tCA  
A8-15  
ADDRESS  
ADDRESS  
tRAE  
tAD  
tRDH  
DATA IN  
AD0-AD7  
tLL  
tLA  
tCL  
tAFR  
tLDR  
tRD  
ALE  
tAL  
tCC  
RD/INTA  
tLC  
tAC  
FIGURE 3. READ  
T1  
T2  
T3  
T1  
CLK  
tLCK  
A8-15  
ADDRESS  
tLDW  
tCA  
DATA OUT  
tWD  
AD0-AD7  
ADDRESS  
tLA  
tLL  
tDW  
ALE  
WR  
tWDL  
tAL  
tCC  
tLC  
tCL  
tAC  
FIGURE 4. WRITE  
Spec Number 518054  
8
HS-80C85RH  
Waveforms (Continued)  
T2  
T2  
THOLD  
THOLD  
T1  
CLK  
HOLD  
tHDS  
tHACK  
tHDH  
HLDA  
BUS  
tHABF  
tHABE  
(ADDRESS, CONTROLS)  
FIGURE 5. HOLD  
T1  
T2  
TWAIT  
T3  
T3  
CLK  
tLCK  
tCA  
A8-15  
ADDRESS  
tRAE  
tAD  
tRDH  
DATA IN  
ADDRESS  
tLA  
AD0-AD7  
tLL  
tCL  
tAFR  
tLDR  
ALE  
tAL  
tRD  
tCC  
tLC  
RD/INTA  
tLRY  
tAC  
tARY  
tRYS tRYH  
tRYS tRYH  
READY  
NOTE 1: READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES.  
FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE  
T1  
T2  
T3  
T4  
T5  
T6  
THOLD T1  
T2  
A8-15  
A0-7  
CALL INST.  
BUS FLOATING†  
RD  
INTR  
tHABE  
INTR  
tINS  
tINH  
HOLD  
tHDH  
tHDS  
HLDA  
tHABF  
tHACK  
† IO/M IS ALSO FLOATING DURING THIS TIME.  
FIGURE 7. INTERRUPT AND HOLD  
Spec Number 518054  
9
HS-80C85RH  
TABLE 9. INSTRUCTION SET SUMMARY  
INSTRUCTION CODE  
MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0  
MOVE, LOAD, AND STORE  
INSTRUCTION CODE  
OPERATIONS  
DESCRIPTION  
OPERATIONS  
DESCRIPTION  
MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0  
RNZ  
RP  
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Return on no zero  
Return on positive  
Return on minus  
MOVr1, r2  
MOV M.r  
MOV r.M  
MVl r  
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
D
D
D
S
S
1
1
1
0
0
0
S
S
1
1
1
0
0
0
S
S
0
0
0
1
1
1
Move register to  
register  
RM  
1
1
0
Move register to  
memory  
RPE  
Return on parity  
even  
D
D
1
D
D
1
D
D
0
Move memory to  
register  
RPO  
1
1
1
1
0
0
0
1
0
1
0
1
Return on parity  
odd  
Move immediate  
register  
RESTART  
RST  
1
A
A
A
Restart  
MVl M  
Move immediate  
memory  
INPUT/OUTPUT  
LXl B  
0
0
0
Load immediate  
register Pair B & C  
IN  
1
1
1
0
0
1
1
1
0
0
0
1
1
1
1
Input  
OUT  
1
Output  
LXl D  
0
1
0
Load immediate  
register Pair D & E  
INCREMENT AND DECREMENT  
LXl H  
1
0
0
Load immediate  
register Pair H & L  
INR r  
0
0
0
0
0
0
0
0
0
0
D
D
1
D
D
1
D
D
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
1
Increment register  
Decrement register  
Increment memory  
Decrement memory  
DCR r  
INR M  
DCR M  
INX B  
STAX B  
STAX D  
LDAX B  
LDAX D  
STA  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
Store A indirect  
Store A indirect  
Load A indirect  
Load A indirect  
Store A direct  
1
1
0
0
0
0
Increment B & C  
registers  
INX D  
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Increment D & E  
registers  
LDA  
Load A direct  
POP B  
POP D  
POP H  
POP PSW  
XTHL  
Pop register Pair B  
& C off stack  
SHLD  
LHLD  
Store H & L direct  
Load H & L direct  
Pop register Pair D  
& E off stack  
XCHG  
Exchange D & E,  
H & L Registers  
Popregister Pair  
H & L off stack  
STACK OPS  
PUSH B  
Pop A and Flags off  
stack  
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Push register Pair  
B & C on stack  
Exchange top ot  
stack, H & L  
PUSH D  
Push register Pair  
D & E on stack  
SPHL  
H & L to stack  
pointer  
PUSH H  
Push register Pair  
H & L on stack  
LXI SP  
INX SP  
DCX SP  
Load immediate  
stack pointer  
PUSH PSW  
Push A and Flags  
on stack  
Increment stack  
pointer  
CZ  
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Call on zero  
CNZ  
CP  
Call on no zero  
Call on positive  
Call on minus  
Decrement stack  
pointer  
CM  
JUMP  
JMP  
JC  
CPE  
CPO  
RETURN  
RET  
RC  
Call on parity even  
Call on parity odd  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Jump unconditional  
Jump on carry  
JNC  
JZ  
Jump on no carry  
Jump on zero  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
Return  
Return on carry  
Return on no carry  
Return on zero  
JNZ  
JP  
Jump on no zero  
Jump on positive  
Jump on minus  
RNC  
RZ  
JM  
Spec Number 518054  
10  
HS-80C85RH  
TABLE 9. INSTRUCTION SET SUMMARY (Continued)  
INSTRUCTION CODE  
INSTRUCTION CODE  
MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0  
OPERATIONS  
DESCRIPTION  
OPERATIONS  
DESCRIPTION  
MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0  
JPE  
1
1
1
0
1
0
1
0
Jump on parity  
even  
ADC M  
1
0
0
0
1
1
1
0
Add memory to A  
with carry  
JPO  
1
1
1
1
1
1
0
0
0
1
0
0
1
0
0
1
Jump on parity odd  
ADl  
ACl  
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
Add immediate to A  
PCHL  
H & L to program  
counter  
Add immediate to A  
with carry  
CALL  
CALL  
CC  
DAD B  
DAD D  
DAD H  
DAD SP  
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Add B & C to H & L  
Add D & E to H & L  
Add H & L to H & L  
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
1
0
0
Call unconditional  
Call on carry  
CNC  
Call on no carry  
Add stack pointer to  
H&L  
LOGICAL  
ANA r  
XRA r  
SUBTRACT  
SUB r  
1
1
0
0
1
1
0
0
0
1
S
S
S
S
S
S
And register with A  
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
S
S
1
1
1
1
S
S
1
1
1
1
S
S
0
0
0
0
Subtract register  
from A  
Exclusive OR  
register with A  
SBB r  
SUB M  
SBB M  
SUl  
Subtract register  
from A with borrow  
ORA r  
CMP r  
1
1
0
0
1
1
1
1
0
1
S
S
S
S
S
S
OR register with A  
Compare register  
with A  
Subtract memory  
from A  
ANA M  
XRA M  
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
And memory with A  
Subtract memory  
from A with borrow  
Exclusive OR mem-  
ory with A  
Subtract immedi-  
ate from A  
ORA M  
CMP M  
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
0
OR memory with A  
SBl  
Subtract immedi-  
ate from A with  
borrow  
Compare memory  
with A  
ANI  
XRI  
ORl  
CPl  
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
And immediate  
with A  
SPECIALS  
CMA  
STC  
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Complement A  
Set carry  
Exclusive OR  
immediate with A  
OR immediate  
with A  
CMC  
DAA  
Complement carry  
Decimal adjust A  
Compare immedi-  
ate with A  
CONTROL  
El  
ROTATE  
RLC  
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
0
0
0
Enable Interrupts  
Disable Interrupt  
No-operation  
Halt  
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
Rotate A left  
DI  
RRC  
Rotate A right  
NOP  
HLT  
RAL  
Rotate A left  
through carry  
RIM  
Read Interrupt  
Mask  
RAR  
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
Rotate A right  
through carry  
SlM  
0
0
1
1
0
0
0
0
Set Interrupt Mask  
INX H  
Increment H & L  
registers  
NOTES:  
1. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111  
DCX B  
DCX D  
DCX H  
ADD  
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
Decrement B & C  
Decrement D & E  
Decrement H & L  
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condi-  
tion flags.  
† All mnemonics copyrighted „ Intel Corporation 1976  
ADD r  
ADC r  
1
1
0
0
0
0
0
0
0
1
S
S
S
S
S
S
Add register to A  
Add register to A  
with carry  
ADD M  
1
0
C
0
0
1
1
0
Add memory to A  
Spec Number 518054  
11  
HS-80C85RH  
enabled or disabled by El or Dl software instructions), and  
Functional Description  
causes the CPU to fetch in an RST instruction, externally  
placed on the data bus, which vectors a branch to any one of  
eight fixed memory locations (Restart addresses). The deci-  
mal addresses of these dedicated locations are: 0, 8, 16,  
24, 32, 40, 48, and 56. Any of these addresses may be used  
to store the first instruction(s) of a routine designed to  
service the requirements of an interrupting device. Since the  
(RST) is a call, completion of the instruction also stores the  
old program counter contents on the STACK. Each of the  
three RESTART inputs, 5.5, 6.5, and 7.5, has a programma-  
ble mask. TRAP is also a RESTART interrupt but it is  
nonmaskable.  
The HS-80C85RH is a complete 8-bit parallel central pro-  
cessing unit implemented in a self aligned, silicon gate,  
CMOS technology. Its static design allows the device to be  
operated at any external clock frequency from a maximum of  
4MHz down to DC. The processor clock can be stopped in  
either the high or low state and held there indefinitely. This  
type of operation is especially useful for system debug or  
power critical applications. The device is designed to fit into  
a minimum system of three ICs: CPU (HS-80C85RH), RAM/  
IO (HS-81C55/56RH) and ROM/IO Chip (HS-83C55RH).  
Since the HS-80C85RH is implemented in CMOS, all of the  
advantages of CMOS technology are inherent in the device.  
These advantages include low standby and operating power,  
high noise immunity, moderately high speed, wide operating  
temperature range, and designed-in radiation hardness.  
Thus the HS-80C85RH is ideal for weapons and space  
applications.  
The three maskable interrupts cause the internal execution  
of RESTART (saving the program counter in the stack and  
branching to the RESTART address) if the interrupts are  
enabled and if the interrupt mask is not set. The non-  
maskable TRAP causes the internal execution of  
a
RESTART vector independent of the state of the interrupt  
enable or masks. (See Table 9.)  
The HS-80C85RH has twelve addressable 8-bit registers.  
Four of them can function only as two 16-bit register pairs.  
Six others can be used interchangeably as 8-bit registers or  
as 16-bit register pairs. The HS-80C85RH register set is as  
follows:  
There are two different types of inputs in the restart  
interrupts. RST 5.5 and RST 6.5 are high level-sensitive and  
are recognized with the same timing as INTR. RST 7.5 is  
rising edge sensitive.  
For RST 7.5, only a pulse is required to set an internal  
flipflop which generates the internal interrupt request (a  
normally high level signal with a low going pulse is recom-  
mended for highest system noise immunity). The RST 7.5  
request flip-flop remains set until the request is serviced.  
Then it is reset automatically. This flip-flop may also be reset  
by using the SlM instruction or by issuing a RESET IN to the  
80C85RH. The RST 7.5 internal flip-flop will be set by a  
pulse on the RST 7.5 pin even when the RST 7.5 interrupt is  
masked out.  
MNEMONIC  
ACC or A  
PC  
REGISTER  
Accumulator  
CONTENTS  
8 -bits  
Program Counter  
16-bit Address  
BC, DE, HL  
General-Purpose  
Registers; Data  
Pointer(HL)  
8-bits x 6 or  
16-bits x 3  
SP  
Stack Pointer  
Flag Register  
16-bit Address  
The status of the three RST interrupt masks can only be  
affected by the SIM instruction and RESET IN.  
Flags or F  
5 Flags (8-bit space)  
The HS-80C85RH uses a multiplexed Data Bus. The The interrupts are arranged in a fixed priority that determines  
address is split between the higher 8-bit Address Bus and which interrupt is to be recognized if more than one is  
the lower 8-bit Address/Data Bus. During the first T state pending as follows: TRAP-highest priority, RST 7.5, RST  
(clock cycle) of a machine cycle the low order address is 6.5, RST 5.5, INTR-lowest priority. This priority scheme does  
sent out on the Address/Data bus. These lower 8 bits may not take into account the priority of a routine that was started  
be latched externally by the Address Latch Enable signal by a higher priority interrupt. RST 5.5 can interrupt an RST  
(ALE). During the rest of the machine cycle the data bus is 7.5 routine if the interrupts are re-enabled before the end of  
used for memory or I/O data.  
the RST 7.5 routine.  
The HS-80C85RH provides RD, WR, S0, S1, and IO/M sig- The TRAP interrupt is useful for catastrophic events such as  
nals for bus control. An Interrupt Acknowledge signal (INTA) power failure or bus error. The TRAP input is recognized just  
is also provided. HOLD and all Interrupts are synchronized as any other interrupt but has the highest priority. It is not  
with the processor’s internal clock. The HS-80C85RH also affected by any flag or mask. The TRAP input is both edge  
provides Serial Input Data (SID) and Serial Output Data and level sensitive. The TRAP input must go high and  
(SOD) lines for simple serial interface.  
remain high until it is acknowledged. It will not be recognized  
again until it goes low, then high again. This avoids any false  
triggering due to noise or logic glitches. Figure 8illustrates  
the TRAP interrupt request circuitry within the HS-80C85RH.  
Note that the servicing of any interrupt (TRAP, RST 7.5, RST  
6.5, RST 5.5, INTR) disables all future interrupts (except  
TRAPs) until an EI instruction is executed.  
In addition to these features, the HS-80C85RH has three  
maskable, vector interrupt pins, one nonmaskable TRAP  
interrupt, and a bus vectored interrupt, INTR.  
Interrupt and Serial I/O  
The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5,  
RST 6.5, RST 7.5, and TRAP INTR is maskable (can be  
Spec Number 518054  
12  
HS-80C85RH  
2. A 10MΩ resistor is required between X1 and X2 for bias point  
INSIDE THE  
80C85RH  
EXTERNAL  
stabilization. In addition, the crystal should have the following  
characteristics:  
TRAP  
INTERRUPT  
REQUEST  
TRAP  
1) Parallel resonance at twice the desired internal clock  
frequency  
TRAP  
RESET IN  
SCHMITT  
TRIGGER  
RESET  
2) CL (load capacitance) ≤ 30pF  
3) CS (shunt capacitance) ≤ 7pF  
4) RS (equivalent shunt resistance) ≤ 75Ω  
5) Drive level: 10mW  
INTERRUPT  
REQUEST  
CLK  
D
VDD  
Q
D
F/F  
CLEAR  
6) Frequency tolerance: ±0.005% (suggested)  
TRAP F.F.  
INTERNAL  
TRAP  
ACKNOWLEDGE  
A parallel-resonant LC circuit may be used as the frequency-  
determining network for the HS-80C85RH, providing that its  
frequency tolerance of approximately ±10% is acceptable.  
The components are chosen from the formula:  
FIGURE 8. TRAP AND RESET IN CIRCUIT  
The TRAP interrupt is special in that is disables interrupts,  
but preserves the previous interrupt enable status. Perform-  
ing the first RIM instruction following a TRAP interrupt allows  
you to determine whether interrupts were enabled or  
disabled prior to the TRAP. All subsequent RIM instructions  
provide current interrupt enable status. Performing a RIM  
instruction following INTR, or RST 5.5-7.5 will provide  
current interrupt enable status, revealing that interrupts are  
disabled.  
1
f =  
2π√ L (Cext + Cint)  
To minimize variations in frequency, it is recommended that  
you choose a value for Cext that is at least twice that of Cint,  
or 30pF. The use of an LC circuit is not recommended for  
frequencies higher than approximately 4MHz.  
An RC circuit may be used as the frequency-determining  
network for the HS-80C85RH if maintaining a precise clock  
frequency is of no importance. Variations in the on-chip tim-  
ing generation can cause a wide variation in frequency when  
using the RC mode. Its advantage is its low component cost.  
The driving frequency generated by the circuit shown is  
approximately 3MHz. It is not recommended that frequen-  
cies greatly higher or lower than this be attempted.  
The serial I/O system is also controlled by the RIM and SIM  
instructions. SID is read by RIM, and SIM sets the SOD  
data.  
Driving the X1 and X2 Inputs  
You may drive the clock inputs of the HS-80C85RH with a  
crystal, an LC tuned circuit, an RC network, or an external  
clock source. The driving frequency may be any value from  
DC to 4MHz and must be twice the desired internal clock  
frequency.  
Figure 9 shows the recommended clock driver circuits.  
For driving frequencies up to and including 4MHz you may  
supply the driving signal to X1 and leave X2 open-circuited  
(Figure 9D).  
The following guidelines should be observed when a crystal  
is used to drive the HS-80C85RH clock input:  
1. A 20pF capacitor should be connected from X2 to ground to  
assure oscillator start-up at the correct frequency.  
80C85RH  
80C85RH  
X1  
X1  
X2  
1
1
2
20pF  
REXT =  
10MΩ  
CINT =  
15pF  
-6K  
2
20pF  
X2  
a.) QUARTZ CRYSTAL CLOCK DRIVER  
c.) RC CIRCUIT CLOCK DRIVER  
LOW TIME > 60ns  
X1  
80C85RH  
X1  
1
CINT =  
15pF  
LEXT  
CEXT  
X2  
2
†
X2  
† X2 Left Floating  
b.) LC TUNED CIRCUIT CLOCK DRIVER  
d.) 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK DRIVER  
CIRCUIT  
FIGURE 9. CLOCK DRIVER CIRCUITS  
Spec Number 518054  
13  
HS-80C85RH  
HS-80C85RH Caveats  
System Interface  
1. An important caveat that is applicable to CMOS devices in gen-  
eral is that unused inputs should never be left floating. This rule  
also applies to inputs connected to a tri- state bus. The need for  
external pull-up resistors during tri-state bus conditions is elimi-  
nated by the presence of regenerative latches on the following  
HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M. Figure  
10 depicts an output and corresponding regenerative latch.  
When the output driver assumes the high impedance state, the  
latch holds the bus in whatever logic state (high or low) it was be-  
fore the tri-state condition. A transient drive current of approxi-  
mately ±1.0mA at 0.5 VDD for 10nsec is required to switch the  
latch. Thus, CMOS device inputs connected to the bus are not  
allowed to float during tri-state conditions.  
The HS-80C85RH family includes memory components,  
which are directly compatible to the HS-8OC8SRH CPU. For  
example, a system consisting of the three radiation-  
hardened chips, HS-80C85RH, HS-81C56RH, and  
HS-83C55RH will have the following features:  
1. 2K Bytes ROM  
2. 256 Bytes RAM  
3. 1 Timer/Counter  
4. 4 8-bit I/O Ports  
5. 1 6-bit I/O Port  
6. 4 Interrupt Levels  
7. Serial In/Serial Out Ports  
2. The RD and WR pins of the HS-80C85RH contain internal dy-  
namic pull-up transistors to avoid spurious selection of memory  
devices when the RD and WR pins assume the high impedance  
state. This eliminates the need for external resistive pull-ups on  
these pins.  
This minimum system, using the standard I/O technique is  
as shown in Figure 12.  
In addition to standard 1/0, the memory mapped I/O offers  
an efficient I/O addressing technique. With this technique, an  
area of memory address space is assigned for I/O address,  
thereby, using the memory address for I/O manipulation.  
Figure 13 shows the system configuration of Memory  
Mapped I/O using HS-80C85RH.  
3. The RESET IN and X1 inputs on the HS-80C85RH are schmit  
trigger inputs. This eliminates the possibility of internal oscilla-  
tions in response to slow rise time input signals at these pins.  
4. A high frequency bypass capacitor of approximately 0.1 µF  
should be connected between VDD and GND to shunt power  
supply transients.  
The HS-80C85RH CPU can also interface with the standard  
radiation-hardened memory that does not have the  
multiplexed address/data bus. It will require use of the  
HS-82C12RH (8-bit latch) as shown in Figure 14.  
5. The HS-80C85RH is functional within 10 input clock cycles after  
application of power (assuming that reset has been asserted  
from power-on). Start up conditions in the crystal controlled  
oscillator mode must also account for the characteristics of the  
oscillator.  
VSS VDD  
OUTPUT  
PIN  
OUTPUT  
DRIVER  
X1  
X2  
RESET IN  
TRAP  
HOLD  
HLDA  
SOD  
SID  
REGENERATIVE  
LATCH  
RST 7.5  
RST 6.5  
RST 5.5  
INTR  
HS-80C85RH  
FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS ADO-AD7,  
A8-A15 AND IO/M.  
S1  
RESET  
OUT  
INTA  
S0  
ADDR/  
ADDR DATA ALE RD WR IO/M  
RDY CLK  
VSS VDD  
Generating An HS-80C85RH Wait State  
(8) (8)  
CE  
PORT  
(8)  
(8)  
(6)  
A
If your system requirements are such that slow memories or  
peripheral devices are being used, the circuit shown in  
Figure 11 may be used to insert one WAIT state in each  
HS-80C85RH machine cycle.  
WR  
RD  
PORT  
B
ALE  
DATA/  
ADDR  
PORT  
C
IN  
TIMER  
OUT  
IO/M  
The D flip-flops should be chosen so that:  
1. CLK is rising edge-triggered  
RESET  
2. CLEAR is low-level active.  
IOW  
RD  
ALE  
The READY line is used to extend the read and write pulse  
lengths so that the 80C85RH can be used with slow mem-  
ory. HOLD causes the CPU to relinquish the bus when it is  
through with it by floating the Address and Data Buses.  
PORT  
A
(8)  
CE  
A0-10  
DATA/  
ADDR  
TO  
PORT  
B
IO/M  
80C85RH  
CLK  
OUTPUT  
(8)  
CLEAR  
80C85RH  
READY  
INPUT  
RESET  
RDY  
CLK  
ALE †  
CLK  
CLK  
D
†
IOR  
VDD  
“D”  
F/F  
“D”  
F/F  
Q
Q
VDD  
D
VSS VDD  
VDD  
†ALE and CLK (OUT) should be buffered if CLK  
input of latch exceeds 80C85RH IOL or IOH.  
† Optional Connection  
FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O  
TECHNIQUE)  
FIGURE11. GENERATIONOFAWAITSTATEFORHS-80C85RH  
CPU.  
Spec Number 518054  
14  
HS-80C85RH  
A8-15  
AD0-7  
ALE  
RD  
HS-80C85RH  
WR  
IO/M  
CLK  
RESET OUT  
READY  
VDD  
TIMER OUT  
HS-81C56RH  
(RAM + I/O + COUNTER/TIMER)  
HS-83C55RH  
(ROM +I/O)  
(6)  
(8)  
(8)  
(8)  
(8)  
† Optional Connection  
FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O)  
VSS VDD  
X1  
X2  
RESET IN  
TRAP  
HOLD  
HLDA  
SOD  
SID  
RST 7.5  
RST 6.5  
RST 5.5  
INTR  
HS-80C85RH  
S1  
RESET  
OUT  
RDY CLK  
INTA  
ADDR  
S0  
ADDR/  
DATA ALE RD WR IO/M  
(8)  
(8)  
IO/M (CS)  
WR  
RD  
STANDARD  
MEMORY  
HS-82C12RH  
DATA  
ADDR (CS)  
CLK  
RESET  
I/O PORTS,  
CONTROLS  
IO/M (CS)  
(16)  
WR  
RD  
DATA  
STANDARD  
I/O  
ADDR  
VDD  
VDD  
VDD  
FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES)  
Spec Number 518054  
15  
HS-80C85RH  
Basic System Timing  
A machine cycle normally consists of three T states, with the  
exception of OPCODE FETCH, which normally has either  
four or six T states (unless WAIT or HOLD states are forced  
by the receipt of READY or HOLD inputs). Any T state must  
be one of ten possible states, shown in Table 11.  
The HS-80C85RH has a multiplexed Data Bus. ALE is used  
as a strobe to sample the lower 8-bits of address on the  
Data Bus. Figure 15 shows an instruction fetch, memory  
read and I/O write cycle (as would occur during processing  
of the OUT instruction). Note that during the I/O write and  
read cycle that the I/O port address is copied on both the  
upper and lower half of the address.  
TABLE 11. HS-80C85RH MACHINE STATE CHART  
MA-  
CHINE  
STATUS & BUSES  
CONTROL  
There are seven possible types of machine cycles. Which of  
these seven takes place is defined by the status of the three  
status lines (lO/M, S1, S0) and the three control signals (RD,  
WR, and INTA). (See Table 10.) The status lines can be  
used as advanced controls (for device selection, for exam-  
ple), since they become active at the T1 state, at the outset  
of each machine cycle. Control lines RD and WR are used  
as command lines since they become active when the trans-  
fer of data is to take place.  
STATE S1, S0 IO/M A8-15 AD0-7 RD,WR INTA ALE  
T1  
X
X
X
X
1
X
X
X
X
X
X
1
X
1
X
X
X
1
1
1
1
1
1
1†  
0
T2  
TWAIT  
T3  
X
X
X
X
0
X
X
X
X
0
T4  
0††  
0††  
0††  
TS  
TS  
TS  
X
TS  
TS  
TS  
TS  
TS  
TS  
1
0
T5  
1
X
1
0
TABLE 10. HS-80C85RH MACHINE CYCLE CHART  
T6  
1
X
1
0
STATUS  
CONTROL  
TRESET  
THALT  
THOLD  
X
0
TS  
TS  
TS  
TS  
TS  
TS  
0
MACHINE CYCLE  
Opcode Fetch (OF)  
IO/M S1 S0 RD WR INTA  
0
0
0
0
1
1
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
0
X
0
Memory Read (MR)  
Memory Write (MW)  
0 = Logic “0”  
1 = Logic “1”  
TS = High Impedance  
X = Unspecified  
I/O Read  
I/O Write  
(IOR)  
(IOW)  
† ALE not generated during 2nd and 3rd machine cycles of DAD  
instruction.  
†† IO/M = 1 during T4, T6 of INA machine cycle.  
Acknowledge (INA)  
of INTR  
Bus Idle  
(BI)  
DAD  
Ack. of  
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
RST,  
TRAP  
HALT  
TS  
TS TS  
M1  
T3  
M2  
T2  
M3  
T2  
T1  
T2  
T4  
T1  
T3  
T1  
T3  
T
CLK  
A8-A15  
PCH (HIGH ORDER ADDRESS)  
(PC + 1)H  
IO PORT  
PCL  
(PC+1)L  
IO PORT  
AD0-7  
ALE  
(LOW ORDER DATA FROM  
ADDRESS)  
DATA TO  
DATA FROM  
MEMORY (I/O  
PORT ADDRESS)  
MEMORY  
MEMORY OR  
PERIPHERAL  
(INSTRUCTION)  
RD  
WR  
IO/M  
STATUS  
S1-S0 (FETCH)  
10 (READ)  
01 WRITE  
11  
FIGURE 15. 80C85RH BASIC SYSTEM TIMING  
Spec Number 518054  
16  
HS-80C85RH  
Metallization Topology  
DIE DIMENSIONS:  
229 mils x 240 mils x 14 mils ±1 mil  
METALLIZATION:  
Type: SiAl  
Thickness: 11kÅ ±2kÅ  
GLASSIVATION:  
Type: SiO2  
Thickness: 8kÅ ±1kÅ  
Metallization Mask Layout  
HS-80C85RH  
TRAP (6)  
RST 7.5 (7)  
RST 6.5 (8)  
RST 5.5 (9)  
(35) READY  
(34) IO/M  
(33) S1  
(32) RD  
INTR (10)  
INTA (11)  
(31) WR  
(30) ALE  
AD0 (12)  
(29) S0  
(28) A15  
AD1 (13)  
AD2 (14)  
(27) A14  
(26) A13  
(25) A12  
AD3 (15)  
AD4 (16)  
Spec Number 518054  
17  
HS-80C85RH  
Packaging  
K42.A TOP BRAZED  
E
N
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
INCHES MILLIMETERS  
MIN  
1
A
A
e
SYMBOL  
MAX  
0.100  
0.025  
0.023  
0.013  
0.010  
1.075  
0.650  
0.680  
0.550  
MIN  
-
MAX  
2.54  
NOTES  
D
A
b
-
-
-
b
0.017  
0.017  
0.007  
0.007  
1.045  
0.630  
-
0.43  
0.43  
0.18  
0.18  
26.54  
16.00  
-
0.64  
E1  
b1  
c
0.58  
-
S1  
C
0.33  
-
L
c1  
D
0.25  
-
A
Q
27.31  
16.51  
17.27  
13.97  
3
-
E2  
E
E1  
E2  
e
3
-
c1  
LEAD FINISH  
0.530  
13.46  
0.050 BSC  
1.27 BSC  
11  
-
BASE  
METAL  
(c)  
k
-
-
-
8.13  
1.14  
0.00  
-
-
8.89  
1.65  
-
b1  
M
L
0.320  
0.045  
0.000  
-
0.350  
0.065  
-
-
M
Q
S1  
M
N
8
6
-
(b)  
SECTION A-A  
NOTES:  
0.0015  
0.04  
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark. Alternately, a tab (dimension k)  
may be used to identify pin one.  
42  
42  
-
Rev. 0 6/17/94  
2. If a pin one identification mark is used in addition to a tab, the lim-  
its of dimension k do not apply.  
3. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
4. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness. The maximum lim-  
its of lead dimensions b and c or M shall be measured at the cen-  
troid of the finished lead surfaces, when solder dip or tin plate  
lead finish is applied.  
5. N is the maximum number of terminal positions.  
6. Measure dimension S1 at all four corners.  
7. For bottom-brazed lead packages, no organic or polymeric mate-  
rials shall be molded to the bottom of the package to cover the  
leads.  
8. Dimension Q shall be measured at the point of exit (beyond the  
meniscus) of the lead from the body. Dimension Q minimum  
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-  
der dip lead finish is applied.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
11. The basic lead spacing is 0.050 inch (1.27mm) between center  
lines. Each lead centerline shall be located within ±0.005 inch  
(0.13mm) of its exact longitudinal position relative to lead 1 and  
the highest numbered (N) lead.  
Spec Number 518054  
18  
HS-80C85RH  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
Taiwan Limited  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
Spec Number  
19  

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