HUF76105DK8T [INTERSIL]
TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | 30V V(BR)DSS | 5A I(D) | SO ; 晶体管| MOSFET |对匹配的| N沟道| 30V V（ BR ） DSS | 5A I（ D） | SO\n
| 型号： | HUF76105DK8T |
| 厂家： | 
Intersil |
| 描述： | TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | 30V V(BR)DSS | 5A I(D) | SO
|
| 文件： | 总12页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76105DK8
TM
Data Sheet
June 2000
File Number 4380.6
5A, 30V, 0.050 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
Features
• Logic Level Gate Drive
• 5A, 30V
This N-Channel power MOSFET is
®
manufactured using the innovative
• Ultra Low On-Resistance, r
= 0.050Ω
UltraFET™ process. This advanced
process technology achieves the
DS(ON)
®
• Temperature Compensating PSPICE Model
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery
operated products.
©
• Temperature Compensating SABER Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA76105.
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
76105DK8
D1(8)
D1(7)
HUF76105DK8
MS-012AA
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76105DK8T.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation.
1
PSPICE® is a registered trademark of MicroSim Corporation. SABER™ is a trademark of Analogy, Inc.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HUF76105DK8
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
HUF76105DK8
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±16
GS
Drain Current
o
Continuous (T = 25 C, V
= 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . I
5
1.4
1.3
A
A
A
A
GS
D
D
o
Continuous (T = 100 C, V
= 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
GS
o
Continuous (T = 100 C, V
A
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Figures 6, 17, 18
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
0.02
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
2. 50 C/W measured using FR-4 board at 1 second.
o
2
3. 228 C/W measured using FR-4 board with 0.006 in of copper at 1000 seconds.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
= 250µA, V
= 0V (Figure 12)
30
-
-
-
-
-
-
V
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
= ±16V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
DS
1
-
-
3
V
Ω
Ω
Ω
GS(TH)
GS
D
r
I
I
I
= 5A, V
= 10V (Figures 9, 10)
GS
0.040
0.055
0.060
0.050
0.072
0.078
DS(ON)
D
D
D
= 1.4A, V
= 1.3A, V
= 5V (Figure 9)
-
GS
GS
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
2
o
Thermal Resistance Junction to Ambient
R
Pad Area = 0.76 in (Note 2)
-
-
-
-
-
-
50
C/W
θJA
2
o
Pad Area = 0.027 in (See TB377)
191
228
C/W
2
o
Pad Area = 0.006 in (See TB377)
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
R
R
= 15V, I
D
1.3A,
= 4.5V,
-
-
-
-
-
-
-
60
-
ns
ns
ns
ns
ns
ns
ON
DD
= 11.5Ω, V
L
GS
Turn-On Delay Time
Rise Time
t
12
28
31
21
-
d(ON)
= 27Ω
GS
(Figure 15)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
80
OFF
2
HUF76105DK8
o
Electrical Specifications T = 25 C, Unless Otherwise Specified (Continued)
A
PARAMETER
SWITCHING SPECIFICATIONS (V
Turn-On Time
SYMBOL
= 10V)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
GS
t
V
R
R
= 15V, I
5A,
-
-
-
-
-
-
-
60
ns
ns
ns
ns
ns
ns
ON
DD
D
= 3Ω, V
= 10V,
L
GS
Turn-On Delay Time
Rise Time
t
17
21
60
20
-
-
d(ON)
= 27Ω
GS
(Figure 16)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
120
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
R
= 15V, I
D
= 10.7Ω
1.4A,
-
-
-
-
-
9
11
6.4
0.45
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
L
Gate Charge at 5V
Q
5.3
g(5)
I
= 1.0mA
g(REF)
(Figure 14)
Threshold Gate Charge
Q
0.35
1.00
2.40
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V = 0V,
GS
-
-
-
325
180
35
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
C
OSS
RSS
Reverse Transfer Capacitance
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
39
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
= 5A
-
-
SD
SD
SD
SD
SD
= 1.4A
V
Reverse Recovery Time
t
= 1.4A, dI /dt = 100A/µs
SD
-
-
-
-
ns
rr
Reverse Recovered Charge
Q
= 1.4A, dI /dt = 100A/µs
42
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
6
5
4
3
2
1
0
o
V
= 10V, R
= 50 C/W
GS
JA
θ
o
V
= 4.5V, R
50
= 228 C/W
GS
JA
θ
25
75
100
125
o
150
0
25
50
75
100
125
150
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
HUF76105DK8
Typical Performance Curves (Continued)
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
o
R
= 228 C/W
JA
θ
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
DM
JA
θ
θ
-5
-4
10
-3
-2
10
-1
10
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
o
T = 25 C
A
o
R
= 228 C/W
JA
θ
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
100
10
1
150 - T
A
I = I
25
125
V
GS
= 5V
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
-3
-2
-1
10
0
10
1
2
10
3
10
10
10
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
20
200
100
T
= MAX RATED
= 25 C
J
o
T
A
o
STARTING T = 25 C
J
10
100µs
10
1
1ms
o
STARTING T = 150 C
J
10ms
If R = 0
AV
If R ≠ 0
OPERATION IN THIS
AREA MAY BE
t
= (L)(I )/(1.3*RATED BV
- V )
DD
AS
DSS
LIMITED BY r
DS(ON)
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
AS
V
= 30V
DSS(MAX)
10
1
0.1
0.01
0.1
1
10
1
100
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
AV
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
4
HUF76105DK8
Typical Performance Curves (Continued)
25
25
PULSE DURATION = 80µs
o
V
= 10V
= 5V
-55 C
GS
DUTY CYCLE = 0.5% MAX
o
25 C
V
GS
V
= 15V
DD
20
15
10
5
20
15
10
5
o
150 C
V
= 4V
GS
V
= 3.5V
GS
V
= 3V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
A
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
110
90
70
50
30
1.8
PULSE DURATION = 80µs
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
I
= 5A
DUTY CYCLE = 0.5% MAX
D
V
= 10V, I = 5A
D
GS
1.6
1.4
1.2
1.0
0.8
0.6
I
= 1.4A
D
2
4
6
8
10
-80
-40
0
40
80
120
160
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.15
V
= V , I = 250µA
I
= 250µA
GS
DS
D
D
1.1
1.0
0.9
0.8
0.7
1.1
1.05
1.0
0.95
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
5
HUF76105DK8
Typical Performance Curves (Continued)
10
600
V
= 15V
V
= 0V, f = 1MHz
DD
GS
ISS
C
C
C
= C
+ C
GS
= C
GD
500
400
300
200
100
0
RSS
OSS
GD
= C
8
+ C
DS
GD
C
C
6
4
2
0
ISS
OSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 5A
= 1.4A
D
D
C
RSS
0
2
4
6
8
10
0
5
10
15
20
25
30
Q , GATE CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
g
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
60
120
V
= 10V, V
DD
= 15V, I = 5A, R = 3Ω
V
= 4.5V, V
DD
= 15V, I = 1.3A, R = 11.5Ω
t
GS
D
L
GS
D
L
d(OFF)
t
d(OFF)
45
30
15
0
90
60
30
0
t
r
t
f
t
r
t
d(ON)
t
d(ON)
t
f
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORM
6
HUF76105DK8
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORMS
2. The number of copper layers and the thickness of the board
3. The use of external heat sinks
Thermal Resistance vs. Mounting Pad
Area
4. The use of thermal vias
The maximum rated junction temperature, T , and the
JM
5. Air flow and board orientation
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P , in an
6. For non-steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in
DM
application. Therefore the application’s ambient temperature,
o
o
T ( C), and thermal resistance R
( C/W) must be
A
θJA
reviewed to ensure that T is never exceeded. Equation 1
Intersil provides thermal information to assist the designer’s
JM
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
preliminary application evaluation. Figure 23 defines the R
θJA
for the device as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board with 1oz
copper after 1000 seconds of steady state power with no air
flow. This graph provides the necessary information for
calculation of the steady state junction temperature or power
dissipation. Pulse applications can be evaluated using the
Intersil device Spice thermal model or manually utilizing the
normalized maximum transient thermal impedance curve.
(T
– T )
JM
Z
A
(EQ. 1)
P
= ------------------------------
DM
θJA
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
Displayed on the curve are R
θJA
values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board
resistance and ultimately the power dissipation, P
.
DM
7
HUF76105DK8
o
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
R
= R
= 159 C/W
θJA1
θJA2
o
Rθβ1 = Rθβ2 = 97 C/W
Equation 2. R
is defined as the natural log of the area
θJA
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
T
and T define the junction temperature of the respective
J2
J1
die. Similarly, P and P define the power dissipated in each
1
2
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
R
= 103.2 – 24.3 × ln(Area)
(EQ. 2)
θJA
Example: Use Equation 4 to calculate T and Equation 5 to
J1
calculate T with the following conditions. Die 2 is
J2
300
dissipating 0.5 Watts; die 1 is dissipating 0 Watts; the
ambient temperature is 70 C; the package is mounted to a
top copper area of 0.1 square inches per die.
R
= 103.2 - 24.3 * ln(AREA)
o
θJA
250
o
2
228 C/W - 0.006in
T
= P R
+ P Rθβ + T
(EQ. 4)
o
2
200
150
100
50
J1
1
θJA
2
A
191 C/W - 0.027in
o
o
o
T
T
= (0 Watts)(159 C/W) + (0.5 Watts)(97 C/W) + 70 C
J1
J1
o
= 119 C
T
= P R
+ P Rθβ + T
(EQ. 5)
o
J2
2
θJA
1
A
Rθβ = 46.4 - 21.7 * ln(AREA)
0
o
o
T
T
= (0.5 Watts)(159 C/W) + (0 Watts)(97 C/W) + 70 C
J2
J2
0.001
0.01
0.1
2
1
o
AREA, TOP COPPER AREA (in ) PER DIE
= 150 C
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
The transient thermal impedance (Z
θJA
) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. SPICE and SABER thermal models are provided for
each of the listed pad areas.
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFETs are offered with two
die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
Rθβ = 46.4 – 21.7 × ln(Area)
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (R
) and thermal coupling resistance
θJA
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
2
0.140 in
2
2
2
120
80
40
0
0.257 in
0.380 in
0.493 in
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
8
HUF76105DK8
rtherm.rtherm8 2 tl = 48
}
SPICE Thermal Model
REV June 1998
JUNCTION
th
HUF76105DK8
2
Copper Area = 0.02 in
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
8
7
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
6
5
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
SABER Thermal Model
2
Copper Area = 0.02 in
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONENT
CTHERM6
0.02 in
0.14 in
1.3e-1
6.0e-1
2.5
0.257 in
0.38 in
0.493 in
1.5e-1
7.5e-1
3
9.0e-2
4.0e-1
1.4
1.5e-1
4.5e-1
2.2
1.5e-1
6.5e-1
3
CTHERM7
CTHERM8
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
9
HUF76105DK8
PSPICE Electrical Model
.SUBCKT HUF76105 2 1 3 ;
REV June 1998
CA 12 8 4.95e-10
CB 15 14 5.15e-10
CIN 6 8 2.9e-10
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
EBREAK 11 7 17 18 33.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
+
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
EVTHRES
+
16
21
+
-
19
MWEAK
LGATE
EVTEMP
+
8
RGATE
GATE
1
6
-
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 9.2e-10
LSOURCE 3 7 3.2e-10
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e-3
RGATE 9 20 3.39
RLDRAIN 2 5 10
RLGATE 1 9 9.2
RLSOURCE 3 7 3.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 22e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),6))}
.MODEL DBODYMOD D (IS = 3.01e-13 IKF = 20 RS = 1.47e-2 TRS1 = -1.7e-3 TRS2 = 4e-5 CJO = 5.74e-10 TT = 2.88e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 3.94e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 2.55e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 1.92 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.26 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.7 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 8e-3 TC2 = 5.3e-5)
.MODEL RSLCMOD RES (TC1 = 1.e-3 TC2 = -1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.87e-3 TC2 = -1.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
10
HUF76105DK8
SABER Electrical Model
REV June
1998
template huf76105 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.01e-13, cjo = 5.74e-10, tt = 2.88e-8, xti = 4.5, m = 0.43)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.55e-10, is = 1e-30, n = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 1.92, kp = 2.1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.26, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.7, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
c.ca n12 n8 = 4.95e-10
c.cb n15 n14 = 5.15e-10
c.cin n6 n8 = 2.9e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 9.2e-10
l.lsource n3 n7 = 3.2e-10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.94e-4, tc2 = 9.84e-8
res.rdbody n71 n5 = 1.47e-2, tc1 = -1.7e-3, tc2 = 4e-5
res.rdbreak n72 n5 = 3.94e-1, tc1 = 9.94e-4, tc2 = 9.12e-7
res.rdrain n50 n16 = 9e-3, tc1 = 8e-3, tc2 = 5.3e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 9.2
res.rlsource n3 n7 = 3.2
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 22e-3, tc1 = 1e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -1.87e-3, tc2 = -1.2e-6
spe.ebreak n11 n7 n17 n18 = 33.87
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 6))
}
}
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
11
HUF76105DK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E
A
INCHES
MILLIMETERS
A
1
1
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
NOTES
A
0.0532
0.004
0.0688
0.0098
0.020
-
-
e
A
1
b
0.013
-
D
c
D
E
0.0075
0.189
0.0098
0.1968
0.244
-
2
-
b
0.2284
0.1497
E
0.1574
3
-
1
e
0.050 BSC
1.27 BSC
o
h x 45
H
L
0.0099
0.016
0.0196
0.050
0.25
0.40
0.50
1.27
-
4
c
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
0.004 IN
0.10 mm
L
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
o
o
0 -8
0.060
1.52
3. Dimension “E ” does not include inter-lead flash or protrusions.
1
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
0.050
1.27
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
0.024
0.6
0.155
4.0
0.275
7.0
4.0mm
USER DIRECTION OF FEED
1.5mm
DIA. HOLE
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
2.0mm
1.75mm
C
L
MS-012AA
12mm TAPE AND REEL
12mm
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
13mm
COVER TAPE
330mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
12.4mm
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
12
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