HUF76107D3S [FAIRCHILD]
20A, 30V, 0.052 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs; 20A ， 30V ， 0.052 Ohm的N通道，逻辑电平UltraFET功率MOSFET
| 型号： | HUF76107D3S |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 20A, 30V, 0.052 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs |
| 文件： | 总11页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76107D3, HUF76107D3S
Data Sheet
January 2003
20A, 30V, 0.052 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
Features
• Logic Level Gate Drive
• 20A, 30V
These N-Channel power
MOSFETs are manufactured using
• Ultra Low On-Resistance, r
= 0.052Ω
the innovative UltraFET™ process.
DS(ON)
®
This advanced process technology
• Temperature Compensating PSPICE Model
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications
where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay
drivers, low voltage bus switches, and power management
in portable and battery operated products.
©
• Temperature Compensating SABER Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA76107.
Ordering Information
Symbol
PART NUMBER
PACKAGE
TO-251AA
TO-252AA
BRAND
76107D
76107D
D
HUF76107D3
HUF76107D3S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76107D3ST.
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
DRAIN
(FLANGE)
DRAIN
GATE
GATE
(FLANGE)
SOURCE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
o
Continuous (T = 25 C, V
C
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
20
10.5
10
A
A
A
GS
D
D
o
Continuous (T = 100 C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
C
GS
o
Continuous (T = 100 C, V
C
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Figure 6
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
0.30
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
= 250µA, V
= 0V (Figure 12)
30
-
-
-
-
-
-
V
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
= ±20V
= 0V
1
µA
µA
nA
DSS
DS
DS
GS
o
= 0V, T = 150 C
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
GS(TH)
GS
DS
D
r
I
I
I
= 20A, V
= 10V (Figure 9, 10)
0.042
0.058
0.065
0.052
0.080
0.085
Ω
Ω
Ω
DS(ON)
D
D
D
GS
= 10.5A, V
= 5V (Figure 9)
-
GS
= 10A, V
GS
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-251, TO-252
-
-
-
-
3.3
C/W
θJC
o
100
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 15V, I
= 4.5V, R
10A, R = 1.50Ω,
-
-
-
-
-
-
-
120
ns
ns
ns
ns
ns
ns
ON
DD
D
L
= 33Ω
GS
GS
Turn-On Delay Time
Rise Time
t
14
66
16
22
-
-
-
d(ON)
(Figure 15)
t
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
57
OFF
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
o
Electrical Specifications T = 25 C, Unless Otherwise Specified (Continued)
A
PARAMETER
SWITCHING SPECIFICATIONS (V
Turn-On Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
= 10V)
GS
t
V
V
= 15V, I
20A, R =0.75Ω,
-
-
-
-
-
-
-
75
ns
ns
ns
ns
ns
ns
ON
DD
D
L
= 10V, R
= 33Ω
GS
GS
Turn-On Delay Time
Rise Time
t
18
30
62
20
-
-
d(ON)
(Figures 16)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
125
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 15V,I
D
10.5A,
-
-
-
-
-
8.6
4.7
10.3
5.7
0.42
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
R = 1.43Ω
L
Gate Charge at 5V
Q
g(5)
I
= 1.0mA
g(REF)
(Figure 14)
Threshold Gate Charge
Q
0.35
1.00
2.40
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V
GS
= 0V, f = 1MHz
-
-
-
315
170
30
-
-
-
pF
pF
pF
ISS
DS
(Figure 13)
Output Capacitance
C
C
OSS
Reverse Transfer Capacitance
RSS
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= 10.5A
MIN
TYP
MAX
1.25
39
UNITS
V
V
I
I
I
-
-
-
-
-
-
SD
SD
SD
SD
t
= 10.5A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 10.5A, dI /dt = 100A/µs
SD
49
nC
RR
Typical Performance Curves Unless otherwise specified
1.2
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5
V
= 10V
GS
V
= 4.5V
GS
0
0
25
50
75
100
125
150
25
50
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
A
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P
DM
x Z
x R
+ T
JC C
J
JC
θ
θ
-5
-4
-3
10
-2
10
-1
10
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
100
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
V
= 10V
C
I = I
25
GS
125
V
= 5V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
-4
-3
10
-2
10
-1
10
0
1
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
200
200
100
If R = 0
= (L)(I )/(1.3*RATED BV
T
= MAX RATED
= 25 C
J
t
- V
)
DD
o
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
T
C
100
t
- V ) +1]
DD
AV
AS DSS
100µs
o
STARTING T = 25 C
J
10
10
o
STARTING T = 150 C
J
1ms
OPERATION IN THIS
AREA MAY BE
10ms
LIMITED BY r
V
= 30V
DSS(MAX)
10
DS(ON)
1
0.001
1
0.01
0.1
1
10
100
1
100
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
30
25
20
15
10
5
30
25
20
15
10
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
o
V
= 10V
-55 C
GS
o
DUTY CYCLE = 0.5% MAX
150 C
o
V
= 5V
V
= 15V
GS
T
= 25 C
DD
C
o
25 C
V
= 4.5V
GS
V
= 4V
GS
V
= 3.5V
GS
V
= 3V
5
GS
0
0
0
1
2
3
4
6
0
3
5
1
2
6
4
V
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
90
80
70
60
50
40
30
2.00
1.75
1.50
1.25
1.00
0.75
0.50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
= 20A
D
V
= 10V, I = 20A
GS
D
I
= 12A
D
I
= 5A
D
-60
0
60
120
o
180
2
4
6
8
10
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.15
1.2
V
= V , I = 250µA
DS D
I = 250µA
D
GS
1.1
1.0
0.9
0.8
0.7
0.6
1.10
1.05
1.00
0.95
0.90
-60
0
60
120
o
180
-60
0
60
120
o
180
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
10
8
600
500
400
300
200
100
0
V
= 0V, f = 1MHz
V
= 15V
DD
GS
ISS
C
C
C
= C
+ C
GS
= C
GD
RSS
OSS
GD
≈
C
+ C
DS
GD
6
C
ISS
4
C
WAVEFORMS IN
DESCENDING ORDER:
OSS
I
I
I
= 20A
= 12A
= 5A
2
D
D
D
C
RSS
0
4
0
2
8
10
6
0
5
15
25
30
10
20
Q , GATE CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
g
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100
100
V
= 4.5V, V
= 15V, I = 10A, R = 1.50Ω
DD D L
V
= 10V, V = 15V, I = 20A, R = 0.75Ω
DD D L
GS
GS
t
t
80
60
40
20
0
d(OFF)
80
60
40
20
0
r
t
r
t
f
t
f
t
d(OFF)
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
PSPICE Electrical Model
SUBCKT HUF76107 2 1 3 ;
REV June 1998
CA 12 8 4.2e-10
CB 15 14 4.9e-10
CIN 6 8 2.85e-10
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
11
-
50
EBREAK 11 7 17 18 35.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
-
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 3.61e-9
LSOURCE 3 7 3.61e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-3
RGATE 9 20 3.39
RLDRAIN 2 5 10
RLGATE 1 9 36.1
RLSOURCE 3 7 36.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RVTEMP
19
S1B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RSOURCE 8 7 RSOURCEMOD 30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),7))}
.MODEL DBODYMOD D (IS = 2.8e-13 IKF = 5 RS = 1.37e-2 TRS1 = 2e-4 TRS2 = 2e-6 CJO = 4.9e-10 TT = 2.88e-8 M = 3.9e-1 XTI =4.75 )
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 3.2e-10 IS = 1e-30 N = 10 M = 7.4e-1)
.MODEL MMEDMOD NMOS (VTO = 2.07 KP = 1.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.4 KP = 19.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.8 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS=.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 3.9e-2 TC2 = 5.5e-5)
.MODEL RSLCMOD RES (TC1 = 1e-4 TC2 = 3.2e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-12 TC2 = 6e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -5.96e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.4e-3 TC2 = 1e-10)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.2 VOFF= -0.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= -4.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= 0.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.0 VOFF= -0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
SABER Electrical Model
nom temp=25 deg c 30v LL Ultrafet
REV Junel 1998
template huf76107 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=2.8e-13, xti=4.75, cjo=4.9e-10,tt=2.88e-8, m=3.9e-1)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=3.2e-10,is=1e-30,n=10,m=7.4e-1)
m..model mmedmod = (type=_n,vto=2.07,kp=1.25,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=19.5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.8,kp=1e-1,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.2,voff=-0.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-4.2)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.0,voff=-0.8)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
c.ca n12 n8 = 4.2e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 2.85e-10
50
-
71
RDRAIN
6
8
ESG
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
EVTHRES
+
+
16
21
-
19
8
MWEAK
d.dplcap n10 n5 = model=dplcapmod
LGATE
EVTEMP
DBODY
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
MMED
i.it n8 n17 = 1
9
20
MSTRO
8
17
18
-
RLGATE
l.ldrain n2 n5 = 1e-9
LSOURCE
l.lgate n1 n9 = 3.61e-9
l.lsource n3 n7 = 3.61e-9
CIN
SOURCE
3
7
RSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RLSOURCE
S1A
S2A
14
13
S2B
RBREAK
12
15
13
17
18
8
res.rbreak n17 n18 = 1, tc1=9.94e-4,tc2=-9.84e-8
res.rdbody n71 n5 =1.37e-2, tc1=2e-4, tc2=2e-6
res.rdbreak n72 n5 =2.5e-1, tc1=9.94e-4, tc2=9.12e-7
res.rdrain n50 n16 = 3.7e-3, tc1=3.9e-2,tc2=5.5e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 36.1
res.rlsource n3 n7 = 36.1
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=3.2e-6
res.rslc2 n5 n50 = 1e3
RVTEMP
19
S1B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rsource n8 n7 = 30e-3, tc1=1e-12,tc2=6e-6
res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-10
res.rvthres n22 n8 = 1, tc1=-1.9e-3,tc2=-5.96e-6
spe.ebreak n11 n7 n17 n18 = 35.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/50))**7 ))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
HUF76107D3, HUF76107D3S
SPICE Thermal Model
JUNCTION
th
REV June1998
HUF76107
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 5.0e-5
CTHERM2 6 5 9.0e-4
CTHERM3 5 4 1.3e-3
CTHERM4 4 3 1.3e-3
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 7.9e-3
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 2.0e-4
RTHERM2 6 5 6.0e-3
RTHERM3 5 4 3.5e-2
RTHERM4 4 3 8.5e-1
RTHERM5 3 2 5.1e-1
RTHERM6 2 tl 1
5
SABER Thermal Model
SABER thermal model HUF76107
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-5
ctherm.ctherm2 6 5 = 9.0e-4
ctherm.ctherm3 5 4 = 1.3e-3
ctherm.ctherm4 4 3 = 1.3e-3
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 7.9e-3
rtherm.rtherm1 th 6 = 2.0e-4
rtherm.rtherm2 6 5 = 6.0e-3
rtherm.rtherm3 5 4 = 3.5e-2
rtherm.rtherm4 4 3 = 8.5e-1
rtherm.rtherm5 3 2 = 5.1e-1
rtherm.rtherm6 2 tl = 1
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
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First Production
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Rev. I2
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