HUF76105SK8 [INTERSIL]
5.5A, 30V, 0.050 Ohm, N-Channel, Logic Level UltraFET Power MOSFET; 5.5A , 30V , 0.050 Ohm的N通道,逻辑电平UltraFET功率MOSFET型号: | HUF76105SK8 |
厂家: | Intersil |
描述: | 5.5A, 30V, 0.050 Ohm, N-Channel, Logic Level UltraFET Power MOSFET |
文件: | 总12页 (文件大小:126K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HUF76105SK8
Data Sheet
May 1999
File Number 4719.1
5.5A, 30V, 0.050 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Features
• Logic Level Gate Drive
• 5.5A, 30V
This N-Channel power MOSFET is
manufactured using the innovative
• Ultra Low On-Resistance, r
• Simulation Models
= 0.050Ω
UltraFET™ process. This advanced
process technology achieves the
DS(ON)
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
®
- Temperature Compensated PSPICE and SABER
Electrical Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at:
www.semi.Intersil.com/families/models.htm
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
Formerly developmental type TA76105.
• Related Literature
Ordering Information
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
PART NUMBER
PACKAGE
BRAND
76105SK8
HUF76105SK8
MS-012AA
Symbol
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76105SK8T.
NC(1)
DRAIN(8)
DRAIN(7)
SOURCE(2)
SOURCE(3)
GATE(4)
DRAIN(6)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
8-1
HUF76105SK8
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±16
GS
Drain Current
o
Continuous (T = 25 C, V
= 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . I
5.5
1.4
1.3
A
A
A
A
GS
D
D
o
Continuous (T = 100 C, V
= 5V) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
GS
o
Continuous (T = 100 C, V
A
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figures 6, 17, 18
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
20
W
mW/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
o
o
1. T = 25 C to 125 C.
J
o
2. 50 C/W measured using FR-4 board at 1 second.
o
2
3. 212 C/W measured using FR-4 board with 0.0115 in copper pad at 1000 seconds.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 12)
30
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
= ±16V
= 0V
1
µA
µA
nA
DSS
DS
DS
GS
o
= 0V, T = 150 C
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
Ω
Ω
Ω
GS(TH)
GS
DS
D
GS
GS
GS
r
I
I
I
= 5.5A, V
= 1.4A, V
= 1.3A, V
= 10V (Figures 9, 10)
= 5V (Figure 9)
0.040
0.055
0.060
0.050
0.072
0.078
DS(ON)
D
D
D
-
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
2
o
Thermal Resistance Junction to Ambient
R
Pad Area = 0.76 in (Note 2)
-
-
-
-
-
-
50
C/W
θJA
2
o
Pad Area = 0.054 in (Figure 23)
175
212
C/W
2
o
Pad Area = 0.0115 in (Figure 23)
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 15V, I
= 4.5V, R
1.3A, R = 11.5Ω,
-
-
-
-
-
-
-
60
-
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
L
= 27Ω
GS
Turn-On Delay Time
Rise Time
t
12
28
31
21
-
d(ON)
(Figures 15, 21, 22)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
80
OFF
8-2
HUF76105SK8
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SWITCHING SPECIFICATIONS (V
Turn-On Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
= 10V)
GS
t
V
V
R
= 15V, I
= 10V,
= 27Ω
5.5A, R = 2.7Ω,
-
-
-
-
-
-
-
60
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
L
Turn-On Delay Time
Rise Time
t
17
21
60
20
-
-
d(ON)
GS
(Figures 16, 21, 22)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
120
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
R
= 15V, I
D
= 10.7Ω
1.4A,
-
-
-
-
-
9
11
6.4
0.45
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
L
Gate Charge at 5V
Q
5.3
0.35
0.8
2.5
g(5)
I
= 1.0mA
g(REF)
(Figures 14, 19, 20)
Threshold Gate Charge
Q
g(TH)
Gate to Source Gate Charge
Reverse Transfer Capacitance
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V = 0V,
GS
-
-
-
325
180
35
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
C
OSS
Reverse Transfer Capacitance
RSS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
39
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
= 5.5A
= 1.4A
-
-
SD
SD
SD
SD
SD
V
Reverse Recovery Time
t
= 1.4A, dI /dt = 100A/µs
SD
-
-
-
-
ns
rr
Reverse Recovered Charge
Q
= 1.4A, dI /dt = 100A/µs
42
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
6
5
4
3
2
o
V
= 10V, R
= 50 C/W
GS
θJA
o
V
= 4.5V, R
= 212 C/W
θJA
1
0
GS
0
25
50
75
100
125
150
25
50
75
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
8-3
HUF76105SK8
Typical Performance Curves (Continued)
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
o
R
= 50 C/W
θJA
0.05
0.02
0.01
1
0.1
P
DM
t
1
t
0.01
0.001
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R + T
J
DM
θJA
θJA A
-5
10
-4
10
-3
-2
10
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
o
R
θJA
= 50 C/W
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
100
10
1
150 - T
A
I = I
25
V
= 5V
GS
125
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
20
200
100
T
= MAX RATED
= 25 C
J
o
T
A
o
STARTING T = 25 C
J
10
100µs
10
1
1ms
o
STARTING T = 150 C
J
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
ds(ON)
10ms
If R = 0
AV
t
= (L)(I )/(1.3*RATED BV
- V )
DD
AS
DSS
If R ≠ 0
AV
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
- V ) +1]
DSS DD
BV
= 30V
DSS MAX
1
0.1
0.01
0.1
1
10
1
10
100
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
AV
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
8-4
HUF76105SK8
Typical Performance Curves (Continued)
25
25
250µs PULSE TEST
V
= 10V
= 5V
GS
o
DUTY CYCLE = 0.5% MAX
o
25 C
V
-55 C
GS
V
= 15V
DD
20
15
10
5
20
15
10
5
V
= 4V
o
GS
150 C
V
= 3V
GS
o
T
= 25 C
250µs PULSE TEST
A
DUTY CYCLE = 0.5% MAX
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
V , DRAIN TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
110
1.8
250µs PULSE TEST
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 5.5A
D
250µs PULSE TEST
DUTY CYCLE = 0.5% MAX
GS
I
= 5.5A
D
1.6
1.4
1.2
1.0
0.8
0.6
90
70
50
30
I
= 1.4A
D
2
4
6
8
10
-80
-40
0
40
80
120
o
160
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
J
GS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.15
V
= V , I = 250µA
I
= 250µA
GS
DS
D
D
1.1
1.0
0.9
0.8
0.7
1.1
1.05
1.0
0.95
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
8-5
HUF76105SK8
Typical Performance Curves (Continued)
10
V
= 15V
600
DD
V
= 0V, f = 1MHz
GS
8
6
4
2
0
500
400
300
200
100
0
C
ISS
WAVEFORMS IN
DESCENDING ORDER:
C
C
OSS
I
I
= 5.5A
= 1.4A
D
D
RSS
0
2
4
6
8
10
0
5
10
15
20
25
30
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
60
120
V
= 10V, V
DD
= 15V, I = 5.5A, R = 2.7Ω
V
= 4.5V, V
= 15V, I = 1.3A, R = 11.5Ω
DD D L
t
GS
D
L
GS
d(OFF)
t
d(OFF)
45
30
15
0
90
60
30
0
t
r
t
f
t
r
t
d(ON)
t
d(ON)
t
f
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
8-6
HUF76105SK8
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 10V
GS
Q
g(5)
V
GS
+
-
V
= 5V
V
V
GS
DD
GS
V
= 1V
GS
DUT
0
Q
I
g(TH)
g(REF)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the thermal
ratings. Precise determination of P is complex and influ-
DM
JM
resistance of the heat dissipating path determines the maximum
enced by many factors:
allowable device power dissipation, P , in an application.
DM
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
o
Therefore the application’s ambient temperature, T ( C), and
A
o
thermal resistance R
( C/W) must be reviewed to ensure that
θJA
T
is never exceeded. Equation 1 mathematically represents
JM
2. The number of copper layers and the thickness of the
board.
the relationship and serves as the basis for establishing the rat-
ing of the part.
3. The use of external heat sinks.
4. The use of thermal vias.
(T
– T )
JM
Z
A
(EQ. 1)
P
= ------------------------------
DM
θJA
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power dissipation
8-7
HUF76105SK8
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the R
sponding to the descending list in the graph. SPICE and SABER
thermal models are provided for each of the listed pad areas.
θJA
for the device as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board with 1oz
copper after 1000 seconds of steady state power with no air
flow. This graph provides the necessary information for calcula-
tion of the steady state junction temperature or power dissipa-
tion. Pulse applications can be evaluated using the Intersil
device Spice thermal model or manually utilizing the normal-
ized maximum transient thermal impedance curve.
Copper pad area has no perceivable effect on transient thermal
impedance for pulse widths less than 100ms. For pulse widths
less than 100ms the transient thermal impedance is deter-
mined by the die and package. Therefore, CTHERM1 through
CTHERM5 and RTHERM1 through RTHERM5 remain con-
stant for each of the thermal models. A listing of the model com-
ponent values is available in Table 1.
300
Displayed on the curve are R
θJA
values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
250
o
2
212 C/W - 0.0115in
resistance and ultimately the power dissipation, P
.
o
2
200
150
100
50
DM
175 C/W - 0.054in
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
R
is defined as the natural log of the area times a coefficient
θJA
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R
= 103.2 - 24.3 * ln(AREA)
θJA
R
= 103.2 – 24.3 × ln(Area)
(EQ. 2)
θJA
0
0.001
0.01
0.1
2
1
The transient thermal impedance (Z ) is also effected by var-
θJA
AREA, TOP COPPER AREA (in )
ied top copper board area. Figure 24 shows the effect of copper
pad area on single pulse transient thermal impedance. Each
trace represents a copper pad area in square inches corre-
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
0.140 in
0.257 in
0.380 in
2
2
120
2
2
0.493 in
80
40
0
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8-8
HUF76105SK8
PSPICE Electrical Model
.SUBCKT HUF76105 2 1 3 ;
REV June 1998
CA 12 8 4.95e-10
CB 15 14 5.15e-10
CIN 6 8 2.9e-10
LDRAIN
DPLCAP
10
DRAIN
2
5
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
EBREAK 11 7 17 18 33.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
5
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
+
IT 8 17 1
RGATE
GATE
1
6
-
18
22
MMED
LDRAIN 2 5 1e-9
LGATE 1 9 9.2e-10
LSOURCE 3 7 3.2e-10
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e-3
RGATE 9 20 3.39
RBREAK
12
15
13
8
14
13
17
18
RLDRAIN 2 5 10
RLGATE 1 9 9.2
RLSOURCE 3 7 3.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 22e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),6))}
.MODEL DBODYMOD D (IS = 3.01e-13 IKF = 20 RS = 1.47e-2 TRS1 = -1.7e-3 TRS2 = 4e-5 CJO = 5.74e-10 TT = 2.88e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 3.94e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7)
.MODEL DPLCAPMOD D (CJO = 2.55e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 1.92 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)
.MODEL MSTROMOD NMOS (VTO = 2.26 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.7 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8)
.MODEL RDRAINMOD RES (TC1 = 8e-3 TC2 = 5.3e-5)
.MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.87e-3 TC2 = -1.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2 VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8-9
HUF76105SK8
SABER Electrical Model
REV July 1998
template huf76105 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.01e-13, cjo = 5.74e-10, tt = 2.88e-8, xti = 4.5, m = 0.43)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.55e-10, is = 1e-30, n = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 1.92, kp = 2.1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.26, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.7, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
c.ca n12 n8 = 4.95e-10
c.cb n15 n14 = 5.15e-10
c.cin n6 n8 = 2.9e-10
50
-
71
RDRAIN
6
8
ESG
EVTHRES
+
+
16
21
d.dbody n7 n71 = model=dbodymod
-
19
8
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
MWEAK
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
MMED
9
i.it n8 n17 = 1
20
MSTRO
8
17
18
-
RLGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 9.2e-10
l.lsource n3 n7 = 3.2e-10
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A
S2A
14
RBREAK
12
15
13
8
17
18
13
res.rbreak n17 n18 = 1, tc1 = 9.94e-4, tc2 = 9.84e-8
res.rdbody n71 n5 = 1.47e-2, tc1 = -1.7e-3, tc2 = 4e-5
res.rdbreak n72 n5 = 3.94e-1, tc1 = 9.94e-4, tc2 = 9.12e-7
res.rdrain n50 n16 = 9e-3, tc1 = 8e-3, tc2 = 5.3e-5
res.rgate n9 n20 = 3.39
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 9.2
res.rlsource n3 n7 = 3.2
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rsource n8 n7 = 22e-3, tc1 = 1e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -1.87e-3, tc2 = -1.2e-6
spe.ebreak n11 n7 n17 n18 = 33.87
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 6))
}
}
8-10
HUF76105SK8
SPICE Thermal Model
REV June 1998
HUF76105SK8
2
JUNCTION
th
Copper Area = 0.02 in
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
RTHERM1
CTHERM1
8
7
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
6
5
SABER Thermal Model
2
Copper Area = 0.02 in
template thermal_model th tl
thermal_c th, tl
{
4
3
2
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
tl
CASE
TABLE 1. Thermal Models
2
2
2
2
2
COMPONANT
CTHERM6
0.02 in
0.14 in
1.3e-1
6.0e-1
2.5
0.257 in
0.38 in
0.493 in
1.5e-1
7.5e-1
3
9.0e-2
4.0e-1
1.4
1.5e-1
4.5e-1
2.2
1.5e-1
6.5e-1
3
CTHERM7
CTHERM8
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
8-11
HUF76105SK8
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8-12
相关型号:
HUF76107D3ST
Power Field-Effect Transistor, 20A I(D), 30V, 0.08ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, TO-252AA, 3 PIN
FAIRCHILD
HUF76107D3ST_NL
20A, 30V, 0.08ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, TO-252AA, 3 PIN
ROCHESTER
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Power Field-Effect Transistor, 20A I(D), 30V, 0.08ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, TO-252AA, 3 PIN
FAIRCHILD
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