HUF76112SK8 [INTERSIL]
7.5A, 30V, 0.026 Ohm, N-Channel, Logic Level Power MOSFET; 7.5A ， 30V ， 0.026 Ohm的N通道，逻辑电平功率MOSFET
| 型号： | HUF76112SK8 |
| 厂家： | 
Intersil |
| 描述： | 7.5A, 30V, 0.026 Ohm, N-Channel, Logic Level Power MOSFET |
| 文件： | 总12页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76112SK8
TM
Data Sheet
April 2000
File Number 4834.1
7.5A, 30V, 0.026 Ohm, N-Channel, Logic
Level Power MOSFET
The HUF76112SK8 is an Application-Specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses, thereby increasing the overall system efficiency.
Features
• 7.5A, 30V
- r
- r
= 0.026Ω, VGS = 10V
= 0.033Ω, VGS = 5V
DS(ON)
DS(ON)
Symbol
• PWM Optimized for Synchronous Buck Applications
• Fast Switching
SOURCE (1)
SOURCE (2)
SOURCE (3)
GATE (4)
DRAIN (8)
DRAIN (7)
DRAIN (6)
DRAIN (5)
• Low Gate Charge
- Q Total 15nC (Typ)
g
• Low Capacitance
- C
- C
725pF (Typ)
Packaging
ISS
36pF (Typ)
RSS
SO8 (JEDEC MS-012AA)
BRANDING DASH
Ordering Information
PART NUMBER
PACKAGE
BRAND
76112SK8
5
HUF76112SK8
MS-012AA
1
2
3
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the HUF76112SK8 in tape and reel, e.g., HUF76112SK8T.
4
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
SYMBOL
PARAMETER
Drain to Source Voltage (Note 1)
HUF76112SK8
UNITS
V
30
30
V
V
V
DSS
V
Drain to Gate Voltage (R = 20kΩ) (Note 1)
GS
DGR
V
Gate to Source Voltage
±16
GS
Drain Current
o
I
I
Continuous (T = 25 C, V = 10V) (Figure 2) (Note 2)
GS
7.5
4.0
Figure 4
A
A
A
D
D
A
o
Continuous (T = 100 C, V
= 5V) (Note 2)
A
GS
I
Pulsed Drain Current
DM
P
Power Dissipation (Note 2)
Derate Above 25 C
2.5
20
W
mW/ C
D
o
o
o
T , T
STG
Operating and Storage Temperature
-55 to 150
C
J
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
o
T
300
260
C
L
o
T
C
pkg
THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient
2
2
o
Measured using FR-4 board with 0.76 in (490.3 mm ) copper pad at 10
second.
50
C/W
2
2
o
R
θJA
Measured using FR-4 board with 0.054 in (34.8 mm ) copper pad at 1000
seconds. (Figure 23)
152
189
C/W
2
2
o
Measured using FR-4 board with 0.0115 in (7.42 mm ) copper pad at 1000
seconds. (Figure 23)
C/W
NOTES:
o
o
1. T = 25 C to 125 C.
J
o
2. R
= 50 C/W
θJA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
UltraFET® is a registered trademark of Intersil Corporation.
HUF76112SK8
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
= 250µA, V
= 0V (Figure 12)
30
-
-
-
-
-
-
V
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
= ±16V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
A
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
Ω
Ω
GS(TH)
GS
DS
D
GS
GS
r
I
I
= 7.5A, V
= 4.0A, V
= 10V (Figures 9, 10)
= 5V (Figure 9)
0.022
0.027
0.026
0.033
DS(ON)
D
D
-
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 5V)
t
GS
t
V
V
R
= 15V, I = 4.0A
D
= 5V,
= 20Ω
-
-
-
-
-
-
-
77
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
11
40
35
32
-
-
d(ON)
GS
t
(Figures 15, 21, 22)
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
100
OFF
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 15V, I = 7.5A
D
= 10V,
= 20Ω
-
-
-
-
-
-
-
75
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
7.2
43
52
45
-
-
d(ON)
GS
t
(Figures 16, 21, 22)
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
145
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Total Gate Charge at 5V
Q
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 15V,
-
-
-
-
-
15
7.2
18
8.7
0.9
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 7.5A,
I
I
D
g(TOT)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
(Figures 14, 19, 20)
0.74
2.1
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
2.9
-
C
V
= 25V, V = 0V,
GS
-
-
-
725
325
36
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figures 13)
Output Capacitance
C
OSS
Reverse Transfer Capacitance
C
RSS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
25
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
= 7.5A
= 4A
-
-
-
-
-
-
-
-
SD
SD
SD
SD
SD
V
Reverse Recovery Time
t
= 7.5A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 7.5A, dI /dt = 100A/µs
SD
14
nC
RR
2
HUF76112SK8
Typical Performance Curves
1.2
8
6
4
2
1.0
0.8
0.6
0.4
0.2
0
o
V
= 10V, R
= 50 C/W
GS
θJA
o
V
= 5V, R
θJA
= 189 C/W
GS
0
0
25
50
75
100
125
150
25
50
75
100
125
150
o
T , AMBIENT TEMPERATURE ( C)
o
A
T , AMBIENT TEMPERATURE ( C)
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
o
R
= 50 C/W
θJA
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
SINGLE PULSE
J
DM
θJA
θJA
A
0.001
10
-5
-4
10
-3
10
-2
10
-1
10
0
1
2
3
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
o
o
= 25 C
R
θJA
= 50 C/W
T
A
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
100
10
1
CURRENT AS FOLLOWS:
V
= 5V
GS
150 - T
A
I = I
25
125
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
2
3
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
HUF76112SK8
Typical Performance Curves (Continued)
500
200
o
= 50 C/W
R
θJA
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
SINGLE PULSE
100
T
T
= MAX RATED
= 25 C
J
o
100
t
AV
- V ) +1]
DD
AS DSS
A
100µs
o
10
STARTING T = 25 C
J
10
1
1ms
o
STARTING T = 150 C
J
OPERATION IN THIS
AREA MAY BE
10ms
LIMITED BY r
DS(ON)
1
0.01
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
0.1
1
10
100
V
DS
t
, TIME IN AVALANCHE (ms)
AV
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
25
25
PULSE DURATION = 80µs
V
=
GS
10V
DUTY CYCLE = 0.5% MAX
V
= 15V
V
= 5V
DD
GS
20
15
10
20
15
10
5
V
= 4.5V
GS
V
= 4V
GS
V
= 3.5V
GS
V
= 3V
o
GS
T
= 25 C
o
J
T
= 150 C
J
5
0
PULSE DURATION = 80µs
o
T
= -55 C
J
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
A
0
0
0.5
1.0
1.5
2.0
1.5
2.0
2.5
3.0
3.5
4.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50
40
30
20
10
1.6
1.3
1.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 7.5A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
GS D
I
= 7.5A
D
I
= 1A
D
0.7
-80
-40
0
40
80
120
160
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
HUF76112SK8
Typical Performance Curves (Continued)
1.2
1.1
1.2
I
= 250µA
D
V
= V , I = 250µA
GS
DS
D
1.0
0.8
0.6
1.0
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
T , JUNCTION TEMPERATURE ( C)
J
o
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
2000
V
= 15V
DD
C
= C
GS
+ C
GD
ISS
1000
8
6
4
2
0
C
C
+ C
OSS
DS GD
100
20
C
=
C
WAVEFORMS IN
DESCENDING ORDER:
RSS
GD
I
I
= 7.5A
= 1A
D
D
V
= 0V, f = 1MHz
GS
0
3
6
9
12
15
0.1
1.0
10
30
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
80
120
t
d(OFF)
V
= 5V, V
DD
= 15V, I = 4.0A
D
V
= 10V, V
DD
= 15V, I = 7.5A
D
GS
GS
100
80
t
d(OFF)
60
40
t
t
f
f
60
t
r
t
r
40
20
0
t
20
0
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
5
HUF76112SK8
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
VARY t TO OBTAIN
P
+
I
AS
R
REQUIRED PEAK I
G
V
DD
AS
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(TOT)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
6
HUF76112SK8
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, P
Thermal Resistance vs Mounting Pad Area
.
DM
The maximum rated junction temperature, T , and the
JM
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P , in
DM
R
is defined as the natural log of the area times a coefficient
an application. Therefore the application’s ambient
θJA
o
o
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
temperature, T ( C), and thermal resistance R
( C/W)
A
θJA
must be reviewed to ensure that T is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
R
= 83.2 – 23.6 × ln(Area)
(EQ. 2)
θJA
The transient thermal impedance (Z
θJA
) is also effected by
(T
– T )
JM
Z
A
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
(EQ. 1)
P
= ------------------------------
DM
θJA
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
240
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
R
= 83.2 - 23.6*ln(AREA)
θJA
o
2
200
160
120
80
189 C/W - 0.0115in
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the R
θJA
o
2
152 C/W - 0.054in
for the device as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board with 1oz
copper after 1000 seconds of steady state power with no air
flow. This graph provides the necessary information for
calculation of the steady state junction temperature or power
dissipation. Pulse applications can be evaluated using the
Intersil device Spice thermal model or manually utilizing the
normalized maximum transient thermal impedance curve.
0.01
0.1
AREA, TOP COPPER AREA (in )
1.0
2
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are R
θJA
values listed in the Electrical
Specifications table. The points were chosen to depict the
150
COPPER BOARD AREA - DESCENDING ORDER
2
0.04 in
2
120
90
60
30
0
0.28 in
0.52 in
0.76 in
1.00 in
2
2
2
-1
10
0
1
2
3
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
HUF76112SK8
PSPICE Electrical Model
.SUBCKT HUF76112SK8 2 1 3 ;
REV 9 Mar 2000
CA 12 8 8.00e-10
CB 15 14 7.40e-10
CIN 6 8 6.90e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 31.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
IT 8 17 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
LDRAIN 2 5 1.00e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 1.29e-10
LGATE
RGATE
EVTEMP
+
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.00e-3
RGATE 9 20 2.82
RLDRAIN 2 5 10
RLGATE 1 9 9 11.2
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*215),2))}
.MODEL DBODYMOD D (IS = 7.75e-13 RS = 8.08e-3 TRS1 = -1.89e-4 TRS2 = 0 CJO = 1.17e-9 TT = 1.41e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 1.34e-1 TRS1 = 0 TRS2 = 0)
..MODEL DPLCAPMOD D (CJO = 3.72e-10 IS = 1e-30 M = 0.72)
.MODEL MMEDMOD NMOS (VTO = 1.90 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.82)
.MODEL MSTROMOD NMOS (VTO = 2.25 KP = 43 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.70 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.15e-4 TC2 = -2.97e-7)
.MODEL RDRAINMOD RES (TC1 = 7.40e-3 TC2 = 2.00e-5)
.MODEL RSLCMOD RES (TC1 = 4.93e-3 TC2 = 1.01e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -5.28e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.55e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.50 VOFF= -2.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.50 VOFF= -6.50)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.20 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -2.20)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
HUF76112SK8
SABER Electrical Model
REV 9 Mar 2000
template huf76112SK8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 7.75e-13,rs=8.08e-3,trs1=-1.89e-4,trs2=0, cjo = 1.17e-9, tt = 1.41e-8, m = 0.43)
dp..model dbreakmod = (rs=1.34e-1,trs1=0,trs2=0)
dp..model dplcapmod = (cjo = 3.72e-10, is = 1e-30, m = 0.72)
m..model mmedmod = (type=_n, vto = 1.90, kp = 1.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.25, kp = 43, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.70, kp = 0.10, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.5, voff = -2.5)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.5, voff = -6.5)
LDRAIN
DPLCAP
5
DRAIN
2
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.2, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -2.2)
RLDRAIN
RSLC1
51
c.ca n12 n8 = 8.00e-10
c.cb n15 n14 = 7.40e-10
c.cin n6 n8 = 6.90e-10
RSLC2
ISCL
DBREAK
11
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
-
19
8
i.it n8 n17 = 1
MWEAK
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 1.12e-9
l.lsource n3 n7 = 1.29e-10
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
7
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 9.15e-4, tc2 = -2.97e-7
res.rdrain n50 n16 = 5.00e-3, tc1 = 7.40e-3, tc2 = 2.00e-5
res.rgate n9 n20 = 2.82
RBREAK
12
15
13
14
13
17
18
8
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 11.2
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 4.93e-3, tc2 = 1.01e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10.00e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.55e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -5.28e-6
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 31.89
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/215))** 2))
}
}
9
HUF76112SK8
SPICE Thermal Model
REV 11 Nov 1999
ITF86130SK8T
2
JUNCTION
th
Copper Area = 0.04 in
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 1.2e-1
CTHERM7 3 2 0.5
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
8
7
CTHERM8 2 tl 1.3
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 26
RTHERM7 3 2 39
RTHERM8 2 tl 55
6
5
SABER Thermal Model
2
Copper Area = 0.04 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 1.2e-1
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 1.3
4
3
2
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 26
rtherm.rtherm7 3 2 = 39
rtherm.rtherm8 2 tl = 55
}
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONENT
CTHERM6
0.04in
0.28in
1.5e-1
1.0
0.52in
0.76in
1.0in
1.2e-1
0.5
1.3
26
2.0e-1
2.0e-1
1.0
2.0e-1
1.0
3.0
12
CTHERM7
1.0
3.0
15
CTHERM8
2.8
3.0
RTHERM6
20
13
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
10
HUF76112SK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E
A
INCHES
MILLIMETERS
A
1
1
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
NOTES
A
0.0532
0.004
0.0688
0.0098
0.020
-
-
e
A
1
b
0.013
-
D
c
D
E
0.0075
0.189
0.0098
0.1968
0.244
-
2
-
b
0.2284
0.1497
E
0.1574
3
-
1
e
0.050 BSC
1.27 BSC
o
h x 45
H
L
0.0099
0.016
0.0196
0.050
0.25
0.40
0.50
1.27
-
4
c
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
0.004 IN
0.10 mm
L
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
o
o
0 -8
0.060
1.52
3. Dimension “E ” does not include inter-lead flash or protrusions.
1
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
0.050
1.27
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
0.024
0.6
0.155
4.0
0.275
7.0
4.0mm
USER DIRECTION OF FEED
1.5mm
DIA. HOLE
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
2.0mm
1.75mm
C
L
MS-012AA
12mm TAPE AND REEL
12mm
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
13mm
COVER TAPE
330mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
12.4mm
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
11
HUF76112SK8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
12
相关型号：
©2020 ICPDF网 联系我们和版权申明