ISL21400IU8Z-TK [INTERSIL]
Programmable Temperature Slope Voltage Reference; 可编程温度斜率电压基准
| 型号： | ISL21400IU8Z-TK |
| 厂家： | 
Intersil |
| 描述： | Programmable Temperature Slope Voltage Reference |
| 文件： | 总17页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL21400
®
Data Sheet
December 14, 2006
FN8091.0
Programmable Temperature Slope
Voltage Reference
Features
• Programmable reference voltage
• Programmable temperature slope
• Programmable Gain Amplifier
The ISL21400 features a precision voltage reference
combined with a temperature sensor whose output voltage
varies linearly with temperature. The precision 1.20V
reference has a very low temperature coefficient (tempco),
and its output voltage is scaled by an internal DAC (V
produce a temperature stable output voltage that is
• Non-volatile storage of programming registers
) to
REF
2
• I C serial interface
programmable from 0V to 1.20V. The output voltage from the
• 2% total accuracy over temperature and V
• 200µA typical active supply current
range
CC
temperature sensor (V ) is summed with V
to produce
TS
REF
a temperature dependent output voltage.
• Operating temperature range = -40°C to +85°C
• 8 Ld MSOP package
The slope of the V portion of the output voltage can be
TS
programmed to be positive or negative in the range
-2.1mV/°C to +2.1mV/°C. A programmable gain amplifier
Applications
(PGA) sums the V and the V
voltages and provides
TS
REF
gains of 1x, 2x, and 4x to scale the output up to 4.8V and the
slope to ±8.4mV/°C.
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
• Sensor bias and linearization
• Data acquisition systems
• Variable DAC reference
• Amplifier biasing
The V
REF
and V terms are programmable with 8 bits of
TS
2
resolution via an I C bus and the values are stored in non-
volatile registers. The PGA gain is also set via the I C bus
2
and the value is stored in a non-volatile register. Non-volatile
memory storage assures the programmed settings are
retained on power-down, eliminating the need for software
initialization at device power-up.
Temperature Characteristics Curve
Pinout
3.0
ISL21400
(8 LD MSOP)
TOP VIEW
A
= 2
V
2.5
2.0
1.5
1.0
0.5
0.0
TS = 127
= 1
TS = 255
TS = 255
V
V
A2
1
8
CC
TS = 0
TS = 0
A
V
A1
A0
2
3
7
6
OUT
SDA
SCL
TS = 127
V
SS
4
5
-40
-15
10
35
60
85
TEMPERATURE (°C)
Ordering Information
V
RANGE
(V)
TEMP RANGE
(°C)
DD
PART NUMBER (Note)
ISL21400IU8Z
PART MARKING
DEW
PACKAGE
PKG. DWG. #
M8.118
M8.118
2.7 to 5.5
2.7 to 5.5
-40 to +85
-40 to +85
8 Ld MSOP (Pb-free)
8 Ld MSOP (Pb-free)
ISL21400IU8Z-TK
DEW
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL21400
Pin Description
MSOP
SYMBOL
DESCRIPTION
2
1
2
3
4
5
6
7
8
A2
A1
A0
Hardwire slave address pin for I C serial bus
2
Hardwire slave address pin for I C serial bus
2
Hardwire slave address pin for I C serial bus
V
Ground pin
SS
SCL
SDA
Serial bus clock input
Serial bus data input/output
Output voltage
VOUT
V
Device power supply
CC
Block Diagram
VCC
TEMP
SENSE
V
(n)
TS
DAC
V
A
Σ
OUT
V
(m)
REF
DAC
V
GAIN
REF
SELECT
AV = 1,2,4
BIAS
SCL
SDA
EEPROM
8x8
COMMUNICATIONS
AND
REGISTERS
n = 0 to 255
m = 0 to 255
VSS
A0
A1
A2
FN8091.0
December 14, 2006
2
ISL21400
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 6.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Thermal Resistance (Typical, Note 15)
θ
JA (°C/ W)
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
Moisture Sensitivity for MSOP Package
(See Technical Brief TB363) . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
130
Voltage on V
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
OUT
CC
Voltage on All Other Pins . . . . . . . . . . . . . . . . . .-0.3V to V +0.3V
CC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
V
= 5.5V, T = 25°C to +85°C, unless otherwise noted
CC A
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 2)
MAX
UNITS
POWER SUPPLY
V
Supply Voltage Range
Supply
2.7
3.0
5.5
V
CC
I
Q
V
V
= 2.7V
= 5.5V
Standby, SDA = SCL = V
200
235
400
500
µA
µA
CC
CC
CC
Standby, SDA = SCL = V
CC
I
Non-Volatile Supply
Q(NV)
Vpor
V
V
= 2.7V
= 5.5V
Nonvolatile write
Nonvolatile write
500
1.3
750
1.6
2.6
µA
mA
V
CC
CC
Power-on Recall Voltage
2.0
0.2
Minimum V
occurs
at which memory recall
CC
V
V
Ramp Rate
CC
V/ms
ms
CC
Ramp
t
Power-Up Delay
above Vpor, time delay to Register
3
D
V
CC
recall, and I C Interface in standby state
2
OUTPUT VOLTAGE PERFORMANCE SPECIFICATIONS
G
G
Gain Error
A
= 2 (Notes 1, 3, 12)
A = 4 (Notes 1, 3, 12)
V
-1
-1
+1
+1
%
%
E1
E2
V
Gain Error
K
Temperature Sensor Coefficient
(Notes 1, 8)
-2.2
-2.1
-2.0
mV/°C
V
Absolute Output Voltage (Swing) Range Unloaded, T = +25°C (Note 3)
V
-
GND +
0.100
A
CC
0.100
Absolute Output Voltage (Swing) Range Loaded, I
= ±500µA (Note 3)
V
0.250
-
GND +
0.250
V
OUT
CC
TS1
TS2
TS3
TS4
Temperature Sensor Slope
A
= 1, n = 255, m = 255 (Notes 1, 6)
= 2, n = 255, m = 255 (Notes 1, 6)
= 4, n = 255, m = 255 (Notes 1, 6)
= 1, n = 255, m = 0 to 255 (Notes 1, 10)
-2.1
-4.2
-8.4
8.2
mV/°C
mV/°C
mV/°C
V
Temperature Sensor Slope
A
V
Temperature Sensor Slope
A
V
Incremental Temperature Sensor Slope
A
μV/°C
V
per Code
TSNL Temperature Slope Non-Linearity
n = 255, m = 0 to 255, T = -40°C to +85°C
(Notes 1, 11)
±0.5
±1.0
%
DNL
INL
DAC Relative Linearity (V
CC
=2.7 to 5.5V) V
and Temp Sense; A = 1 (Note 13)
-1.0
-3.0
+1.0
+3.0
LSB
LSB
REF
V
DAC Absolute Linearity (V = 2.7 to 5.5V) V
CC
and Temp Sense; A = 1 (Note 13)
V
REF
FN8091.0
December 14, 2006
3
ISL21400
Analog Specifications
V
= 5.5V, T = 25°C to +85°C, unless otherwise noted
A
CC
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
(Notes 1, 8, 9)
= 1, n = 255, m = 128, T = +25°C,
MIN
(Note 2)
MAX
±2
UNITS
V
Total Error for V
±1
%
V
OUT(TE)
OUT
V
V
V
Output Voltage V
, Gain = 1
REF
A
1.189
2.378
4.756
1.2
1.211
OUT1
OUT2
OUT3
V
A
V
= 5.5V
CC
Output Voltage V
Output Voltage V
, Gain = 2
REF
A
= 2, n = 255, m = 128, T = +25°C,
2.40
4.80
2.422
4.844
V
V
V
A
V
= 5.5V
CC
A = 4, n = 255, m = 128, T = +25°C,
V
, Gain = 4
REF
A
V
= 5.5V
CC
V
V
Output Voltage V
Output Voltage V
+ TS
+ TS
A
= 1, n = 255, m = 0, T = +85°C (Note 3)
1.315
1.188
1.326
1.199
1.337
1.210
V
V
OUT4
OUT5
REF
REF
V
A
A
= 1, n = 255, m = 128, T = +85°C
A
V
(Note 3)
V
Output Voltage V
+ TS
A
= 1, n = 255, m = 255, T = +85°C
1.063
1.074
1.085
V
OUT6
REF
V
A
(Note 3)
V
V
Output Voltage V
Output Voltage V
+ TS
+ TS
A = 1, n = 255, m = 0, T = -40°C, (Note 3)
1.052
1.189
1.063
1.200
1.074
1.211
V
V
OUT7
OUT8
REF
REF
V
A
A
= 1, n = 255, m = 128, T = -40°C,
A
V
(Note 3)
V
Output Voltage V
+ TS
A
= 1, n = 255, m = 255, T = -40°C,
1.336
50
1.325
1.347
V
OUT9
REF
V
A
(Note 3)
OUTPUT VOLTAGE DC SPECIFICATIONS
PSRR Power Supply Rejection Ratio
A
= 1, n = 255, m = 128, (Note 7)
60
2
dB
V
R
Output Impedance (load regulation)
Given by R
= (ΔV
/ΔI
OUT OUT
) ,
5
Ω
OUT
OUT
= +25°C, I
T
= ±500µA
A
OUT
I
Short Circuit, Sourcing
Short Circuit, Sinking
Load Capacitance
V
= 5.5V, V
= 5.5V, V
= 0V
5
6
5
9
9
mA
mA
nF
SC
CC
CC
OUT
OUT
V
= 5.5V
C
Reference output stable for all C up to
L
L
specifications
OUTPUT VOLTAGE AC SPECIFICATIONS
V
Output Voltage Noise
0.1Hz to 10Hz, A =1
90
TBD
500
60
µV
p-p
N
V
10Hz to 10kHz, C = 0, A = 1
mV
RMS
L
V
Power On Response
Line Ripple Rejection
1% Settling
= 5V ±100mV, f = 120Hz
µs
V
dB
CC
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise)
TYP
SYMBOL
PARAMETER
Input Leakage
TEST CONDITIONS
= GND to V
MIN
(Note 2)
MAX
UNITS
I
V
1
V
V
V
V
LI
IN
CC
V
Input LOW Voltage
Input HIGH Voltage
-0.3
0.3 x V
IL
CC
V
0.7 x V
V
+ 0.3
CC
IH
CC
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x V
CC
V
C
SDA Output Buffer LOW Voltage
Pin Capacitance
I
= 3mA
0
0.4
V
OL
OL
(Note 3)
(Note 3)
10
pF
pin
f
SCL Frequency
400
kHz
SCL
FN8091.0
December 14, 2006
4
ISL21400
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
TYP
(Note 2)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
t
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
(Note 3)
50
ns
sp
t
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
900
ns
ns
AA
30% of V , until SDA exits
CC
the 30% to 70% of V
window (Note 3)
CC
t
Time the Bus Must be Free Before SDA crossing 70% of V
the Start of a New Transmission
1300
BUF
CC
during a STOP condition, to
SDA crossing 70% of V
CC
during the following START
condition (Note 3)
t
Clock LOW Time
Measured at the 30% of V
crossing (Note 3)
1300
600
ns
ns
ns
LOW
CC
CC
t
Clock HIGH Time
Measured at the 70% of V
crossing (Note 3)
HIGH
t
START Condition Setup Time
SCL rising edge to SDA
600
SU:STA
falling edge; both crossing
70% of V (Note 3)
CC
From SDA falling edge
crossing 30% of V to SCL
t
t
START Condition Hold Time
Input Data Setup Time
600
100
0
ns
ns
ns
ns
HD:STA
CC
falling edge crossing 70% of
(Note 3)
V
CC
From SDA exiting the 30% to
70% of V window, to SCL
SU:DAT
HD:DAT
SU:STO
HD:STO
CC
rising edge crossing 30% of
(Note 3)
V
CC
From SCL rising edge
crossing 70% of V to SDA
t
Input Data Hold Time
CC
entering the 30% to 70% of
window (Note 3)
V
CC
t
STOP Condition Setup Time
From SCL rising edge
crossing 70% of V , to SDA
CC
rising edge crossing 30% of
600
V
(Note 3)
CC
t
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL
falling edge; both crossing
1300
0
ns
ns
70% of V
(Note 3)
CC
t
Output Data Hold Time
From SCL falling edge
DH
crossing 30% of V , until
CC
SDA enters the 30% to 70%
of V
window (Note 3)
CC
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
(Note 3)
20 +
0.1 x Cb
250
250
400
ns
ns
pF
R
CC
t
From 70% to 30% of V
(Note 3)
20 +
0.1 x Cb
F
CC
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
(Note 4)
10
FN8091.0
December 14, 2006
5
ISL21400
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 2)
MAX
UNITS
Rpu
SDA and SCL Bus Pull-up Resistor Maximumisdetermined byt
1
kΩ
R
Off-chip
and t
F
For Cb = 400pF, max is about
2~2.5kΩ
For Cb = 40pF, max is about
15~20kΩ
I
Output Leakage Current (SDA only) V
= GND to V
CC
1
µA
V
LO
OUT
V
A1, A0, SHDN, SDA, and SCL Input
Buffer LOW Voltage
-0.3
V
x 0.3
CC
IL
V
A1, A0, SHDN, SDA, and SCL Input
Buffer HIGH Voltage
V
x 0.7
V
V
V
IH
CC
CC
V
SDA Output Buffer LOW Voltage
I
= 100µA (Note 3), at 3mA
0
0.4
OL
OL
sink
C
Capacitive Loading of SDA or SCL Total on-chip and off-chip
(Note 3)
10
400
pF
L
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T ≤ +55°C
t
Non-Volatile Write Cycle Time
12
20
WC
(Note 14)
Timing Diagrams
Bus Timing
t
sp
t
t
t
t
t
F
HIGH
LOW
R
HD:STO
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
BUF
AA
DH
SDA
(OUTPUT TIMING)
Write Cycle Timing
SCL
8th BIT OF LAST BYTE
ACK
SDA
t
WC
STOP
CONDITION
START
CONDITION
NOTES:
1. Equation 1 governs the output voltage and is stated as follows:
⎧
⎨
⎩
⎫
n
255
(2 • m)–255
---------
--------------------------------
, n = 0 to 255, m = 0 to 255, K = -2.1mV/C(typ), T0 = +25°C
⎬
V
= A
•
V
•
+ K(T – T )
OUT
V
REF
0
255
⎭
2. Typical values are for T = +25°C and V
A
= 5.5V.
CC
FN8091.0
December 14, 2006
6
ISL21400
3. This parameter is not 100% tested.
4. Cb = total capacitance of one bus line in pF.
5. t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
WC
minimum cycle time to be allowed for any nonvolatile write by the user.
6. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in V
is divided by the
OUT
temperature range; in this case, -40°C to +85°C = +125°C. TS , TS , TS =.
1
2
3
V
(Tmin) – V
(Tmax)
OUT
OUT
-------------------------------------------------------------------------------
TS =
Tmin – Tmax
7. Given by PSRR (dB) = 20 * log (ΔVout/ΔV ) at DC.
10 CC
8. Test +25°C and +85°C only.
9. Total error of Equation 1 @ A =1, K = -2.1mV/°C, V
= 1.20V, m = 255, n = 255 to 0, V
CC
= 3.0V
x100%
V
REF
V
(measured) – V
(Equation1)
OUT
OUT
------------------------------------------------------------------------------------------------------------
V
(TE) =
OUT
V
(Equation1)
OUT
10. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in V
is divided by the
temperature range. Incremental TS is the temperature slope at m = 255 minus the temperature slope at m = 0 divided by 255 with A = 1, n = 255
OUT
V
V
(Tmin) – V
(Tmax)
V
(Tmin) – V
(Tmax)
OUT
⎛
⎜
⎝
⎞
⎟
⎛
⎜
⎝
⎞
⎟
OUT
OUT
OUT
-------------------------------------------------------------------------------
(Tmin – Tmax)
-------------------------------------------------------------------------------
TS4 =
–
÷ 255
(Tmin – Tmax)
⎠
⎠
m = 255
m = 0
11. Temperature Slope Non- linearity is measured over the specified temperature range. The actual change in output voltage is subtracted from the
expected change in output voltage, and then divided by the expected change to normalize before converting to percent.
(TS (ΔT)) – ΔVOUT
y
---------------------------------------------------------
TSNL =
x100%; y = 1, 2, 3
TS × ΔT
y
12. For codes n = 8 to 255
13. Guaranteed monotonic
2
14. t
is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal nonvolatile
WC
write cycle.
15. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Typical Performance Curves
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
A
= 2
V
A
= 4
V
TS = 127
= 1
TS = 255
TS = 255
TS = 0
TS = 0
A
V
TS = 127
TS = 255
TS = 0
TS = 127
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 1. V
vs TEMPERATURE (A = 1, 2)
V
FIGURE 2. V
vs TEMPERATURE (A = 4)
OUT V
OUT
FN8091.0
December 14, 2006
7
ISL21400
Typical Performance Curves (Continued)
1.22
0.4
0.35
0.3
VREF REGISTER = 255d
TS REGISTER = 127d
VREF REGISTER = 255d
TS REGISTER = 127d
+85°C
1.21
+25°C
0.25
0.2
1.20
1.19
1.18
-4×C
-40°C
0.15
0.1
0.05
0
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
2
3
4
5
6
7
V
V
(V)
CC
CC
FIGURE 3. V
vs V
(V
CC CC
= +2.7V to +5.5V)
FIGURE 4. SUPPLY VOLTAGE vs SUPPLY CURRENT
OUT
NO LOAD
= 1
NO LOAD
= 4
A
V
A
V
100µV/DIV (V
x 1000)
OUT
50µV/DIV (V
x 1000)
OUT
FIGURE 5. V
VOLTAGE NOISE (A = 1, NO LOAD)
V
FIGURE 6. V
VOLTAGE NOISE (A = 4, NO LOAD)
OUT V
OUT
1.22
CH1 = V
CC
1.21
1.20
1.19
CH2 = V
OUT
VREF REGISTER = 255d
TS REGISTER = 127d
1.18
-40
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 7. ACCURACY vs TEMPERATURE (-40°C TO +85°C)
FIGURE 8. POWER ON
FN8091.0
December 14, 2006
8
ISL21400
Typical Performance Curves (Continued)
3
2
1
0
1.0
0.8
AT +25°C
0.6
0.4
0.2
0.0
AT +25°C
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
0
15 30 45 60 75 90 105120135150165180195210225240255
CODE
CODE
FIGURE 9. INL, V
AND TEMP SLOPE DAC
FIGURE 10. DNL, V
AND TEMP SLOPE DAC
REF
REF
1.4
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
At +25°C
TS REGISTER = 127d
VREF REGISTER = 255d
1.2
1.0
0.8
0.6
0.4
0.2
0.0
+85°C
-40°C
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
REGISTER CODE (m)
0
15 30 45 60 75 90 10512013515 0165180195210225240255
TS REGISTER CODE (n)
V
REF
FIGURE 11. V
vs V
CODE (m)
REF
FIGURE 12. V
OUT
vs TEMP SENSE CODE (n), T = -40°C AND
A
OUT
+85°C
1.209
1.208
1.207
1.206
1.205
1.204
1.203
1.202
1.201
1.2
VREF REGISTER = 255d
TS REGISTER = 127d
At +25°C
-1
-0.5
0
0.5
1
I
(mA)
OUT
FIGURE 13. V
vs I
(±1mA)
OUT
OUT
FN8091.0
December 14, 2006
9
ISL21400
Reference Sections
Referring to the Block Diagram on page 2, the V
Pin Descriptions
and
REF
V
OUT
Temperature Sense (V ) outputs are summed together (Σ)
TS
Programmable voltage output pin. Absolute voltage is
determined by device temperature and Equation 1. Drive
capability is limited to ±500μA output current and 5000pF
output capacitance.
and then passed through the output gain stage (A). The
voltage output is programmable and is determined by the
following equation:
⎧
⎨
⎩
⎫
⎬
⎭
n
255
(2 • m)–255
(EQ. 1)
---------
--------------------------------
+ V
TS
V
= A
•
V
•
OUT
V
REF
A2, A1, A0
255
Hardware slave address pins that can be used to provide
several ISL21400 with a unique physical address to allow for
multiple devices off one I C bus.
where
• A = 1, 2, 4
2
V
GND
• V
REF
= 1.200 (not temperature dependent)
This is the circuit ground pin. It is common for the V
control signal inputs.
and
OUT
• 0 ≤ n ≤ 255 (setting contained in Register 0, V
REF
)
• V = K(T-T )
TS
0
SDA
• K = dV / dT = -2.1mV/C
TS
Serial Data Input/Output. Bidirectional pin used for serial
data transfer. As an output, it is open drain and may be
wire-ored with any number of open drain or open collector
outputs. A pullup resistor is required and the value is
dependent on the speed of the serial data bus and the
number of outputs tied together.
• T = device temperature
• T = +25°C
0
• 0 ≤ m ≤ 255 (setting contained in Register 1, TS)
See the Applications Information for ways to use Equation 1
and methods for output voltage calculations.
SCL
Serial Clock Input. Accepts a clock signal for clocking serial
data into and out of the device. The SCL line requires a
pullup resistor whose value is dependent on the speed of the
serial clock bus and the number of inputs tied together.
DACs Section
The ISL21400 contains two 8-bit DACs whose registers can
be programmed via the I C serial bus. The DAC registers
are non-volatile such that the values are restored during the
2
V
power-up cycle of the device. One DAC (V
)is
REF
CC
dedicated to scale the bandgap voltage reference
(Temperature invariant) and the other DAC (V ) is
V
CC
Positive Power Supply. Connect to a voltage supply in the
TS
range of 2.7V<V <5.5V, with minimum noise and ripple. For
best performance, bypass with a 0.1µF capacitor to ground.
If the A gain is set to 4 and V
CC
dedicated to scale the Temperature Sensor. Both of these
DACs can determine the output voltage as defined by
Equation 1 (See Register Information).
approaches 5.0V, then
must be set to >5.2V for best output performance.
V
OUT
V
CC
Output Gain Amplifier Section
Functional Description
The ISL21400 contains an output gain amplifier (A) that is
2
programmed via the I C serial bus. The gain amplifier is the
Functional Overview
last stage before the output and therefore controls the
overall gain for the device. The gain can be programmed for
1x, 2x, or 4x amplification. This gain factor is used to
program the output voltage as determined by Equation 1
(See Register Description).
Refer to the Functional Block Diagram on page 2. The
ISL21400 provides a programmable output voltage which
combines both a temperature independent term and a
temperature dependent term. The temperature independent
term uses a bandgap voltage reference, and the
temperature dependent term uses a Proportional To
Absolute Temperature (PTAT) reference, or Temperature
Sensor. Each voltage source is scalable using two DACs via
There are 5 registers in the ISL21400 device, all nonvolatile
(see Table 2). All registers are accessible for reading or
writing through the I C serial bus.
2
2
the I C serial bus. The resulting output voltage can vary from
0V to over 5V and has a variable, programmable
Temperature Slope (TS).
FN8091.0
December 14, 2006
10
ISL21400
Register Descriptions
TABLE 1. ISL21400 REGISTER BIT MAP
D7
D0
Addr
(MSB)
D6
D5
D4
D3
D2
D1
(LSB)
0
1
2
3
4
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
REF
REF
REF
REF
REF
REF
REF
REF
TS7
D7
TS6
D6
TS5
D5
TS4
D4
TS3
D3
TS2
D2
TS1
TS0
GAIN1
D1
GAIN0
D0
D7
D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D1
D0
and the resulting output gain. Note that two states produce
the same gain (Gain 1:0 set to 01b and 10b) of x2.
TABLE 2. REGISTER DESCRIPTIONS
REG
NONVOLATILE
DESCRIPTION
Reference setting
The other 6 bits in the register can be used for general
purpose memory (nonvolatile) or left alone.
0
1
2
3
4
Y
Y
Y
Y
Y
Temperature Sensor setting
Gain and storage
Storage
Registers 3 and 4: general purpose data
(nonvolatile)
These two registers are one byte each and can be used for
general purpose nonvolatile memory.
Storage
2
Register 0: Bandgap Reference Gain (Nonvolatile)
I C Serial Interface
Register 0 sets the output voltage of the bandgap reference
The ISL21400 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL21400
operates as a slave device in all applications.
(V
). Referring to Equation 1, the number “n” is the setting
REF
from Register 0 as follows:
n
---------
, for n=0 to 255
V
•
REF
255
This term of Equation 1 can vary from 0 to 1.20V.
Register 1: Temperature Slope Gain (Nonvolatile)
2
All communication over the I C interface is conducted by
Register 1 sets the Temperature Slope (TS) of the
temperature sensor. Referring to Equation 1, the number “m”
is the setting from Register 1 as follows:
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 10). On power-up of the ISL21400 the SDA pin is in
the input mode.
(2 • m)–255
--------------------------------
V
TS
255
V
is the temperature dependent term and varies from
TS
+136mV at -40°C to -126mV at +85°C. The other term varies
from -1 to +1 and scales the temperature term before adding
2
All I C interface operations must begin with a START
to the V
portion.
REF
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL21400 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 10). A START condition is ignored during the power-
up sequence and during non-volatile write cycles for the
device.
Register 2: Device Gain and Storage (nonvolatile)
TABLE 3. REGISTER 2 OUTPUT GAIN (NONVOLATILE):
OUTPUT GAIN
GAIN1
GAIN0
OUTPUT GAIN, A
V
0
0
1
1
0
1
0
1
x 1
x 2
x 2
x 4
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 10) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode. A STOP condition at the end
of a write operation to a non-volatile byte initiates an internal
Register 2 contains 2 bits (2 LSB’s) which control the output
gain of the device. Table 3 shows the state of these two bits
FN8091.0
December 14, 2006
11
ISL21400
non-volatile write cycle. The device enters its standby state
when the internal, non-volatile write cycle is completed.
Read Operation
A Current Address Read operation is shown in Figure 13. It
consists of a minimum 2 bytes: a START followed by the ID
byte from the master with the R/W bit set to 1, then an ACK
followed by the data byte or bytes sent by the slave. The
master terminates the Read operation by not responding
with an ACK and then issuing a STOP condition. This
operation is useful if the master knows the current address
and desires to read one or more data bytes.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 11).
The ISL21400 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL21400 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A Random Address Read operation consists of a three byte
“dummy write” instruction followed by a Current Address
Read operation (See Figure 14). The master initiates the
operation issuing the following sequence: a START, the
identification byte with the R/W bit set to "0", an Address
Byte, a second START, and a second Identification byte with
the R/W bit set to "1". After each of the three bytes, the
ISL21400 responds with an ACK. The ISL21400 then
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the Read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 13).
A valid Identification Byte contains 0101 A2 A1 A0 as the
seven MSBs. The A2 A1 A0 bits must correspond to the
logic levels at those pins of the ISL21400 device. The LSB in
the Read/Write bit. Its value is “1” for a Read operation, and
“0” for a Write operation (See Table 4)
Write Operation
TABLE 4. IDENTIFICATION BYTE FORMAT
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial’s value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
Address 04h is the last valid data byte, higher addresses are
not available. Data from addresses higher than memory
location 04h will be invalid.
0
1
0
1
A2
A1
A0
R/W
(MSB)
(LSB)
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL21400 responds with an ACK. The master will then send
a STOP and at this time the device begins its internal non-
volatile write cycle. During this time, the device ignores
transitions at the SDA and SCL pins, and the SDA output is
at a high impedance state. When the internal non-volatile
write cycle is completed, the ISL21400 enters its standby
state (see Figure 12).
STOP conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte and
its associated ACK signal. If a STOP byte is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the ISL21400 resets itself without performing the
write. The contents of the array are not affected.
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection for the registers. A STOP
condition also acts as a protection for non-volatile memory.
During a Write sequence, the Data Byte is loaded into an
internal shift register as it is received. The presence of the
STOP condition after the rest of the bits are received then
triggers the non-volatile write.
FN8091.0
December 14, 2006
12
ISL21400
SCL
SDA
START
DATA
STABLE
DATA
CHANGE STABLE
DATA
STOP
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH
HIGH
SDA OUTPUT
FROM RECEIVER
START
ACK
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
SIGNALS FROM THE
S
T
O
P
IDENTIFICATION
BYTE WITH R/W = 0
MASTER
ADDRESS
BYTE
DATA
BYTE
R
T
SIGNAL AT SDA
0 1 0 1
A2 A1 A0
0
0 0 0 0 0
SIGNALS FROM THE
ISL21400
A
C
K
A
C
K
A
C
K
FIGURE 16. BYTE WRITE SEQUENCE
READ
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH R/W = 1
SIGNAL AT SDA
0 1 0 1 A2 A1 A0
1
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ DATA
BYTE
LAST READ DATA
BYTE
FIGURE 17. ADDRESS READ SEQUENCE
S
S
T
A
R
T
SIGNALS
FROM THE
MASTER
T
A
R
T
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH R/W = 0
IDENTIFICATION
BYTE WITH R/W = 1
ADDRESS
BYTE
0 1 0 1
A
A
A 0
0 0 0 0 0
0 1 0 1 A A A 1
SIGNAL AT SDA
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. RANDOM ADDRESS READ SEQUENCE
FN8091.0
December 14, 2006
13
ISL21400
with V
= 5.5V). The Resolution of V
(DC) control
OUT
Applications Information
CC
changes with A , so that with a 4.80V full scale output
V
Power-Up Considerations
(A = 4), the resolution is 4.80/255 or 18.8mV/bit. With
V
The ISL21400 has on-chip EEPROM memory storage for
the DAC and gain settings of the device. These settings
must be recalled correctly on power-up for proper operation.
Normally there are no issues with recall, although it is always
best to provide a smooth, glitch-free power-up waveform on
A = 1, the resolution is 4.7mV/bit.
V
TEMP SENSE CONTROL DISCUSSION
The equation above yields this expression, Equation 3, for
Temp Slope:
V
. Adding a small 0.1μF capacitor at the device V
will
CC
CC
V
(TS) = A • V • A
V TS TS
(EQ. 3)
OUT
help with power-up as well as V
load changes.
OUT
Noise Performance
Since V = K(T-T ), the slope term is dependent on the
TS
0
base temp slope of the device, K (-2.1mV/°C), and the gain
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
terms A and A . This gives a formula for the portion of
typically 90µV . The noise measurement is made with a
V
TS
P-P
V
at a specific temperature:
bandpass filter made of a 1 pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz
OUT
V
(TS)= A • K • A • (T – T )
(EQ. 4)
OUT
V
TS
0
bandwidth. Load capacitance up to 5000pF can be added
but will result in only marginal improvements in output noise
and transient response. The output stage of the ISL21400 is
not designed to drive heavily capacitive loads. For high
impedance loads, an R-C network can be added to filter high
frequency noise and preserve DC control.
The product A *A ranges from -4 to 4, so the Temperature
TS
V
Slope can range from -8.4 to +8.4mV/°C, which is
independent of the output DC voltage. The resolution of
Slope control is determined by this range (±8.4mV/°C) and
the gain terms, and will vary from 65.8μV/°C/bit (A = 4)
V
down to 16.2μV/°C/bit (A = 1).
V
Output Voltage Programming Considerations
At T = T = +25°C, V
OUT
(TS) = zero, no changes in A will
TS
0
Setting and controlling the output voltage of the ISL21400
can be done easily by breaking down the components into
temperature variant and invariant, and setting them
separately. Let’s use Equation (1) above to derive separate
Reference Output and Output Temp Slope equations:
cause a change in V
, and V will only vary with the
OUT OUT
V
(DC) control. As temperature increases or decreases,
OUT
from T = +25°C, V
will then change according to the
OUT
programmed Temp Slope.
In many cases a form of Equation 4 is needed which yields a
⎧
⎨
⎩
⎫
⎬
⎭
⎧
⎨
⎩
⎫
⎬
⎭
n
255
(2 • m) – 255
⎛
⎝
⎞
⎠
---------
----------------------------------
V
change with respect to temperature. By rearranging,
V
=
A
• V
•
+
A • V
V
•
OUT
we get:
OUT
V
REF
TS
255
= {A • V
• A
} + {A • V • A } ,Eq. 2
REF V TS
TS
V
REF
V
(TS)
OUT
----------------------------
V
(T)=
= A • K • A
,(in mV/°C)
TS
(EQ. 5)
Reference Term
+ Temp Slope Term
OUT
V
(T – T )
0
The first term controls the output DC value, and the second
term controls the Temp slope, where
EXAMPLE 1: PROGRAMMED TEMPERATURE
COMPENSATION EXAMPLE
n
255
---------
(ranges from 0 to 1)
A
A
=
The ISL21400 can easily compensate for known
REF
temperature drift by programming the device for the initial
setting and Tempco using standard equations and
(2 • m) – 255
⎛
⎝
⎞
⎠
----------------------------------
=
(ranges from -1 to +1)
V
OUT
TS
255
some simple steps. The accuracy of the final programmed
output will be limited to the data sheet specs (typically 1%
DC OUTPUT CONTROL DISCUSSION
accuracy for V
OUT
and Slope).
The equation above yields this expression, Equation 2, for
Reference output:
In this example, an N-channel MOSFET gate has a
-2.8mV/°C Tempco from -10°C to +85°C. A constant bias
drain current is desired, with a target Vgs range derived from
the data sheet of 2.5V to 3.5V at +25°C.
V
(DC) = A • V
• A
REF REF
(EQ. 2)
OUT
V
Note that the DC term is dependent on the 1.20V reference
voltage, which is constant, the overall gain, A , and the
Offset Setting: Using Equation 2 and targeting
V
V
= 3.0VDC,
OUT
Reference gain, A
. Since the product A * A ranges
REF
V
REF
V
(DC)= (A • V
• A
) = 3.00V
REF
from 0 to 4, the total reference DC output can range from
OUT
V
REF
V
= 1.20V
• A = 2.50
OS
0.0V to 4.8V. In order to get the 4.8V output, V must be
CC
greater than 4.8V by the output dropout plus any overhead
REF
A
V
for output loading (the specification for V
= 5.0V is listed
OUT
FN8091.0
December 14, 2006
14
ISL21400
Note that A
REF
varies from 0 to 1, so to get 2.40, A = 4.
V
Also, to solve for overall temp slope of the output:
2.50
4
n
255
6
0.8812mV ⁄ °C
872.5mV
-----------
---------
A(REF) =
= 0.625 =
---------------------------------------
• 10 = 1010ppm ⁄ °C
n = 159 decimal
= 9F hex
Note that Equation 1 can be used directly to solve for output
voltage at a given temperature, in this case +85°C:
Temperature Slope Setting: Using Equation 5, which can
solve for Slope directly:
⎧
⎨
⎩
⎫
⎬
⎭
n
255
(2 • m)–255
---------
--------------------------------
V
= A
•
V
•
+ K(T – T )
OUT
V
REF
0
255
V
A
(TS)= A • K • A
= –2.8mV ⁄ °C
PTAT
OUT
V
⎧
⎫
⎬
⎭
178
255
(2 • 74)–255
---------
---------------------------------
V
(85°C) = 1 • 1.20 •
+ (–0.0021)(85 – 25)
⎨
OUT
–2.8
4 • –2.1
255
⎩
--------------------
=
PTAT
= 0.8905V
(2 • m) – 255
----------------------------------
= 0.333 =
A
PTAT
255
Typical Applications Circuits
m = 170 decimal
= A9 hex
LDMOS RF Power Amplifier (RFPA). The ISL21400 is used
to set the gate bias for the LDMOS transistor in a single
stage of an RFPA. Normally this is done with a DAC or digital
potentiometer with some discrete temperature
The ISL21400 device can be programmed with these
calculated parameters and perform temperature
compensation circuitry. The ISL21400 simplifies this control
and allows a full range of DC bias and tempco control.
compensation or direct control in the target circuit. If
parameters change for some reason, then the device can be
reprogrammed with new values and the circuit retested.
A typical circuit can be calibrated for correct bias at room
temperature (+25°C) on power-up using a microcontroller or
EXAMPLE 2. CALCULATING THE V
SLOPE
TEMPERATURE
OUT
2
direct I C control. The temperature of the unit can then be
increased to the highest operating range, and the
Temperature Slope setting can then be adjusted to bring the
amplifier back to correct bias. Since the Temp Slope setting
has a negligible effect on the room temperature setting, the
amplifier will be biased correctly over the operating
temperature of the unit.
In some applications, it may be desirable to calculate what
the output voltage and temp slope are, given the
programmed register settings. Such an application could be
a closed loop system with internal calibration procedure. By
reading the registers of the ISL21400, then calculating the
V
parameters, the system characteristics can be
OUT
recorded.
For the example below, let’s determine the voltage output,
V
(DC) at +25°C, and also the change due to
OUT
temperature variation (ppm) from +25°C to +85°C.
Equations 2 and 5 above will be used to calculate the
answers.
Given, the contents of the registers:
A = 1
V
n = 178 decimal
m = 74 decimal
Using Equation 2:
V
(DC)= (A • V
• A
)
REF
OUT
V
REF
178
⎛
⎞
---------
=
1 • 1.20 •
⎝
⎠
255
= 0.8376V
Using Equation 5:
V
(T) = (A • K • A ) mV ⁄ °C
V TS
OUT
(2 • 74) – 255
------------------------------------
= 1 • –2.1 •
255
= 0.8812mV ⁄ °C
FN8091.0
December 14, 2006
15
ISL21400
+28V
U2
1
2
3
IN OUT
GND
+28V
+5V REGULATOR
8
7
4
5
6
1
2
2
VCC
SCL
SDA
I C BUS
R1
1k
R2
A0
A1
A2
VOUT
GND
L1
100
C1
3
100pF
ISL21400
RF OUTPUT
Q1
LDMOS
C2
RF INPUT
FIGURE 19. LDMOS RFPA BIAS CONTROL
FN8091.0
December 14, 2006
16
ISL21400
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8091.0
December 14, 2006
17
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