ISL22313_技术文档

ISL22313

®

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet

July 17, 2007

FN6421.0

2 ®

Low Noise, Low Power, I C Bus, 256 Taps

Features

The ISL22313 integrates a single digitally controlled

potentiometer (DCP), control logic and non-volatile memory

on a monolithic CMOS integrated circuit.

• 256 resistor taps

2

• I C serial interface

- Two address pins, up to four devices per bus

• Non-volatile EEPROM storage of wiper position

• 14 General Purpose non-volatile registers

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

2

I C bus interface. The potentiometer has an associated

• High reliability

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR) that can be directly written to and read by the

user. The contents of the WR control the position of the

wiper. At power up the device recalls the contents of the

DCP’s IVR to the WR.

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T≤+55°C

• Wiper resistance: 70Ω typical @ 1mA

• Standby current <2.5µA max

The ISL22313 also has 14 general purpose non-volatile

registers that can be used as storage of lookup table for

multiple wiper position or any other valuable information.

• Shutdown current <2.5µA max

• Dual power supply

- VCC = 2.25V to 5.5V

- V- = -2.25V to -5.5V

The ISL22313 features a dual supply, that is beneficial for

applications requiring a bipolar range for DCP terminals

between V- and VCC.

• DCP terminal voltage from V- to VCC

• 10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40 to +125°C

• 10 Lead MSOP

The DCP can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide variety of

applications including control, parameter adjustments, and

signal processing.

• Pb-free plus anneal product (RoHS compliant)

Pinout

ISL22313

(10 LD MSOP)

TOP VIEW

O

10

9

SCL

SDA

A1

VCC

1

2

3

4

5

RH

RW

8

7

A0

RL

V-

GND

6

Ordering Information

PART

RESISTANCE

TEMP.

NUMBER

PART

MARKING

OPTION

(kΩ)

RANGE

(°C)

PACKAGE

(Pb-Free)

(Notes 1, 2)

ISL22313TFU10Z

ISL22313UFU10Z

ISL22313WFU10Z

NOTES:

PKG. DWG. #

M10.118

313TZ

100

50

-40 to +125

10 Ld MSOP

313UZ

313WZ

10 Ld MSOP

M10.118

10

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL22313

Block Diagram

V-

V

CC

RH

SCL

SDA

A1

POWER UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

2

I C

WR

INTERFACE

VOLATILE

REGISTER

AND

A0

WIPER

CONTROL

CIRCUITRY

NON-VOLATILE

REGISTERS

RL

RW

GND

Pin Descriptions

MSOP PIN

SYMBOL

DESCRIPTION

2

1

2

SCL

SDA

A1

Open drain I C interface clock input

2

Open drain Serial data I/O for the I C interface

2

3

Device address input for the I C interface

2

4

A0

Device address input for the I C interface

5

V-

Negative supply pin

Device ground pin

6

GND

RL

7

“Low” terminal of DCP

“Wiper” terminal of DCP

“High” terminal of DCP

Power supply pin

8

RW

RH

9

10

VCC

FN6421.0

July 17, 2007

2

ISL22313

Absolute Maximum Ratings

Thermal Information

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

Thermal Resistance (Typical, Note 3)

θ

(°C/W)

120

JA

10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

CC

Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V

Voltage at any DCP Pin with

respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V

CC

Recommended Operating Conditions

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW

Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C

ESD

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V

CC

V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V

Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

MIN

TYP

MAX

SYMBOL

PARAMETER

RH to RL resistance

TEST CONDITIONS

(Note 18) (Note 4) (Note 18)

UNIT

kΩ

R

W option

U option

T option

10

50

TOTAL

kΩ

100

kΩ

RH to RL resistance tolerance

-20

V-

+20

%

End-to-End Temperature Coefficient

W option

±150

±50

ppm/°C

V

U, T option

V

, V

RH RL

DCP terminal voltage

Wiper resistance

V

and V to GND

RL

V

CC

RH

R

RH - floating, V = V-, force I current to

RL

the wiper, I = (V

70

10/10/25

0.1

250

Ω

W

- V )/R

W

CC

RL TOTAL

C /C /C

W

Potentiometer capacitance

Leakage on DCP pins

See Macro Model below.

pF

µA

H

L

(Note 16)

I

Voltage at pin from GND to V

@ RH; measured at RW, unloaded)

W option

1

LkgDCP

CC

VOLTAGE DIVIDER MODE (V- @ RL; V

CC

INL

Integral non-linearity

-1.5

±0.5

1.5

LSB

(Note 9)

(Note 5)

U, T option

W option

-1.0

±0.2

±0.4

1.0

DNL

Differential non-linearity

LSB

(Note 8)

(Note 5)

U, T option

W option

-0.5

0

±0.15

1

0.5

5

ZSerror

(Note 6)

Zero-scale error

Full-scale error

LSB

(Note 5)

U, T option

W option

0

0.5

-1

2

FSerror

(Note 7)

-5

-2

0

LSB

(Note 5)

U, T option

-1

0

TC

Ratiometric temperature coefficient

DCP register set to 80 hex

±4

ppm/°C

V

(Notes 10, 16)

FN6421.0

July 17, 2007

3

ISL22313

Analog Specifications Over recommended operating conditions unless otherwise stated. Limits are established by characterization.

(Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

-3dB cut off frequency

TEST CONDITIONS

(Note 18) (Note 4) (Note 18)

UNIT

kHz

f

Wiper at midpoint (80hex) W option (10k)

Wiper at midpoint (80hex) U option (50k)

Wiper at midpoint (80hex) T option (100k)

1000

250

cutoff

(Note 16)

120

RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 14)

Integral non-linearity

Differential non-linearity

Offset

W option

-3

±1.5

±0.3

±0.4

±0.15

1

3

MI

(Note 11)

U, T option

-1

1

MI

(Note 11)

RDNL

(Note 13)

W option

-1.5

-0.5

0

1.5

0.5

5

MI

(Note 11)

U, T option

MI

(Note 11)

Roffset

W option

MI

(Note 12)

(Note 11)

U, T option

0

0.5

2

MI

(Note 11)

TC

Resistance temperature coefficient

DCP register set between 32 hex and FF hex

±50

ppm/°C

R

(Notes 15, 16)

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

= +5.5V, V- = -5.5V, f = 400kHz;

SDA = Open; (for I C, active, read and write

states)

(Note 18) (Note 4) (Note 18)

UNIT

I

V

Supply Current (volatile

V

0.07

0.02

-0.18

-0.06

1

0.15

0.05

mA

CC1

CC

SCL

2

write/read)

V

= +2.25V, V- = -2.25V, f

SCL

SDA = Open; (for I C, active, read and write

= 400kHz;

mA

CC

2

states)

I

V- Supply Current (volatile write/read) V- = -5.5V, V

= +5.5V, f

CC SCL

SDA = Open; (for I C, active, read and write

states)

= 400kHz;

-1

V-1

2

V- = -2.25V, V

CC

SDA = Open; (for I C, active, read and write

= +2.25V, f

SCL

= 400kHz;

-0.4

2

states)

I

V

Supply Current (non-volatile

V = +5.5V, V- = -5.5V, f

CC SCL

SDA = Open; (for I C, active, read and write

= 400kHz;

2

CC2

CC

2

write/read)

states)

V

= +2.25V, V- = -2.25V, f

SCL

SDA = Open; (for I C, active, read and write

= 400kHz;

0.3

0.7

CC

2

states)

I

V- Supply Current (non-volatile

write/read)

V- = -5.5V, V

CC

SDA = Open; (for I C, active, read and write

= +5.5V, f

SCL

= 400kHz;

-2

-1.2

-0.4

V-2

2

states)

V- Supply Current (non-volatile

write/read)

V- = -2.25V, V

CC

SDA = Open; (for I C, active, read and write

= +2.25V, f

SCL

= 400kHz;

-0.7

2

states)

FN6421.0

July 17, 2007

4

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

= +5.5V, V- = -5.5V @ +85°C, I C

(Note 18) (Note 4) (Note 18)

UNIT

2

I

V

Current (standby)

V

0.2

1

1.5

2.5

1

µA

SB

CC

interface in standby state

2

V

= +5.5V, V- = -5.5V @ +125°C, I C

µA

µs

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +85°C, I C

0.1

0.5

-0.7

-3

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +125°C, I C

2

CC

interface in standby state

2

I

V- Current (standby)

V- = -5.5V, V

= +5.5V @ +85°C, I C

-2.5

-4

V-SB

CC

interface in standby state

2

V- = -5.5V, V

= +5.5V @ +125°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +85°C, I C

-1.5

-3

-0.3

-1

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +125°C, I C

CC

interface in standby state

2

I

V

Current (shutdown)

V

= +5.5V, V- = -5.5V @ +85°C, I C

0.2

1

1.5

2.5

1

SD

CC

interface in standby state

2

V

= +5.5V, V- = -5.5V @ +125°C, I C

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +85°C, I C

0.1

0.5

-0.7

-3

CC

interface in standby state

2

V

= +2.25V, V- = -2.25V @ +125°C, I C

2

CC

interface in standby state

2

I

V- Current (standby)

V- = -5.5V, V

= +5.5V @ +85°C, I C

-2.5

-4

V-SB

CC

interface in standby state

2

V- = -5.5V, V

= +5.5V @ +125°C, I C

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +85°C, I C

-1.5

-3

-0.3

-1

CC

interface in standby state

2

V- = -2.25V, V

= +2.25V @ +125°C, I C

CC

interface in standby state

I

Leakage current, at pins A0, A1, SDA, Voltage at pin from GND to V

and SCL

-1

1

LkgDig

CC

t

DCP wiper response time

SCL falling edge of last bit of DCP data byte

to wiper new position

1.5

DCP

(Note 16)

t

DCP recall time from shutdown mode SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

µs

ShdnRec

(Note 16)

Vpor

Power-on recall voltage

ramp rate

Minimum V

at which memory recall occurs

1.9

0.2

2.1

5

V

CC

VCC Ramp

V

V/ms

ms

CC

t

Power-up delay

V

above Vpor, to DCP Initial Value

CC

D

2

Register recall completed, and I C Interface

in standby state

EEPROM SPECIFICATION

EEPROM Endurance

1,000,000

50

Cycles

Years

ms

EEPROM Retention

Temperature T ≤ +55°C

t

Non-volatile Write cycle time

12

20

WC

(Note 17)

FN6421.0

July 17, 2007

5

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 18) (Note 4) (Note 18)

UNIT

SERIAL INTERFACE SPECS

V

A1, A0, SDA, and SCL input buffer

LOW voltage

-0.3

0.3*V

V

IL

CC

V

A1, A0, SDA, and SCL input buffer

HIGH voltage

0.7*V

V

+ 0.

CC

IH

CC

3

Hysteresis SDA and SCL input buffer hysteresis

(Note 16)

0.05*V

0

V

CC

V

SDA output buffer LOW voltage,

0.4

10

V

OL

(Note 16) sinking 4mA

Cpin

A1, A0, SDA, and SCL pin

pF

(Note 16) capacitance

f

SCL frequency

Pulse width suppression time at SDA Any pulse narrower than the max spec is

400

50

kHz

ns

SCL

t

sp

and SCL inputs suppressed

t

SCL falling edge to SDA output data SCL falling edge crossing 30% of V , until

CC

900

ns

AA

(Note 16) valid

SDA exits the 30% to 70% of V

window

CC

t

Time the bus must be free before the SDA crossing 70% of V

during a STOP

1300

BUF

(Note 16) start of a new transmission

CC

condition, to SDA crossing 70% of V

CC

during the following START condition

t

Clock LOW time

Measured at the 30% of V

Measured at the 70% of V

crossing

1300

600

ns

LOW

CC

t

Clock HIGH time

HIGH

CC

t

START condition setup time

SCL rising edge to SDA falling edge; both

crossing 70% of V

600

SU:STA

HD:STA

SU:DAT

CC

From SDA falling edge crossing 30% of V

t

START condition hold time

Input data setup time

600

100

ns

CC

to SCL falling edge crossing 70% of V

CC

From SDA exiting the 30% to 70% of V

CC

window, to SCL rising edge crossing 30% of

V

CC

t

Input data hold time

From SCL rising edge crossing 70% of V

0

ns

HD:DAT

CC

to SDA entering the 30% to 70% of V

window

CC

t

STOP condition setup time

From SCL rising edge crossing 70% of V

to SDA rising edge crossing 30% of V

,

600

1300

0

ns

SU:STO

CC

t

STOP condition hold time for read, or From SDA rising edge to SCL falling edge;

volatile only write

HD:STO

both crossing 70% of V

CC

t

Output data hold time

From SCL falling edge crossing 30% of V

,

DH

(Note 16)

CC

until SDA enters the 30% to 70% of V

window

t

SDA and SCL rise time

From 30% to 70% of V

20 +

0.1 * Cb

250

400

ns

R

CC

(Note 16)

t

SDA and SCL fall time

From 70% to 30% of V

20 +

0.1 * Cb

F

CC

(Note 16)

Cb

(Note 16)

Capacitive loading of SDA or SCL

Total on-chip and off-chip

10

pF

kΩ

Rpu

SDA and SCL bus pull-up resistor

Maximum is determined by t and t

R F

1

(Note 16) off-chip

For Cb = 400pF, max is about 2kΩ~2.5kΩ

For Cb = 40pF, max is about 15kΩ~20kΩ

FN6421.0

July 17, 2007

6

ISL22313

Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by

characterization. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

A1 and A0 setup time

A1 and A0 hold time

TEST CONDITIONS

Before START condition

After STOP condition

(Note 18) (Note 4) (Note 18)

UNIT

ns

t

600

SU:A

t

ns

HD:A

NOTES:

4. Typical values are for T = +25°C and 3.3V supply voltage.

A

5. LSB: [V(R

)

– V(R ) ]/255. V(R

)

and V(R ) are V(R ) for the DCP register set to FF hex and 00 hex respectively. LSB is the

W 0

W 255

W 0 W 255

W

incremental voltage when changing from one tap to an adjacent tap.

6. ZS error = V(RW) /LSB.

0

7. FS error = [V(RW)

– V ]/LSB.

CC

255

8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

9. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255

i

0

Max(V(RW) ) – Min(V(RW) )

6

10

i

10.

for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

--------------------------------------------------------------------------------------------- ----------------

TC

=

×

V

+

i

11. MI = |RW

– RW |/255. MI is a minimum increment. RW

and RW are the measured resistances for the DCP register set to FF hex and

255 0

255

0

00 hex respectively.

12. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

255

13. RDNL = (RW – RW )/MI -1, for i = 16 to 255.

i-1

i

14. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.

i

0

6

15.

for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is

the minimum value of the resistance over the temperature range.

[Max(Ri) – Min(Ri)]

10

--------------------------------------------------------------- ----------------

165°C

[Max(Ri) + Min(Ri)] ⁄ 2 +

TC

=

×

R

16. Limits should be considered typical and are not production tested.

2

17. t is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-volatile

WC

write cycle.

18. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.

DCP Macro Model

R

TOTAL

RH

RL

C

L

C

H

C

W

10pF

25pF

RW

SDA vs SCL Timing

t

sp

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

FN6421.0

July 17, 2007

7

ISL22313

A0 and A1 Pin Timing

STOP

START

SCL

CLK 1

SDA

t

HD:A

SU:A

A0, A1

Typical Performance Curves

80

2.0

1.5

1.0

0.5

0

T = +125ºC

70

60

50

40

30

20

10

0

T = +25ºC

I

CC

-0.5

-1.0

-1.5

-2.0

I

V-

T = -40ºC

0

50

100

150

200

250

-40

0

40

TEMPERATURE (°C)

80

120

TAP POSITION (DECIMAL)

FIGURE 2. STANDBY I

AND I vs TEMPERATURE

V-

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 10kΩ (W)

CC

CC TOTAL

0.50

0.25

0

V

= 5.5V

CC

T = +25ºC

V

= 2.25V

CC

0.25

0

-0.25

-0.50

-0.25

-0.50

V

= 5.5V

V

= 2.25V

100

CC

100

TAP POSITION (DECIMAL)

CC

0

50

150

200

250

0

50

150

200

250

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

FN6421.0

July 17, 2007

8

ISL22313

Typical Performance Curves (Continued)

2.0

0

10k

1.6

1.2

-1

-2

V

= 2.25V

CC

50k

V

= 5.5V

CC

0.8

50k

-3

-4

10k

V

= 2.25V

V

= 5.5V

CC

0.4

0

-5

-40

0

40

80

120

-40

0

40

TEMPERATURE (ºC)

80

120

TEMPERATURE (ºC)

FIGURE 5. ZS ERROR vs TEMPERATURE

FIGURE 6. FS ERROR vs TEMPERATURE

2.0

0.5

0.25

0

T = +25ºC

V

= 5.5V

1.5

1.0

CC

V

= 2.25V

CC

0.5

0

-0.25

-0.50

V

= 2.25V

100

CC

V

= 5.5V

CC

50

-0.5

0

100

150

200

250

0

50

150

200

250

TAP POSITION (DECIMAL)

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR

10kΩ (W)

200

1.60

10k

160

1.20

10k

120

80

0.80

5.5V

0.40

0.00

50k

40

50k

2.25V

0

-0.40

16

66

116

166

216

266

-40

0

40

80

120

TAP POSITION (DECIMAL)

TEMPERATURE (ºC)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. END TO END R

TOTAL

% CHANGE vs

TEMPERATURE

FN6421.0

July 17, 2007

9

ISL22313

Typical Performance Curves (Continued)

500

INPUT

OUTPUT

10k

400

300

200

50k

100

WIPER AT MID POINT (POSITION 80h)

= 10kΩ

R

TOTAL

0

16

66

116

166

216

TAP POSITION (DECIMAL)

FIGURE 12. FREQUENCY RESPONSE (1MHz)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

CS

SCL

WIPER UNLOADED,

WIPER

MOVEMENT FROM 0h to FFh

FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h

FIGURE 14. LARGE SIGNAL SETTLING TIME

Bus Interface Pins

Pin Description

Serial Data Input/Output (SDA)

Potentiometers Pins

2

The SDA is a bidirectional serial data input/output pin for I C

interface. It receives device address, operation code, wiper

RH and RL

The high (RH) and low (RL) terminals of the ISL22313 are

equivalent to the fixed terminals of a mechanical

potentiometer. RH and RL are referenced to the relative

position of the wiper and not the voltage potential on the

terminals. With WR set to 255 decimal, the wiper will be

closest to RH, and with the WR set to 0, the wiper is closest

to RL.

2

address and data from an I C external master device at the

rising edge of the serial clock SCL, and it shifts out data after

each falling edge of the serial clock.

SDA requires an external pull-up resistor, since it is an open

drain input/output.

Serial Clock (SCL)

2

RW

This input is the serial clock of the I C serial interface. SCL

requires an external pull-up resistor, since it is an open drain

input.

RW is the wiper terminal, and it is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WR register.

FN6421.0

July 17, 2007

10

ISL22313

Device Address (A1, A0)

Memory Description

The address inputs are used to set the least significant 2 bits

of the 7-bit I C interface slave address. A match in the slave

The ISL22313 contains one non-volatile 8-bit Initial Value

Register (IVR), fourteen General Purpose non-volatile 8-bit

registers and two volatile 8-bit registers: Wiper Register (WR)

and Access Control Register (ACR). Memory map of ISL22313

is in Table 1. The non-volatile register (IVR) at address 0,

contains initial wiper position and volatile register (WR) contains

current wiper position.

2

address serial data stream must match with the Address

input pins in order to initiate communication with the

ISL22313. A maximum of four ISL22313 devices may

2

occupy the I C serial bus (see Table 3).

Principles of Operation

TABLE 1. MEMORY MAP

The ISL22313 is an integrated circuit incorporating one DCP

with its associated registers, non-volatile memory and an I C

ADDRESS

2

(hex)

10

F

NON-VOLATILE

VOLATILE

serial interface providing direct communication between a

host and the potentiometer and memory. The resistor array

is comprised of individual resistors connected in series. At

either end of the array and between each resistor is an

electronic switch that transfers the potential at that point to

the wiper.

N/A

ACR

Reserved

E

D

C

B

A

9

General Purpose

IVR

N/A

WR

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions.

When the device is powered down, the last value stored in

IVR will be maintained in the non-volatile memory. When

power is restored, the contents of the IVR are recalled and

loaded into the WR to set the wiper to the initial value.

8

7

DCP Description

6

The DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each

DCP are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RL pins). The RW pin of the DCP is

connected to intermediate nodes, and is equivalent to the

wiper terminal of a mechanical potentiometer. The position

of the wiper terminal within the DCP is controlled by an 8-bit

volatile Wiper Register (WR). When the WR of a DCP

contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW)

is closest to its “Low” terminal (RL). When the WR register of

a DCP contains all ones (WR[7:0]= FFh), its wiper terminal

(RW) is closest to its “High” terminal (RH). As the value of

the WR increases from all zeroes (0) to all ones (255

decimal), the wiper moves monotonically from the position

closest to RL to the position closest to RH. At the same time,

the resistance between RW and RL increases monotonically,

while the resistance between RH and RW decreases

monotonically.

5

4

3

2

1

0

The non-volatile IVR and volatile WR registers are

accessible with the same address.

The Access Control Register (ACR) contains information

and control bits described below in Table 2.

The VOL bit (ACR[7]) determines whether the access to

wiper registers WR or initial value registers IVR.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT #

7

6

5

4

0

3

0

2

0

1

0

While the ISL22313 is being powered up, the WR is reset to

80h (128 decimal), which locates RW roughly at the center

between RL and RH. After the power supply voltage

becomes large enough for reliable non-volatile memory

reading, the WR will be reloaded with the value stored in a

non-volatile Initial Value Register (IVR).

NAME

VOL

SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If

VOL bit is 1, only the volatile WR is accessible. Note: Value

is written to IVR register also is written to the WR. The

default value of this bit is 0.

The WR and IVR can be read or written to directly using the

I C serial interface as described in the following sections.

The SHDN bit (ACR[6]) disables or enables Shutdown mode.

When this bit is 0, i.e. DCP is forced to end-to-end open

circuit and RW is shorted to RL as shown on Figure 15.

Default value of the SHDN bit is 1.

2

FN6421.0

July 17, 2007

11

ISL22313

2

All I C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL22313 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (see

Figure 16). A START condition is ignored during the power-

up of the device.

RH

RW

RL

2

All I C interface operations must be terminated by a STOP

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (see Figure 16). A STOP condition at the end

of a read operation, or at the end of a write operation places

the device in its standby mode.

The WIP bit (ACR[5]) is a read-only bit. It indicates that non-

volatile write operation is in progress. It is impossible to write

to the WR or ACR while WIP bit is 1.

2

An ACK (Acknowledge) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (see Figure 17).

I C Serial Interface

2

The ISL22313 supports an I C bidirectional bus oriented

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and

the device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL22313

operates as a slave device in all applications.

The ISL22313 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22313 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

2

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

A valid Identification Byte contains 10100 as the five MSBs,

and the following two bits matching the logic values present

at pins A1 and A0. The LSB is the Read/Write bit. Its value is

“1” for a Read operation and “0” for a Write operation (see

Table 3).

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 16). On power-up of the ISL22313, the SDA pin is in

the input mode.

TABLE 3. IDENTIFICATION BYTE FORMAT

LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY

1

0

1

0

A1

A0

R/W

(MSB)

(LSB)

SCL

SDA

START

DATA

STOP

STABLE

CHANGE STABLE

FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS

FN6421.0

July 17, 2007

12

ISL22313

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

SIGNALS FROM

THE MASTER

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 0 1 0 0 A1A0 0

0 0 0 0

SIGNALS FROM

THE SLAVE

A

C

K

A

C

K

A

C

K

FIGURE 18. BYTE WRITE SEQUENCE

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

A

C

K

A

C

K

IDENTIFICATION

BYTE WITH

R/W = 0

IDENTIFICATION

BYTE WITH

R/W = 1

A

C

K

ADDRESS

BYTE

SIGNAL AT SDA

1 0 1 0 0A1A0 0

0 0 0 0

1 0

1

0 A1A0 1

0

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 19. READ SEQUENCE

Write Operation

Read Operation

A Read operation consist of a three byte instruction followed

by one or more Data Bytes (see Figure 19). The master

initiates the operation issuing the following sequence: a

START, the Identification byte with the R/W bit set to “0”, an

Address Byte, a second START, and a second Identification

byte with the R/W bit set to “1”. After each of the three bytes,

the ISL22313 responds with an ACK. Then the ISL22313

transmits Data Bytes as long as the master responds with an

ACK during the SCL cycle following the eighth bit of each

byte. The Data Bytes are from the registers indicated by an

internal pointer. This pointer initial value is determined by the

Address Byte in the Read operation instruction, and

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL22313 responds with an ACK. At this time, the device

enters its standby state (see Figure 18).

The non-volatile write cycle starts after STOP condition is

determined and it requires up to 20ms delay for the next

non-volatile write. Thus, non-volatile registers must be

written individually.

FN6421.0

July 17, 2007

13

ISL22313

increments by one during transmission of each Data Byte.

After reaching the memory location 0Fh, the pointer “rolls

over” to 00h, and the device continues to output data for

each ACK received.The master terminates the read

operation issuing a NACK (ACK ) and a STOP condition

following the last bit of the last Data Byte (see Figure 19).

Applications Information

When stepping up through each tap in voltage divider mode,

some tap transition points can result in noticeable voltage

transients (or overshoot/undershoot) resulting from the

sudden transition from a very low impedance “make” to a

much higher impedance “break within an extremely short

period of time (<50ns). Two such code transitions are EFh to

F0h, and 0Fh to 10h. Note that all switching transients will

settle well within the settling time as stated in the datasheet.

A small capacitor can be added externally to reduce the

amplitude of these voltage transients, but that will also

reduce the useful bandwidth of the circuit, thus this may not

be a good solution for some applications. It may be a good

idea, in that case, to use fast amplifiers in a signal chain for

fast recovery.

FN6421.0

July 17, 2007

14

ISL22313

Mini Small Outline Plastic Packages (MSOP)

N

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

E1

E

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

-B-

0.20 (0.008)

INDEX

AREA

A

A1

A2

b

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-

1 2

A

B

C

-

TOP VIEW

-

4X θ

0.25

(0.010)

R1

9

R

GAUGE

PLANE

c

-

D

3

SEATING

PLANE

E1

e

4

L

-C-

4X θ

0.020 BSC

0.50 BSC

-

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

SEATING

PLANE

L

6

0.10 (0.004)

-A-

C

L1

N

0.037 REF

10

0.95 REF

10

-

b

-H-

A1

7

e

D

R

0.003

-

0.07

-

0.20 (0.008)

C

R1

θ

-

a

SIDE VIEW

o

C

L

5

15

5

15

-

o

E

1

0

6

0

6

-

α

-B-

0.20 (0.008)

C

D

END VIEW

Rev. 0 12/02

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6421.0

July 17, 2007

15


型号：	ISL22313
厂家：	Intersil
描述：	Single Digitally Controlled Potentiometer XDCP 单数字控制电位器XDCP 电位器
文件：	总15页 (文件大小：618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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