ISL22416UFU10Z [INTERSIL]
Single Digitally Controlled Potentiometer; 单数字控制电位器
| 型号： | ISL22416UFU10Z |
| 厂家： | 
Intersil |
| 描述： | Single Digitally Controlled Potentiometer |
| 文件： | 总13页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL22416
®
Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
®
June 23, 2006
FN6227.0
Low Noise, Low Power, SPI Bus, 128 Taps
Features
The ISL22416 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
• 128 resistor taps
• SPI serial interface
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the WR.
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
- Register data retention: 50 years @ T ≤ 55 °C
• 10 Lead MSOP
• Pb-free plus anneal product (RoHS compliant)
Pinout
ISL22416
(10 LD MSOP)
TOP VIEW
10
9
SCK
SDO
SDI
VCC
1
2
3
4
5
RH
RW
8
7
CS
RL
SHDN
GND
6
Ordering Information
RESISTANCE OPTION
TEMP. RANGE
PART NUMBER
PART MARKING
416UZ
(kΩ)
(°C)
PACKAGE
10 Ld MSOP
PKG. DWG. #
ISL22416UFU10Z
(Notes 1, 2)
50
10
-40 to +125
M10.118
(Pb-Free)
ISL22416WFU10Z
(Notes 1, 2)
416WZ
-40 to +125
10 Ld MSOP
(Pb-Free)
M10.118
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22416
Block Diagram
V
CC
SCK
SDO
SDI
RH
Power up
Interface,
Control
and
Status
Logic
SPI
INTERFACE
CS
RW
RL
WR
IVR
Non-volatile
Register
SHDN
GND
Pin Descriptions
MSOP PIN
SYMBOL
DESCRIPTION
1
2
SCK
SDO
SDI
SPI interface clock input
Push-pull/Open Drain Data Output of the SPI serial interface
Data Input of the SPI serial interface
Chip Select active low input
Shutdown active low input
Device ground pin
3
4
CS
5
SHDN
GND
RL
6
7
“Low” terminal of DCP
8
RW
“Wiper” terminal of DCP
9
RH
“High” terminal of DCP
10
V
Power supply pin
CC
FN6227.0
June 23, 2006
2
ISL22416
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
120
JA
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to V
Recommended Operating Conditions
CC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
I
W
Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C
ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CC
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.
Analog Specifications Over recommended operating conditions unless otherwise stated.
TYP
SYMBOL
PARAMETER
to R Resistance
TEST CONDITIONS
MIN
(NOTE 5)
MAX
UNIT
kΩ
R
R
R
W option
U option
10
50
TOTAL
H
H
L
kΩ
to R Resistance Tolerance
-20
+20
%
L
End-to-End Temperature Coefficient
W option
U option
±50
±80
70
ppm/°C
(Note 19)
ppm/°C
(Note 19)
R
Wiper Resistance
V
V
= 3.3V @ 25°C, wiper current =
200
Ω
W
CC
/R
CC TOTAL
and V to GND
V
, V
RH RL
V
and V Terminal Voltages
RL
V
0
V
V
RH
RH
RL
CC
C /C /C
W
(Note 19)
Potentiometer Capacitance
10/10/25
0.1
pF
H
L
I
Leakage on DCP Pins
Voltage at pin from GND to V
1
1
µA
LkgDCP
CC
VOLTAGE DIVIDER MODE (0V @ R ; V
@ R ; measured at R , unloaded)
H W
L
CC
INL
(Note 10)
Integral Non-linearity
Differential Non-linearity
Zero-scale Error
-1
LSB
(Note 6)
DNL
(Note 9)
Monotonic over all tap positions
-0.5
0.5
LSB
(Note 6)
ZSerror
(Note 7)
W option
U option
W option
U option
0
0
1
0.5
-1
5
2
0
0
LSB
(Note 6)
FSerror
(Note 8)
Full-scale Error
-5
-2
LSB
(Note 6)
-1
TC
Ratiometric Temperature Coefficient
DCP register set to 40 hex for W and U
option
±4
ppm/°C
V
(Note 11, 19)
RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)
W
L
H
W
H
L
RINL
(Note 15)
Integral Non-linearity
DCP register set between 10 hex and 70 hex;
monotonic over all tap positions;
W and U option
-1
1
MI
(Note 12)
RDNL
Differential Non-linearity
W option
-1
1
MI
(Note 14)
(Note 12)
U option
-0.5
0.5
MI
(Note 12)
FN6227.0
June 23, 2006
3
ISL22416
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(NOTE 5)
MAX
UNIT
Roffset
(Note 13)
Offset
W option
U option
0
1
5
MI
(Note 12)
0
0.5
2
MI
(Note 12)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(NOTE 5)
MAX
UNIT
I
V
Supply Current (volatile
f = 5MHz; (for SPI Active, Read and
SCK
0.5
mA
CC1
CC
write/read)
Volatile Write states only)
I
V
Supply Current (non-volatile
f
= 5MHz; (for SPI Active, Read and
3
5
7
3
5
3
5
2
4
1
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC2
CC
write/read)
SCK
Non-volatile Write states only)
I
V
Current (standby)
V
= +5.5V @ +85°C, SPI interface in
SB
CC
CC
standby state
V
= +5.5V @ +125°C, SPI interface in
CC
standby state
V
= +3.6V @ +85°C, SPI interface in
CC
standby state
V
= +3.6V @ +125°C, SPI interface in
CC
standby state
I
V
Current (shutdown)
V
= +5.5V @ +85°C, SPI interface in
SD
CC
CC
standby state
V
= +5.5V @ +125°C, SPI interface in
CC
standby state
V
= +3.6V @ +85°C, SPI interface in
CC
standby state
V
= +3.6V @ +125°C, SPI interface in
CC
standby state
I
Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to V
SDI, SDO and CS
-1
LkgDig
CC,
SDO is inactive
t
Wiper Response Time
Wiper Response Time after SPI write to WR
register
1.5
1.5
1.5
WRT
(Note 17)
t
DCP Recall Time from Shutdown
From rising edge of SHDN signal to wiper
stored position and RH connection
µs
ShdnRec
(Note 19) Mode
SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection
µs
V
Power-on Recall Voltage
Ramp Rate
Minimum V
CC
at which memory recall occurs
2.0
0.2
2.6
3
V
POR
V
Ramp
V
V/ms
ms
CC
CC
t
Power-up Delay
V
above V
, to DCP Initial Value
POR
D
CC
Register recall completed, and SPI Interface
in standby state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T ≤ 55 °C
t
Non-volatile Write Cycle Time
12
20
WC
(Note 17)
SERIAL INTERFACE SPECIFICATIONS
V
SHDN, SCK, SDI, and CS Input Buffer
LOW Voltage
-0.3
0.3*V
CC
V
V
IL
V
SHDN, SCK, SDI, and CS Input Buffer
HIGH Voltage
0.7*V
V
+0.3
IH
CC
CC
FN6227.0
June 23, 2006
4
ISL22416
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(NOTE 5)
MAX
UNIT
Hysteresis SHDN, SCK, SDI, and CS Input Buffer
Hysteresis
0.05*
V
V
CC
0
V
SDO Output Buffer LOW Voltage
SDO Pull-up Resistor Off-chip
I
= 4mA
0.4
2
V
OL
OL
R
Maximum is determined by t
and t with
FO
kΩ
pu
RO
maximum bus load Cb = 30pF, f
(Note 18)
= 5MHz
SCK
Cpin
SHDN, SCK, SDI, SDO and CS Pin
10
5
pF
(Note 19) Capacitance
f
SPI Frequency
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCK
t
SPI Clock Cycle Time
SPI Clock High Time
200
100
100
250
250
50
CYC
t
WH
t
SPI Clock Low Time
WL
t
Lead Time
LEAD
t
Lag Time
LAG
t
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Valid Time
SDO Output Hold Time
SDO Output Rise Time
SDO Output Fall Time
CS Deselect Time
SU
t
50
H
t
10
RI
t
10
20
FI
t
0
100
350
DIS
t
V
t
0
2
HO
RO
t
R
= 2k, Cbus = 30pF
= 2k, Cbus = 30pF
60
60
pu
t
t
R
pu
FO
CS
Notes:
5. Typical values are for T = 25°C and 3.3V supply voltage.
A
6. LSB: [V(R
)
– V(R ) ]/127. V(R
)
and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
W 0
W 127
W 0 W 127
W
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW) /LSB.
0
8. FS error = [V(RW)
127
– V ]/LSB.
CC
9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.
i-1
i
10. INL = [V(RW) – (i • LSB) – V(RW) ]/LSB for i = 1 to 127
i
0
Max(V(RW) ) – Min(V(RW) )
6
10
i
i
11.
for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper
[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
--------------------------------------------------------------------------------------------- ----------------
TC
=
×
V
i
i
12. MI = |RW
– RW |/127. MI is a minimum increment. RW
and RW are the measured resistances for the DCP register set to 7F hex and
127 0
127
0
00 hex respectively.
13. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
127
14. RDNL = (RW – RW )/MI -1, for i = 1 to 127.
i
i-1
15. RINL = [RW – (MI • i) – RW ]/MI, for i = 1 to 127.
i
0
6
16.
for i = 16 to 127, T = -40°C to 125°C. Max( ) is the maximum value of the resistance and Min ( ) is
the minimum value of the resistance over the temperature range.
[Max(Ri) – Min(Ri)]
[Max(Ri) + Min(Ri)] ⁄ 2
10
--------------------------------------------------------------- ----------------
TC
=
×
R
165°C
17. t
is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
WC
18. R is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
pu
19. This parameter is not 100% tested.
FN6227.0
June 23, 2006
5
ISL22416
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SDI
High Impedance
SDO
Output Timing
CS
SCK
SDO
SDI
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
XDCP Timing (for All Load Instructions)
CS
t
WC
SCK
...
...
t
WRT
MSB
LSB
SDI
V
W
High Impedance
SDO
FN6227.0
June 23, 2006
6
ISL22416
Typical Performance Curves
100
1.4
1.2
1
Vcc = 3.3V, T = 125ºC
90
80
70
60
50
40
30
T=125ºC
0.8
0.6
0.4
0.2
0
Vcc = 3.3V, T = -40ºC
Vcc = 3.3V, T = 20ºC
20
10
0
T=25ºC
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
TAP POSITION (DECIMAL)
Vcc, V
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10kΩ (W)
FIGURE 2. STANDBY I
vs V
CC
CC
CC TOTAL
0.2
0.1
0
0.2
0.1
0
T = 25ºC
Vcc = 2.7V
T = 25ºC
Vcc =2.7V
-0.1
-0.2
-0.1
-0.2
Vcc = 5.5V
Vcc = 5.5V
20 40
0
60
80
100
120
0
20
40
60
80
100
120
TAP POSITION(DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
MODE FOR 10kΩ (W)
0.00
1.30
10k
1.10
0.90
0.70
-0.30
Vcc = 2.7V
50k
10k
Vcc = 5.5V
-0.60
-0.90
-1.20
-1.50
Vcc =2.7V
0.50
0.30
Vcc =5.5V
0.10
50k
-0.10
-0.30
-40 -20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100 120
TEMPERATURE(ºC)
TEMPERATURE (ºC)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
FN6227.0
June 23, 2006
7
ISL22416
Typical Performance Curves (Continued)
0.4
0.2
0
0.4
T = 25ºC
T = 25º C
0.2
0
Vcc = 5.5V
-0.2
-0.2
-0.4
-0.6
Vcc =5.5V
Vcc =2.7V
Vcc = 2.7V
-0.4
-0.6
16
36
56
76
96
116
16
36
56
76
96
116
TAPPOSITION(DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR
10kΩ (W)
10kΩ (W)
1.00
105
50k
90
Vcc = 2.7V
10k
0.50
0.00
75
60
45
30
-0.50
50k
Vcc = 5.5V
10k
15
0
-1.00
-40
-20
0
20
40
60
80
100 120
16
36
56
76
96
TAP POSITION (DECIMAL)
TEMPERATURE(ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FOR
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
10kΩ (W)
OUTPUT
INPUT
300
250
200
150
100
50
10k
50k
Wiper at Mid Point (position 40h)
= 9.5kΩ
R
TOTAL
0
16
36
56
76
96
TAP POSITION(DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
FIGURE 11. TC FOR Rheostat MODE IN ppm FOR 50kΩ (U)
FN6227.0
June 23, 2006
8
ISL22416
Typical Performance Curves (Continued)
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Description
Potentiometer Pins
RH and RL
Bus Interface Pins
Serial Clock (SCK)
This is the serial clock input of the SPI serial interface.
The high (RH) and low (RL) terminals of the ISL22416 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 127 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.
Serial Data Output (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
Serial Data Input (SDI)
RW
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RH and shorts RW to RL. When SHDN is
returned to logic high, the previous latch settings put RW at
the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. SPI interface is
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.
Chip Select (CS)
CS LOW enables the ISL22416, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22416 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
RH
The ISL22416 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
FN6227.0
June 23, 2006
9
ISL22416
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
0
BIT
NAME
VOL SHDN WIP
DCP Description
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 7-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (127
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically OR’d with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. The WIP bit can
be read repeatedly after a non-volatile write to determine if
the write has been completed. It is impossible to write to the
WR or ACR while WIP bit is 1.
SPI Serial Interface
The ISL22416 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22416. SCK and CS lines are
controlled by the host or master. The ISL22416 operates
only as a slave device.
While the ISL22416 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a non-
volatile Initial Value Register (IVR).
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22416 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
TABLE 3. IDENTIFICATION BYTE FORMAT
The ISL22416 contains one non-volatile 7-bit register, known
as the Initial Value Register (IVR), volatile 7-bit Wiper
Register (WR), and volatile 8-bit Access Control Register
(ACR). The memory map of ISL22416 is on Table 1. The
non-volatile register (IVR) at address 0, contain initial wiper
position and volatile registers (WR) contain current wiper
position.
0
1
0
1
0
0
0
0
(MSB)
(LSB)
The next byte sent to the ISL22416 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 4).
TABLE 1. MEMORY MAP
TABLE 4. IDENTIFICATION BYTE FORMAT
ADDRESS
NON-VOLATILE
VOLATILE
7
6
5
4
3
0
2
0
1
0
2
1
0
—
ACR
I3
I2
I1
I0
R1
R0
Reserved
IVR
WR
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
There are only two registers address possible for this DCP. If
the R1, R0 bits are zero, then the read or write is to either
FN6227.0
June 23, 2006
10
ISL22416
CS
SCK
SDI
0
0
0
1
0
1
0
0
0
I3 I2
I1 I0
0
0
R1 R0
0
D6 D5 D4 D3 D2 D1 D0
FIGURE 16. THREE BYTE WRITE SEQUENCE
the IVR or the WR register (depends of VOL bit at ACR). If
the R1 bit is 1 and R0 bit is 0, then the operation is on the
ACR.
Applications Information
Communicating with ISL22416
Communication with ISL22416 proceeds using SPI interface
through the ACR (address 10b), IVR (address 00b) and WR
(address 00b) registers.
Write Operation
A Write operation to the ISL22416 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a
write to address 0 (WR), the byte at address 2 (ACR<7>)
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit at address 10b is set to 0.
Writing a new value to the IVR register will set a new power
up position for the wiper. Also, writing to this register will load
the same value into the WR as the IVR. Reading from the
IVR will not change the WR, if its contents are different.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms.
Read Operation
A read operation to the ISL22416 is a three byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS pin from
LOW to HIGH (see Figure 17).
In order to read back the non-volatile IVR, it is reccomended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
CS
SCK
SDI
Don’t Care
0
0
0
1
0
1
0
0
0
I3 I2
I1 I0
0
0
R1 R0
SDO
0
D6 D5 D4 D3 D2 D1 D0
FIGURE 17. THREE BYTE READ SEQUENCE
FN6227.0
June 23, 2006
11
ISL22416
Examples:
A. Writing to the IVR:
This sequence will write a new value (77h) to the IVR(non-volatile):
Set the ACR (Addr 02h) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte
0
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
(Sent to DI)
Set the IVR (Addr 00h) to 77h
Send the ID byte, Instruction Byte, then the Data byte
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
(Sent to DI)
B. Reading from the WR:
This sequence will read the value from the WR (volatile):
Write to ACR first to access the WR
Send the ID byte, Instruction Byte, then the Data byte
0
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
(Sent to DI)
Read the data from WR (Addr 00h)
Send the ID byte, Instruction Byte, then Read the Data byte
0
1
0
1
0
0
0
0
1
0
1
1
0
0
0
0
x
x
x
x
x
x
x
x
(Out on DO)
FN6227.0
June 23, 2006
12
ISL22416
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.020 BSC
0.50 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
10
0.95 REF
10
-
0.10 (0.004)
-A-
C
C
b
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
θ
-
o
o
o
o
a
SIDE VIEW
5
15
5
15
-
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 0 12/02
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6227.0
June 23, 2006
13
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