ISL34321_技术文档

16-Bit Long-Reach Video SERDES with Bi-directional

Side-Channel

ISL34321

Features

• 16-bit RGB transport over single differential pair

The ISL34321 is a serializer/deserializer of LVCMOS

parallel video data. The video data presented to the

serializer on the parallel LVCMOS bus is serialized into a

high-speed differential signal. This differential signal is

converted back to parallel video at the remote end by the

deserializer. It also transports auxiliary data

• 6MHz to 45MHz pixel clock rates

• Bi-directional auxiliary data transport without extra

bandwidth and over the same differential pair

• Hot plugging with automatic resynchronization every

HSYNC.

bidirectionally over the same link during the video

vertical retrace interval.

2

• I C Bus Mastering to the remote side of the link with

a controller on either the serializer or deserializer

2

I C bus mastering allows the placement of external slave

2

• Selectable clock edge for parallel data output

devices on the remote side of the link. An I C controller

can be place on either side of the link allowing

bidirectional I C communication through the link to the

• DC balanced with industry standard 8b/10b line code

allows AC-coupling

2

external devices on the other side. Both chips can be

fully configured from a single controller or independently

by local controllers.

- Provides immunity against ground shifts

• 16 programmable settings each for transmitter

amplitude boost and pre-emphasis and receiver

equalization allow for longer cable lengths and

higher data rates

Applications*(see page 12)

• Video entertainment systems

• Industrial computing terminals

• Remote cameras

• Same device for serializer and deserializer simplifies

inventory

Related Literature*(see page 12)

• See ISL34341 datasheet FN6827 “WSVGA 24-Bit

Long-Reach Video SERDES with Bi-directional Side-

Channel”

Typical Application

3.3V

1.8V

VDD_IO

3.3V

1.8V

VDD_IO

16

10m DIFFERENTIAL CABLE

27nF

RGBA/C

SERIOP

SERION

SERIOP

VSYNC

HSYNC

VSYNC

HSYNC

VIDEO

ISL34321

SERION

SOURCE

TARGET

DATAEN

PCLK_IN

DATAEN

PCLK_OUT

REF_CLK

PCLK_IN

VDD_IO

September 23, 2010

FN6870.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL34321

Block Diagram

SCL

I²C

SDA

VCM

GENERATOR

RAM

SERIOP

SERION

PRE-

EMPHASIS

TX

3

V/H/DE

TDM

MUX

DEMUX

8b/10b

RGB

16

RX EQ

VIDEO_TX

(HI)

CDR

PCLK_IN

x20

(REF_CLK WHEN

VIDEO_TX IS LO)

PCLK_OUT

x20

Pin Configuration

ISL34321

(48 LD EPTQFP)

TOP VIEW

36 35 34 33 32 31 30 29 28 27 26 25

GND_IO

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

SDA

VDD_IO

PCLK_OP

RGBA0

RGBA1

RGBA2

RGBA3

RGBA4

RGBA5

RGBA6

RGBA7

GND_IO

SCL

VDD_P

GND_P

PCLK_IN

VIDEO_TX

VHSYNCPOL

VSYNC

HSYNC

DATAEN

VDDCR

GNDCR

1

2

3

4

5

6

7

8

9 10 11 12

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ISL34321

Pin Descriptions

DESCRIPTION

PIN NUMBER

PIN NAME

SERIALIZER

DESERIALIZER

47, 46

45, 44

43, 42

41, 40

9, 8

7, 6

5, 4

3, 2

RGBA7, RGBA6

RGBA5, RGBA4

RGBA3, RGBA2

RGBA1, RGBA0

RGBC7, RGBC6

RGBC5, RGBC4

RGBC3, RGBC2

RGBC1, RGBC0

Parallel video data LVCMOS inputs with

Hysteresis

Parallel video data LVCMOS outputs

16

17

15

HSYNC

VSYNC

DATAEN

Horizontal (line) Sync LVCMOS input with

Hysteresis

Horizontal (line) Sync LVCMOS output

Vertical (frame) Sync LVCMOS output

Video Data Enable LVCMOS output

Vertical (frame) Sync LVCMOS input with

Hysteresis

Video Data Enable LVCMOS input with

Hysteresis

20

39

PCLK_IN

PCLK_OUT

Pixel clock LVCMOS input

Default; not used

PLL reference clock LVCMOS input

Recovered clock LVCMOS output

High speed differential serial I/O

33, 32

18

SERIOP, SERION

VHSYNCPOL

High-speed differential serial I/O

CMOS input for HSYNC and VSYNC Polarity

1: HSYNC & VSYNC active low

0: HSYNC & VSYNC active high

19

VIDEO_TX

CMOS input for video flow direction

1: video serializer

0: video deserializer

2

24, 23

25, 26

27

SDA, SCL (Note 1) I C Interface Pins (I C DATA, I C CLK)

2

I2CA[1:0] (Note 1) I C Device Address

2

MASTER

RSTB/PDB

STATUS

I C Master Mode

1: Master

0: Slave

12

10

CMOS input for Reset and Power-down. For normal operation, this pin must be forced

high. When this pin is forced low, the device will be reset. If this pin stays low, the device

will be in PD mode.

CMOS output for Receiver Status:

1: Valid 8b/10b data received

0: otherwise

Note: serializer and deserializer switch roles during side-channel reverse traffic

28

21

REF_RES

Analog bias setting resistor connection; use 3.16kΩ ±1% to ground

GND_P (Note 2)

PLL Ground

37, 48

35

GND_IO (Note 2) Digital (Parallel and Control) Ground

GND_CDR (Note 2) Analog (Serial) Data Recovery Ground

GND_TX (Note 2) Analog (Serial) Output Ground

GND_AN (Note 2) Analog Bias Ground

31

29

13

GND_CR (Note 2) Core Logic Ground

14

VDD_CR

VDD_TX

VDD_AN

Core Logic VDD

34

Analog (Serial) Output VDD

Analog Bias VDD

30

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ISL34321

Pin Descriptions(Continued)

DESCRIPTION

PIN NUMBER

PIN NAME

SERIALIZER

DESERIALIZER

36

1, 38

VDD_CDR

Analog (Serial) Data Recovery VDD

VDD_IO (Note 1) Digital (Parallel and Control) VDD

22

VDD_P

TEST_EN

PD

PLL VDD

11

Must be connected to ground

Exposed Pad

NOTES:

1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting

together external components or features.

2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The

different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins.

In particular, for ESD testing, they should be considered a common connection

Ordering Information

PART

NUMBER

(Notes 3, 4, 5)

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

PART MARKING

ISL34321INZ

ISL34321 INZ

-40 to +85

48 Ld EPTQFP

Q48.7x7B

3. Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL34321. For more information on MSL please

see techbrief TB363.

FN6870.1

September 23, 2010

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ISL34321

Absolute Maximum Ratings

Thermal Information

Supply Voltage

VDD_P to GND_P, VDD_TX to GND_TX,

Thermal Resistance (Typical)

θ

(°C/W)

12

JA

JC

EPTQFP (Notes 6, 7). . . . . . . . . . .

38

VDD_IO to GND_IO . . . . . . . . . . . . . . . . -0.5V to 4.6V

VDD_CDR to GND_CDR, VDD_CR to GND_CR -0.5V to 2.5V

Between any pair of GND_P, GND_TX,

GND_IO, GND_CDR, GND_CR . . . . . . . . . . -0.1V to 0.1V

3.3V Tolerant LVTTL/LVCMOS

Input Voltage . . . . . . . . . . . . . . . .-0.3V to VDD_IO+0.3V

Differential Input Voltage . . . . . . . .-0.3V to VDD_IO + 0.3V

Differential Output Current . . . . . . . . Short Circuit Protected

LVTTL/LVCMOS Outputs . . . . . . . . . . Short Circuit Protected

ESD Rating

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . .327mW

Maximum Junction Temperature . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range . . . -65°C to +150°C

Operating Temperature Range . . . . . . . . . . -40°C to +85°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Human Body Model

All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV

SERIOP/N (all VDD Connected, all GND Connected) . 8kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

Latch Up (Tested per JESD-78B; Class2, Level A). . . .100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

JA

features. See Tech Brief TB379.

7. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V

,

VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16kΩ, High-speed

AC-coupling capacitor = 27nF.

A

PARAMETER

POWER SUPPLY VOLTAGE

VDD_CDR, VDD_CR

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

1.7

3.0

1.8

3.3

1.9

3.6

V

VDD_TX, VDD_P, VDD_AN, VDD_IO

SERIALIZER POWER SUPPLY CURRENTS

Total 1.8V Supply Current

PCLK_IN = 45MHz

(Note 8)

62

40

80

52

mA

Total 3.3V Supply Current

DESERIALIZER POWER SUPPLY CURRENTS

Total 1.8V Supply Current

PCLK_IN = 45MHz

(Note 8)

66

50

76

63

mA

Total 3.3V Supply Current

POWER-DOWN SUPPLY CURRENT

Total 1.8V Power-Down Supply Current

Total 3.3V Power-Down Supply Current

PARALLEL INTERFACE

RSTB = GND

10

mA

0.5

High Level Input Voltage

Low Level Input Voltage

Input Leakage Current

High Level Output Voltage

V

2.0

V

IH

V

0.8

1

IL

I

-1

±0.01

µA

V

IN

V

I

= -4.0mA,

2.6

OH

VDD_IO = 3.0V

Low Level Output Voltage

V

I

= 4.0mA,

0.4

35

V

OL

VDD_IO = 3.6V

Output Short Circuit Current

I

mA

OSC

FN6870.1

September 23, 2010

5

ISL34321

Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V

,

VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16kΩ, High-speed

AC-coupling capacitor = 27nF. (Continued)

A

PARAMETER

SYMBOL

/t

CONDITIONS

MIN

TYP

MAX

UNITS

Output Rise and Fall Times

t

Slew rate control set to min

C = 8pF

1

ns

OR OF

L

Slew rate control set to

4

ns

max, C = 8pF

L

SERIALIZER PARALLEL INTERFACE

PCLK_IN Frequency

f

6

45

60

MHz

%

IN

PCLK_IN Duty Cycle

t

40

50

IDC

Parallel Input Setup Time

Parallel Input Hold Time

t

3.5

1.0

ns

IS

IH

t

ns

DESERIALIZER PARALLEL INTERFACE

PCLK_OUT Frequency

f

6

45

MHz

%

OUT

PCLK_OUT Duty Cycle

t

50

0.5

±20

ODC

PCLK_OUT Period Jitter (rms)

PCLK_OUT Spread Width

t

Clock randomizer off

Clock randomizer on

%t

OJ

PCLK

t

OSPRD

PCLK

PCLK_OUT to Parallel Data Outputs

(includes Sync and DE pins)

t

Relative to PCLK_OUT,

(Note 9)

-1.0

4

5.5

14

ns

DV

Deserializer Output Latency

t

Inherent in the design

9

PCLK

CPD

DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)

REF_CLK Lock Time

t

100

µs

PLL

REF_CLK to PCLK_OUT Maximum

Frequency Offset

PCLK_OUT is the

recovered clock

1500

650

5000

ppm

HIGH-SPEED TRANSMITTER

HS Differential Output Voltage,

Transition Bit

VOD

TXCN = 0x00

TXCN = 0x0F

TXCN = 0xF0

TXCN = 0xFF

TXCN = 0x00

TXCN = 0x0F

TXCN = 0xF0

TXCN = 0xFF

800

900

mV

TR

P-P

1100

1300

800

HS Differential Output Voltage, Non-

Transition Bit

VOD

650

NTR

900

430

600

HS Generated Output Common Mode

Voltage

V

2.35

V

OCM

HS Common Mode Serializer-

Deserializer Voltage Difference

ΔV

10

20

mV

CM

HS Differential Output Impedance

HS Output Latency

R

80

4

100

7

120

10

Ω

PCLK

ps

OUT

t

Inherent in the design

20% to 80%

LPD

HS Output Rise and Fall Times

HS Differential Skew

t

150

<10

6

R/ F

t

ps

SKEW

HS Output Random Jitter

HS Output Deterministic Jitter

t

PCLK_IN = 45MHz

ps

RJ

DJ

rms

t

25

ps

P-P

FN6870.1

September 23, 2010

6

ISL34321

Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V

,

VDD_TX = VDD_P = VDD_AN = 3.3V, T = +25°C, Ref_Res = 3.16kΩ, High-speed

AC-coupling capacitor = 27nF. (Continued)

A

PARAMETER

HIGH SPEED RECEIVER

HS Differential Input Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

75

mV

P-P

ID

HS Generated Input Common Mode

Voltage

V

2.32

V

ICM

HS Differential Input Impedance

HS Maximum Jitter Tolerance

R

80

100

120

Ω

IN

0.50

UI

P-P

2

I C

2

I C Clock Rate (on SCL)

f

100

400

1

kHz

µs

I2C

2

I C Clock Pulse Width (HI or LO)

1.3

0

2

I C Clock Low to Data Out Valid

µs

2

I C Start/Stop Setup/Hold Time

0.6

100

µs

2

I C Data in Setup Time

ns

2

I C Data in Hold Time

ns

2

I C Data out Hold Time

ms

NOTES:

8. IDDIO is nominally 50µA and not included in this total as it is dominated by the loading of the parallel pins

9. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is

dependent on the PCLK frequency and is calculated as follows: 0.5 * f - t

.

IN

DV.

FN6870.1

September 23, 2010

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ISL34321

Diagrams

VOD_TR

VOD_NTR

TXCN

0x00

0x0F

0xF0

0xFF

FIGURE 1. VOD vs. TXCN SETTING

1/f

T

IDC

IN

VIDEO_TX = 1

PCLK_IN

T

IH

IS

RGB[A:C][7:0]

VALID DATA

DATA IGNORED

VALID DATA

IH

T

IS

HSYNC

VSYNC

DATAEN

FIGURE 2. PARALLEL VIDEO INPUT TIMING [PCLK_IN ACTIVE LOW, HSYNC/VSYNC ACTIVE HIGH]

FN6870.1

September 23, 2010

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ISL34321

VIDEO_TX = 0

T

OF

1/f

ODC

OR

OUT

PCLK_OUT

T

DV

VALID DATA

DATA HELD AT PREVIOUS VALUE

VALID DATA

RGB[A:C][7:0]

T

DV

HSYNC

VSYNC

DATAEN

FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [PCLK_OUT ACTIVE LOW, HSYNC/VSYNC ACTIVE HIGH]

PCB traces need to be adjacent and matched in length

(so as to minimize the imbalanced coupling to other

traces or elements) and of a geometry to match the

impedance of the transmitter and receiver to minimize

reflections. Similar care needs to be applied to the choice

of connectors and cables.

Applications

Detailed Description and Operation

A pair of ISL34321 SERDES transports 16-bit parallel

video for the ISL34321 along with auxiliary data over a

single 100Ω differential cable either to a display or from a

camera. Auxiliary data is transferred in both directions

and can be used for remote configuration and telemetry.

SERIOP and SERION pins incorporate internal differential

termination of the serial signal lines.

SERIO Pin AC-Coupling

The benefits include lower EMI, lower costs, greater

reliability and space savings. The same device can be

configured to be either a serializer or deserializer by

setting one pin (VIDEO_TX), simplifying inventory.

RGBA/B/C, VSYNC, HSYNC, and DATAEN pins are inputs

in serializer mode and outputs in deserializer mode.

AC-coupling minimizes the effects of DC common mode

voltage difference and local power supply variations

between two SERDES. The serializer outputs DC

balanced 8b/10b line code, which allows AC-coupling.

The AC-coupling capacitor on SERIO pins must be 27nF

on the serializer board and 27nF on the deserializer

board. The value of the AC-coupling capacitor is very

critical since a value too small will attenuate the high

speed signal at low clock rate. A value too big will slow

down the turn around time for the side-channel. It is an

advantage to have the pair of capacitors as closely

matched as possible.

The video data presented to the serializer on the parallel

LVCMOS bus is serialized into a high-speed differential

signal. This differential signal is converted back to

parallel video at the remote end by the deserializer. The

Side Channel data is transferred between the SERDES

pair during two lines of the vertical video blanking

interval.

When the side-channel is enabled, there will be a number

of PCLK cycles uncertainty from frame-to-frame. This

should not cause sync problems with most displays, as

this occurs during the vertical front porch of the blanking

period. When properly configured, the SERDES link

supports end-to-end transport with fewer than one error

Receiver Reference Clock (REF_CLK)

The reference clock (REF_CLK) for the PLL is fed into

PCLK_IN pin. REF_CLK is used to recover the clock

from the high speed serial stream. REF_CLK is very

sensitive to any instability. The following conditions

must be met at all times after power is applied to the

deserializer, or else the deserializer may need a

manual reset:

10

in 10 bits.

Differential Signals and Termination

The ISL34321 serializes the 16-bit parallel data plus 3

sync signals at 20x the PCLK_IN frequency. The extra 2

bits per word come from the 8b/10b encoding scheme

which helps create the highest quality serial link.

• VDD must be applied and stable.

• REF_CLK frequency must be within the limits

specified

The high bit rate of the differential serial data requires

special care in the layout of traces on PCBs, in the choice

and assembly of connectors, and in the cables

themselves.

• REF_CLK amplitude must be stable.

A simple 3.3V CMOS crystal oscillator can be used for

REF_CLK.

FN6870.1

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ISL34321

Power Supply Sequencing

The 3.3V supply must be higher than the 1.8V supply at

all times, including during power-up and power-down. To

meet this requirement, the 3.3V supply must be powered

up before the 1.8V supply.

For the deserializer, REF_CLK must not be applied before

the device is fully powered up. Applying REF_CLK before

power-up may require the deserializer to be manually

reset. A 10ms delay after the 1.8V supply is powered up

guarantees normal operation.

Power Supply Bypassing and Layout

The serializer and deserializer functions rely on the stable

functioning of PLLs locked to local reference sources or

locked to an incoming signal. It is important that the

various supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX)

be well bypassed over a wide range of frequencies, from

below the typical loop bandwidth of the PLL to

approaching the signal bit rate of the serial data. A

combination of different values of capacitors from

1000pF to 5µF or more with low ESR characteristics is

generally required.

FIGURE 4. POWER SUPPLY BYPASSING

2

I C Interface

The I C interface allows access to internal registers used

to configure the SERDES and to obtain status

information. A serializer must be assigned a different

address than its deserializer counterpart. The upper 5

bits are permanently set to 011 11 and the lower 2bits

determined by pins as follows:

2

The parallel LVCMOS VDD_IO supply is inherently less

sensitive, but since the RGB and SYNC/DATAEN signals

can all swing on the same clock edge, the current in

these pins and the corresponding GND pins can undergo

substantial current flow changes, so once again, a

combination of different values of capacitors over a wide

range, with low ESR characteristics, is desirable.

0

1

I2CA1 I2CA0 R/W

Thus, 16 SERDES can reside on the same bus. By

convention, when all address pins are tied low, the device

address is referred to as 0x78.

A set of arrangements of this type is shown in Figure 4,

where each supply is bypassed with a ferrite-bead-based

choke, and a range of capacitors. A “choke” is preferable

to an “inductor” in this application, since a high-Q

inductor will be likely to cause one or more resonances

with the shunt capacitors, potentially causing problems

at or near those frequencies, while a “lossy” choke will

reflect a high impedance over a wide frequency range.

SCL and SDA are open drain to allow multiple devices to

share the bus. If not used, SCL and SDA should be tied to

VDD_IO.

Side Channel Interface

The Side Channel is a mechanism for transferring data

between the two chips on each end of the link. This data

is transferred during video blanking so none of the video

bandwidth is used. It has three basic uses:

The higher value capacitor, in particular, needs to be

chosen carefully, with special care regarding its ESR.

Very good results can be obtained with multilayer

ceramic capacitors, available from many suppliers, and

generally in small outlines (such as the 1210 outline

suggested in the schematic shown in Figure 4), which

provide good bypass capabilities down to a few mΩ at

1MHz to 2MHz. Other capacitor technologies may also be

suitable (perhaps niobium oxide), but “classic”

electrolytic capacitors frequently have ESR values of

above 1Ω, that nullify any decoupling effect above the

1kHz to 10kHz frequency range.

• Data exchanges between two processors

• Master Mode I²C commands to remote slaves

• Remote SERDES configuration

This interface allows the user to initialize registers,

control and monitor both SERDES chips from a single

micro controller which can reside on either side of the

serial link. This feature is used to automatically transport

the remote side serdes chip’s status back to a local

register. The Side Channel needs to be enabled (the

default) for this to work. In the case where there is a

micro controller on each side of the of the link, data can

be buffered and exchanged between the two. Up to 224

bytes can be sent in each direction during each VSYNC

active period.

Capacitors of 0.1µF offer low impedance in the 10MHz to

20MHz region, and 1000pF capacitors in the 100MHz to

200MHz region. In general, one of the lower value

capacitors should be used at each supply pin on the IC.

Figure 4 shows the grounding of the various capacitors to

the pin corresponding to the supply pin. Although all the

ground supplies are tied together, the PCB layout should

be arranged to emulate this arrangement, at least for the

smaller value (high frequency) capacitors, as much as

possible.

FN6870.1

September 23, 2010

10

ISL34321

Master Mode

COPPER PAD

This is a mode activated by strapping the MASTER pin to

a ‘1’ on the ISL34321 on the remote side of the

controller. This is a virtual extension of the I²C interface

across the link that allows the local processor to read and

write slave devices connected to the remote side serdes

I²C bus. No additional wires or components are needed

other than the serial link. The I²C commands and data

are transferred during video blanking causing no

interruptions in the video data. In Master mode the data

is transported across the link by the Side Channel so the

maximum throughput achievable would be the same.

The SCL and SDA frequency is adjustable through the

programming of a register.

VIAS

25X

FIGURE 5. LAYOUT FOR THE EXPOSED PAD

Exposed Pad

While it is not a required electrical connection, it is

recommended that the exposed pad on the bottom of the

package be soldered to the circuit board. This will ensure

that the full power dissipation of the package can be

utilized. The pad should be connected to ground and not

left floating. For best thermal conductivity 9 - 25 vias

should connect the footprint for the exposed pad on the

circuit board to the ground plane.

FN6870.1

September 23, 2010

11

ISL34321

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

7/15/10

FN6870.1

Updated “Package Outline Drawing” on page 13. Changes were: Updated the format by

moving dimensions from table onto drawing and adding land pattern.

5/14/10

Converted to New Intersil Template

Updated Ordering Information by adding MSL note

Removed from Features Section:

• Internal 100Ω termination on high-speed serial lines

• Programmable powerdown of the transmitter and the receiver

• I2C communication interface

• 8kV ESD rating for serial lines

• Pb-free (RoHS compliant)

Changed Order of following items in datasheet:

-Moved Block Diagram to immediately follow page 1 then Pin Configuration

-Pin Description Table moved to immediately follow Pinout

-Ordering Information to follow Pin Descriptions

Added Latch-up to Abs Max Ratings

Added Diagrams and Applications Section, Revision History and Products Information

Initial Release to web

3/16/09

FN6870.0

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

handheld products, and notebooks. Intersil's product families address power management and analog signal

processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL34321

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6870.1

September 23, 2010

12

ISL34321

Package Outline Drawing

Q48.7x7B

48 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE

Rev 2, 7/10

9.0±0.20

4

5

7.0±0.10

3

D

A

3

7.0±0.10

4

5

9.0±0.20

4.00±0.1

0.50

B

3

TOP VIEW

EXPOSED PAD

4.00±0.1

1.20 MAX

11/13°

BOTTOM VIEW

C

0.08

0° MIN.

SEE DETAIL "A"

H

0.08 M C A-B D

WITH LEAD FINISH

2

1.00 ±0.05

0.05/0.15

0.17/0.27

7

0.09/0.20

0.09/0.16

0.25

GAUGE

PLANE

0-7°

0.20 MIN.

(1.00)

0.60 ±0.15

0.17/0.23

BASE METAL

DETAIL "A"

(10.00)

(0.28) TYP

NOTES:

1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.

2. Datum plane H located at mold parting line and coincident

with lead, where lead exits plastic body at bottom of parting line.

(10.00)

3. Datums A-B and D to be determined at centerline between

leads where leads exit plastic body at datum plane H.

(4.00)

4. Dimensions do not include mold protrusion. Allowable mold

protrusion is 0.254mm on D1 and E1 dimensions.

5. These dimensions to be determined at datum plane H.

6. Package top dimensions are smaller than bottom dimensions

and top of package will not overhang bottom of package.

(1.50) TYP

7. Dimension does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm total at maximum material

condition. Dambar cannot be located on the lower radius or

the foot.

8. Controlling dimension: millimeter.

(4.00)

9.

This outline conforms to JEDEC publication 95 registration

MS-026, variation ABC-HD.

TYPICAL RECOMMENDED LAND PATTERN

10. Dimensions in ( ) are for reference only.

FN6870.1

September 23, 2010

13


型号：	ISL34321
厂家：	Intersil
描述：	16-Bit Long-Reach Video SERDES with Bi-directional Side-Channel 16位长距离视频SERDES与双向侧通道
文件：	总13页 (文件大小：370K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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