ISL59530_0708 [INTERSIL]
16x16 Video Crosspoint; 16×16视频交叉点型号: | ISL59530_0708 |
厂家: | Intersil |
描述: | 16x16 Video Crosspoint |
文件: | 总25页 (文件大小:1447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL59530
®
Data Sheet
August 29, 2007
FN6220.6
16x16 Video Crosspoint
Features
The ISL59530 is a 300MHz 16x16 Video Crosspoint Switch.
Each input has an integrated DC-restore clamp and an input
buffer. Each output has a fast On-Screen Display (OSD)
switch (for inserting graphics or other video) and an output
buffer. The switch is non-blocking, so any combination of
inputs to outputs can be chosen, including one channel
driving multiple outputs. The Broadcast Mode directs one
input to all 16 outputs. The output buffers can be individually
controlled through the SPI interface, the gain can be
programmed to x1 or x2, and each output can be placed into
a high impedance mode.
• 16x16 non-blocking switch with buffered inputs and outputs
• 300MHz typical bandwidth
• 0.025%/0.05° dG/dP
• Output gain switchable x1 or x2 for each channel
• Individual outputs can be put in a high impedance state
• -90dB Isolation at 6MHz
• SPI digital interface
• Single +5V supply operation
• Pb-free available (RoHS compliant)
The ISL59530 offers a typical -3dB signal bandwidth of
300MHz. Differential gain of 0.025% and differential phase of
0.05°, along with 0.1dB flatness out to 50MHz, make the
ISL59530 suitable for many video applications.
Applications
• Security camera switching
• RGB routing
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible three-wire
serial interface. The ISL59530 interface is designed to
facilitate both fast updates and initialization. On power-up, all
outputs are high impedance to avoid output conflicts.
• HDTV routing
Ordering Information
PART NUMBER
(Note)
PACKAGE
(Pb-Free)
TAPE & REEL
PKG. DWG. #
V356.27x27
L72.10x10C
The ISL59530 is available in a 356 ball BGA package and
specified over an extended -40°C to +85°C temperature range.
ISL59530IKZ
-
-
356 Ld PBGA
72 Ld QFN
(Coming Soon)
ISL59530IRZ
The single-supply ISL59530 can accommodate input signals
from 0V to 3.5V and output voltages from 0V to 3.8V. Each
input includes a clamp circuit that restores the input level to
an externally applied reference in AC-coupled applications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
The ISL59531 is a fully differential input version of this device.
Block Diagram
VS
VOVERn
OVERn
16 OVERLAY
VIDEO INPUTS
16 OVERLAY
CHANNEL
ENABLES
VREF
CLAMP
16 VIDEO
OUTPUTS
OUT0 – OUT15
16 VIDEO
INPUTS
IN0 – IN15
16x16
SWITCH
MATRIX
CLAMP
AV
X1, X2
OUTPUT
ENABLE
CLAMP
ENABLE
SDI
VSDO
SDO
SPI INTERFACE AND
CONTROL REGISTERS
SCLK
SLATCH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2007. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL59530
Pinouts
ISL59530
(356 LD BGA)
TOP VIEW
A
In12
In13
In14
In15
Over15
Over14
Out14
Out13
Over13
Vover13
Out12
Over12
Vover12
B
C
D
E
F
Out15
Vover15
Vover14
In11
In10
In9
In8
In7
In6
In5
In4
Vover11 Out11 Over11
Vover10 Out10 Over10
Vover9 Over9 Out9
Vover8 Over8 Out8
V
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
SDO
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
G
H
J
SDO
RESET
SLATCH
CLK
K
L
SDI
M
N
P
R
T
V
Vover7 Out7
Vover6 Out6
Over7
Over6
REF
Vover5 Over5 Out5
U
V
W
Y
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
NC
NC
NC
Vover0
Vover1
Vover2
Vover3
Vover4 Over4 Out4
Over0
Over1
Out2
Out3
In3
In2
In1
In0
Out0
Out1
Over2
Over3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
= NO BALLS
BALLS LABELLED “NC” SHOULD BE LEFT UNCONNECTED - DO NOT TIE THEM TO
GROUND!
BALLS WITH NO LABELS MAY BE TIED TO GROUND TO SLIGHTLY REDUCE
THERMAL IMPEDANCE.
FN6220.6
August 29, 2007
2
ISL59530
Pinouts (Continued)
ISL59530
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
GND
RESET
VS
1
2
54 GND
VS
53
52
51
50
49
48
47
46
45
44
43
42
41
3
OUT11
OUT10
VS
4
IN11
IN10
VS
5
6
OUT9
OUT8
GND
VS
7
IN9
8
IN8
9
SLATCH
VS
10
11
12
13
14
OUT7
OUT6
VS
CLK
IN7
IN6
OUT5
OUT4
VS
VS
15
16
17
40
39
38
IN5
IN4
GND
GND
VS
SDI 18
37 GND
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN6220.6
August 29, 2007
3
ISL59530
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . . 6.0V
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA
Maximum power supply (V ) slew rate . . . . . . . . . . . . . . . . . . 1V/µs
S
Operating Conditions
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications
V = 5V, R = 150Ω unless otherwise noted.
S L
MIN
MAX
PARAMETER
DESCRIPTION
Power Supply Voltage
CONDITION
(Note 1)
TYP
(Note 1) UNIT
V
4.5
1.2
0.98
1.96
-1.5
-1.5
0
5.5
5.5
V
V
S
V
Power Supply for SDO output pin
Gain
Establishes serial data output high level
SDO
A
A
= 1
= 2
= 1
= 2
= 1
= 2
1
2
1.02
2.04
+1.5
+1.5
3.5
V/V
V/V
%
V
V
A
V
GM
Gain Matching (to average of all other
outputs)
A
V
A
%
V
V
V
Video Input Voltage Range
Video Output Voltage Range
Input Bias Current
A
V
IN
V
A
0.1
-10
0.5
3.8
V
OUT
V
I
Clamp function disabled (DC coupled inputs)
-5
2
1
µA
µA
µA
mV
mV
mA
mA
dB
mA
mA
mA
B
Clamp function enabled, V = V
IN
+ 0.5V
10
REF
I
V
Input Current
Clamp function enabled
-110
8
REF
REF
V
Output Offset Voltage
A
= 1
= 2
-20
-70
60
35
40
OS
V
A
-10
108
31
V
I
Output Current
Sourcing, R = 10Ω to GND
L
OUT
Sinking, R = 10Ω to 2.5V
24
L
PSRR
Power Supply Rejection Ratio
Supply Current
A
= 1 and A = 2
50
70
V
V
I
Enabled, all outputs enabled, no load current
Enabled, all outputs disabled, no load current
Disabled
275
135
1.2
320
165
1.8
360
195
2.4
S
AC Electrical Specifications
V = 5V, R = 150Ω unless otherwise noted.
S L
MIN
MAX
PARAMETER
BW -3dB
BW 0.1dB
SR
DESCRIPTION
3dB Bandwidth
CONDITION
(Note 1)
TYP
300
50
(Note 1) UNIT
V
V
V
V
= 200mV , A = 2
MHz
MHz
OUT
OUT
OUT
OUT
P-P
V
0.1dB Bandwidth
Slew Rate
= 200mV , A = 2
P-P
V
= 2V , A = 2
300
520
12
740
V/µs
ns
P-P
V
t
Settling Time to 0.1%
Switching Glitch, Peak
Overlay Delay Time
Diff Gain
= 2V , A = 2
S
P-P
V
Glitch
A
= 1
40
mV
ns
V
t
From OVER rising edge to output transition
6
over
dG
dP
A
= 2, R = 150Ω
0.025
0.05
-90
-72
18
%
V
L
Diff Phase
A
= 2, R = 150Ω
°
V
L
XT
ADJACENT
Adjacent Channel Crosstalk
Hostile Crosstalk
Input Referred Noise Voltage
6MHz, A = 1
dB
V
XT
HOSTILE
6MHz, A = 1
dB
V
V
nV/√Hz
N
NOTE:
1. All Min/Max parameters are guaranteed by 100% production testing at T = +25°C. Typical values are for information purposes only.
A
FN6220.6
August 29, 2007
4
ISL59530
Pin Descriptions
72 LD QFN
356 LD BGA
Y8
NAME
DESCRIPTION
27
26
21
19
16
15
13
12
8
IN0
IN1
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Input
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Crosspoint Video Output
Y6
Y4
IN2
Y2
IN3
V1
IN4
T1
IN5
P1
IN6
M1
IN7
K1
IN8
7
H1
IN9
5
F1
IN10
4
D1
IN11
72
70
64
63
29
30
33
34
41
42
44
45
48
49
51
52
56
57
59
60
-
A1
IN12
A3
IN13
A5
IN14
A7
IN15
Y10
Y12
W14
W16
V20
T20
P19
M19
K20
H20
F19
D19
A17
A15
B13
B11
W10
W12
Y14
Y16
V19
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OVER0
OVER1
OVER2
OVER3
OVER4
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
-
-
-
-
FN6220.6
August 29, 2007
5
ISL59530
Pin Descriptions (Continued)
72 LD QFN
356 LD BGA
NAME
DESCRIPTION
Overlay Logic Control (with pull-down)
-
-
T19
P20
M20
K19
H19
F20
D20
B17
B15
A13
A11
V10
V12
V14
V16
V18
T18
P18
M18
K18
H18
F18
D18
C17
C15
C13
C11
M3
OVER5
OVER6
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Logic Control (with pull-down)
Overlay Video Input
-
OVER7
-
OVER8
-
OVER9
-
OVER10
OVER11
OVER12
OVER13
OVER14
OVER15
VOVER0
VOVER1
VOVER2
VOVER3
VOVER4
VOVER5
VOVER6
VOVER7
VOVER8
VOVER9
VOVER10
VOVER11
VOVER12
VOVER13
VOVER14
VOVER15
VREF
-
-
-
-
-
-
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
-
Overlay Video Input
22
DC-restore clamp reference input. In an AC-coupled configuration
(DC-Restore clamp enabled), the sync tip of composite video inputs
will be restored to this level. Set to 0.3V to 0.7V for optimum
performance.
In an DC-coupled configuration (DC-Restore clamp disabled), this pin
should be tied to ground.
Do not let the VREF pin float! A floating VREF pin drifts high and, if
the clamp function is enabled, will cause all of the outputs to
simultaneously try to drive ~4V DC into their 150Ω loads.
9
J3
SLATCH
Serial Latch. Serial data is latched into ISL59530 on rising edge of
SLATCH.
11
18
K3
L3
CLK
SDI
Serial data clock
Serial data input
FN6220.6
August 29, 2007
6
ISL59530
Pin Descriptions (Continued)
72 LD QFN
356 LD BGA
NAME
DESCRIPTION
69
G3
H3
D3
SDO
RESET
VSDO
VS
Serial data output. Can be tied to SDI of another ISL59530 to enable
daisy-chaining of multiple devices.
2
Reset input. Pull high then low to reset device, but not needed in
normal operation. Tie to ground in final application.
65
Power supply for SDO pin. Tie to +5V for a 0V to 5V SDO output
signal swing.
3, 6, 10, 14, 17, 24, 25,
28, 32, 40, 43, 46, 50,
53, 58, 61, 62, 67, 68
D4, E4, F4, G4, H4, J4,
K4, L4, M4, N4, P4, R4,
T4, U4, D5, D6, D7, D8,
D9, D10, D11, D12, D13,
D14, D15, D16, D17, U5,
U6, U7, U8, U9, U10,
+5V power supply
U11, U12, U13, U14,
U15, U16, U17, E17, F17,
G17, H17, J17, K17, L17,
M17, N17, P17, R17, T17
1, 20, 23, 31, 35, 36, 37,
38, 39, 47, 54, 55, 66, 71
F6-R6, F7-R7, F8-R8,
F9-R9, F10-R10,
F11-R11, F12-R12,
F13-R13, F14-R14,
F15-R15
GND
NC
Ground
V5, V6, V9
No Connect - Do not electrically connect to anything, including
ground.
FN6220.6
August 29, 2007
7
ISL59530
Typical Performance Curves
15pF
15pF
V
= +5V
= 1
= 100Ω
V
= +5V
= 2
= 100Ω
s
S
A
A
V
V
R
R
L
L
10pF
INPUT_CH 0
OUTPUT_CH 0
INPUT_CH 0
OUTPUT_CH 0
10pF
4.7pF
0pF
4.7pF
0pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS C , A = 1,
FIGURE 2. FREQUENCY RESPONSE - VARIOUS C , A = 2,
L
V
L
V
MUX MODE
MUX MODE
V
=+5V
= 2
= 1pF
V
=+5V
= 1
= 1pF
S
S
A
A
V
V
C
C
L
L
INPUT_CH 0
OUTPUT_CH 0
INPUT_CH 0
OUTPUT_CH 0
150Ω
150Ω
50Ω
50Ω
500Ω
1.03kΩ
500Ω
1.03kΩ
FIGURE 3. FREQUENCY RESPONSE - VARIOUS R , A = 1,
FIGURE 4. FREQUENCY RESPONSE - VARIOUS R , A = 2,
L V
L
V
MUX MODE
MUX MODE
OVERLAY MODE
OVERLAY MODE
A
= 1
A
= 2
V
V
R
C
= 100Ω
= 1pF
L
L
R
C
= 100Ω
= 1pF
L
L
INPUT_CH 0
INPUT_CH 0
OUTPUT_CH 15
OUTPUT_CH 15
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT,
= 1
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT,
= 2
A
A
V
V
FN6220.6
August 29, 2007
8
ISL59530
Typical Performance Curves (Continued)
V
= +5V
= 2
= 100Ω
15pF
10pF
S
A
V
15pF
10pF
R
L
INPUT_CH 0
OUTPUT_CH 0
4.7pF
4.7pF
V
= +5V
= 1
= 100Ω
S
A
V
0pF
0pF
R
L
INPUT_CH 0
OUTPUT_CH 0
FIGURE 8. FREQUENCY RESPONSE - VARIOUS C , A = 2,
FIGURE 7. FREQUENCY RESPONSE - VARIOUS C , A = 1,
L
V
L
V
BROADCAST MODE
BROADCAST MODE
V
= +5V
= 1
= 1pF
S
V
= +5V
= 2
= 1pF
S
A
V
A
V
C
L
50Ω
C
L
150Ω
INPUT_CH 0
OUTPUT_CH 0
INPUT_CH 0
OUTPUT_CH 0
50Ω
150Ω
503Ω
503Ω
1.03kΩ
1.03kΩ
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS R , A = 1,
L
V
FIGURE 10. FREQUENCY RESPONSE - VARIOUS R , A = 2,
L
V
BROADCAST MODE
BROADCAST MODE
-30
-40
-50
-60
-70
-80
-90
-100
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
A
R
C
= 1
= 100Ω
=1pF
A
R
C
= 2
= 100Ω
= 1pF
V
L
L
V
L
L
ALL HOSTILE IN_CH14
BROADCAST TO
ALL EXCEPT OUT_CH15
HOSTILE BROADCAST
IN CH14 TO ALL BUT CH15
OUT CH15
ADJACENT
IN CH14
OUT CH15
ADJACENT
IN CH14
OUT CH15
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. CROSSTALK - A = 2
FIGURE 11. CROSSTALK - A = 1
V
V
FN6220.6
August 29, 2007
9
ISL59530
Typical Performance Curves (Continued)
THD
THD
V
= +5V
= 2
= 100Ω
S
A
V
R
L
INPUT_CH 1
OUTPUT_CH1
F
= 1MHz
IN
2nd HD
V
= +5V
= 2
= 100Ω
S
2nd HD
A
V
R
L
INPUT_CH 1
3rd HD
OUTPUT_CH 1
3rd HD
V
= 2V
OP-P
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs V
OUT_P-P
FIGURE 15. DISABLED OUTPUT IMPEDANCE
FIGURE 16. ENABLED OUTPUT IMPEDANCE
MUX MODE
A
R
= 1
= 100Ω
V
L
INPUT_CH 0
OUTPUT_CH 0
FALL TIME
2.44ns
RISE TIME
2.42ns
MUX MODE
A
= 1
= 100Ω
V
R
L
INPUT_CH 0
OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 17. RISE TIME - A = 1
V
FIGURE 18. FALL TIME - A = 1
V
FN6220.6
August 29, 2007
10
ISL59530
Typical Performance Curves (Continued)
MUX MODE
A
= 2
= 100Ω
V
R
L
INPUT_CH 0
FALL TIME
2.40ns
OUTPUT_CH 0
RISE TIME
2.32ns
MUX MODE
A
= 2
= 100Ω
V
R
L
INPUT_CH 0
OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 19. RISE TIME - A = 2
FIGURE 20. FALL TIME - A = 2
V
V
MUX MODE
= 1
A
V
L
R
= 100Ω
INPUT_CH 0
SLEW RATE
-395V/µs
OUTPUT_CH 0
SLEW RATE
405V/µs
MUX MODE
A
= 1
= 100Ω
V
R
L
INPUT_CH 0
OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 21. RISING SLEW RATE - A = 1
V
FIGURE 22. FALLING SLEW RATE - A = 1
V
MUX MODE
A
R
= 2
= 100Ω
V
L
INPUT_CH 0
SLEW RATE
-420V/µs
OUTPUT_CH 0
SLEW RATE
430V/µs
MUX MODE
A
= 2
= 100Ω
V
R
L
INPUT_CH 0
OUTPUT_CH 0
TIME (ns)
TIME (ns)
FIGURE 23. RISING SLEW RATE - A = 2
V
FIGURE 24. FALLING SLEW RATE - A = 2
V
FN6220.6
August 29, 2007
11
ISL59530
Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY
LOGIC
INPUT
OVERLAY
LOGIC
INPUT
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
A
= 2
= 100Ω
V
R
L
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
A
= 2
= 100Ω
V
R
L
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, A = 2
V
FIGURE 28. DIFFERENTIAL PHASE, A = 2
V
A
= 2
= 100Ω
A
= 2
= 100Ω
V
V
R
R
L
L
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, A = 2
V
FIGURE 30. DIFFERENTIAL PHASE, A = 2
V
FN6220.6
August 29, 2007
12
ISL59530
Typical Performance Curves (Continued)
A
= 1
= 100Ω
V
R
L
INPUT_CH 1
OUTPUT_CH1
OSC = 40mV
A
= 1
= 100Ω
V
R
L
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 32. DIFFERENTIAL PHASE, A = 1
V
FIGURE 31. DIFFERENTIAL GAIN, A = 1
V
A
R
= 1
= 100Ω
V
L
A
= 1
= 100Ω
V
R
L
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, A = 1
V
FIGURE 34. DIFFERENTIAL GAIN, A = 1
V
A
= 2
= 100Ω
A
= 2
= 100Ω
V
V
R
R
L
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 36. DIFFERENTIAL PHASE, A = 2
V
FIGURE 35. DIFFERENTIAL GAIN, A = 2
V
FN6220.6
August 29, 2007
13
ISL59530
Typical Performance Curves (Continued)
A
= 2
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
A
= 2
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 38. DIFFERENTIAL PHASE, A = 2
V
FIGURE 37. DIFFERENTIAL GAIN, A = 2
V
A
= 1
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
A
= 1
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, A = 1
V
FIGURE 40. DIFFERENTIAL PHASE, A = 1
V
A
= 1
= 100Ω
V
A
R
= 1
= 100Ω
V
L
R
L
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 42. DIFFERENTIAL PHASE, A = 1
V
FIGURE 41. DIFFERENTIAL GAIN, A = 1
V
FN6220.6
August 29, 2007
14
ISL59530
Typical Performance Curves (Continued)
A
= 2
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 01
OSC = 40mV
A
R
= 2
= 100Ω
V
L
INPUT_CH 01
OUTPUT_CH 01
OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, A = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, A = 2
V
V
A
= 1
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 01
OSC = 40mV
A
= 1
= 100Ω
V
R
L
INPUT_CH 01
OUTPUT_CH 01
OSC = 40mV
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, A = 1
V
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, A = 1
V
FN6220.6
August 29, 2007
15
ISL59530
3dB Bandwidth, MUX Mode, A = 1, R = 100Ω [MHz]
V
L
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
255
244
257
264
255
253
247
253
255
241
235
223
220
211
199
193
229
217
229
210
222
221
224
190
180
186
183
174
176
171
174
175
169
168
164
161
160
160
222
169
168
171
175
177
177
178
184
187
188
186
188
192
192
194
197
152
233
190
212
189
207
193
166
160
169
171
167
173
170
178
183
182
185
186
185
189
193
238
2
235
204
3
217
219
4
220
202
5
218
237
6
226
230
231
210
157
163
168
165
7
227
236
235
240
218
239
223
223
228
236
240
241
223
242
219
222
217
235
211
213
8
9
10
11
12
13
14
15
236
230
207
185
225
217
209
202
205
198
214
207
224
223
212
217
197
197
216
186
177
225
3dB Bandwidth, MUX Mode, A = 2, R = 100Ω [MHz]
V
L
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
295
268
277
279
269
263
259
263
262
253
253
246
241
236
233
227
316
290
290
397
384
405
395
220
211
216
213
201
201
196
201
203
194
194
187
184
182
178
183
288
183
192
196
192
196
196
205
212
210
215
213
216
220
220
223
240
299
250
385
234
396
291
188
183
196
196
192
200
200
211
216
214
216
217
225
225
230
293
2
300
289
3
408
392
4
391
402
5
407
298
6
404
398
394
388
283
407
411
410
7
411
407
307
308
402
402
387
383
412
412
307
300
402
403
387
385
413
415
398
394
8
9
10
11
12
13
14
15
417
293
385
367
412
400
412
396
391
379
272
244
419
413
279
274
396
385
407
230
324
276
FN6220.6
August 29, 2007
16
ISL59530
3dB Bandwidth, Broadcast Mode, A = 1, R = 100Ω [MHz]
V
L
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
215
214
210
212
206
203
201
204
204
202
196
194
193
191
189
187
198
195
195
183
184
188
172
178
174
171
171
169
165
163
167
167
164
160
157
156
151
151
153
151
152
153
157
157
159
159
167
171
170
169
171
171
174
175
178
145
157
145
140
146
144
144
158
158
159
164
164
164
164
170
175
174
178
174
178
178
178
181
2
188
147
3
178
143
4
174
150
5
177
161
6
156
160
161
157
151
156
160
160
7
187
187
182
183
170
172
170
171
175
176
168
172
157
160
151
155
158
161
154
159
8
9
10
11
12
13
14
15
170
169
161
155
160
167
162
157
156
160
170
167
164
166
172
173
162
164
161
149
167
179
3dB Bandwidth, Broadcast Mode, A = 2, R = 100Ω [MHz]
V
L
INPUT CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
234
232
228
229
223
219
217
220
220
218
220
212
211
209
208
205
216
215
209
199
204
205
190
196
193
189
191
186
183
181
183
184
181
176
174
174
170
167
166
169
169
171
175
177
177
178
184
187
188
186
188
192
192
194
197
160
172
162
158
163
161
161
178
178
178
182
183
183
183
189
193
193
192
192
195
195
196
198
2
204
164
3
196
163
4
193
168
5
192
177
6
174
175
177
174
167
173
178
178
7
204
205
198
199
189
190
190
191
192
193
184
188
174
178
169
173
174
178
172
178
8
9
10
11
12
13
14
15
185
187
179
171
177
184
179
172
176
179
187
184
181
185
191
191
181
182
176
160
185
195
FN6220.6
August 29, 2007
17
ISL59530
Block Diagram
VS
VOVERn
OVERn
16 OVERLAY
VIDEO INPUTS
16 OVERLAY
CHANNEL
ENABLES
VREF
CLAMP
16 VIDEO
OUTPUTS
OUT0 – OUT15
16 VIDEO
INPUTS
IN0 – IN15
16x16
SWITCH
MATRIX
CLAMP
AV
X1, X2
OUTPUT
ENABLE
CLAMP
ENABLE
SDI
SCLK
VSDO
SDO
SPI INTERFACE AND
CONTROL REGISTERS
SLATCH
Serial Interface
General Description
The ISL59530 is programmed through a simple serial
interface. Data on the SDI (serial data input) pin is shifted
into a 16-bit shift register on the rising edge of the SCLK
(serial clock) signal (this is continuously done regardless of
the state of the SLATCH signal). The LSB (bit 0) is loaded
first and the MSB (bit 15) is loaded last (see the “Serial
Timing Diagram” on page 19). After all 16 bits of data have
been loaded into the shift register, the rising edge of
SLATCH updates the internal registers.
The ISL59530 is a 16x16 integrated video crosspoint switch
matrix with input and output buffers and On-Screen Display
(OSD) insertion. This device operates from a single +5V
supply. Any output can be generated from any of the 16 input
video signal sources, and each output can have OSD
information inserted through a dedicated, fast 2:1 mux
located before the output buffer. There is also a Broadcast
mode allowing any one input to be broadcast to all 16
outputs. A DC restore clamp function enables the ISL59530
to AC-coupled incoming video.
While the ISL59530 has an SDO (Serial Data Out) pin, it
does not have a register readback feature. The data on the
SDO pin is an exact replica of the incoming data on the SDI
pin, delayed by 15.5 SCLKs (an input bit is latched on the
rising edge of SLCK, and is output on SDO on the falling
edge of SLCK 15.5 SCLKs later). Multiple ISL59530’s can be
daisy-chained by connecting the SDO of one to the SDI of
the other, with SCLK and SLATCH common to all the daisy-
chained parts. After all the serial data is transmitted
(16 bits*n devices = 16*n SCLKs), the rising edge of
SLATCH will update the configuration registers of all n
devices simultaneously.
The ISL59530 offers a -3dB signal bandwidth of 300MHz.
Differential gain and differential phase of 0.025% and 0.05°
respectively, along with 0.1dB flatness out to 50MHz make
this ideal for multiplexing composite NTSC and PAL signals.
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible, three-wire
serial interface. The ISL59530 interface is designed to
facilitate both fast initialization and configuration changes.
On power-up, all outputs are initialized to the disabled state
to avoid output conflicts in the user’s system.
Digital Interface
The “Serial Timing Diagram” on page 19 and the “SERIAL
TIMING PARAMETERS” on page 19 show the timing
requirements for the serial interface.
The ISL59530 uses a serial interface to program the
configuration registers. The serial interface uses three
signals (SCLK, SDI, and SLATCH) for programming the
ISL59530, while a fourth signal (SDO) enables optional
daisy-chaining of multiple devices. The serial clock can run
at up to 5MHz (5Mbits/s).
FN6220.6
August 29, 2007
18
ISL59530
Serial Timing Diagram
SLATCH
SLATCH falling edge timing/placement is a “don’t care.”
Serial data is latched only on rising edge of SLATCH.
t
SL
t
SCLK
t
HD
t
w
t
SD
B15
(MSB)
B0
(LSB)
SDI
B1
B1
B2
B2
B0
(LSB)
B15
(PREVIOUS)
B0
B1
B2
SDO
(PREVIOUS)
(PREVIOUS))(PREVIOUS)
SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59530s. SDO changes on the falling edge of SCLK.
TABLE 1. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
t
≥200ns
0.50*t
≥20ns
≥20ns
≥20ns
SCLK period
t
Clock Pulse Width
Data Setup Time
Data Hold Time
W
t
SD
HD
t
t
Final SLCK rising edge (latching B15) to SLATCH rising edge
SL
Programming Model
The ISL59530 is configured by a series of 16-bit serial control words. The three MSBs (B15 through B13) of each serial word
determine the basic command:
TABLE 2. COMMAND FORMAT
B15
0
B14
0
B13
0
COMMAND
INPUT/OUTPUT: Maps input channels to output channels
OUTPUT ENABLE: Output enable for individual channels
GAIN SET: Gain (x1 or x2) for each channel
NUMBER OF WRITES
16 (1 channel per write)
4 (4 channels per write)
4 (4 channels per write)
1
0
0
1
0
1
0
0
1
1
BROADCAST: Enables broadcast mode and selects the input channel to be
broadcast to all output channels
1
1
1
CONTROL: Clamp on/off, operational/standby mode, and global output
enable/disable
1
Mapping Inputs to Outputs
Inputs are mapped to their desired outputs using the input/output control word. Its format is:
TABLE 3. INPUT/OUTPUT WORD
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
I
I
I
I
0
0
0
0
O
O
O
O
0
0
3
2
1
0
3
2
1
I :I form the 4-bit word indicating the input channel (0 to 15), and O :O determine the output channel which that input channel
3 0
3
0
will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59530, 16 INPUT/OUTPUT words must
be transmitted - one for each input channel.
Note: Broadcast Mode must be disabled when configuring input/output mapping. INPUT/OUTPUT words transmitted while in
Broadcast Mode will not be processed correctly and result in corrupt channel mapping when Broadcast Mode is disabled.
FN6220.6
August 29, 2007
19
ISL59530
Enabling Outputs
The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by
writing 4 serial words, each controlling a bank of four outputs at a time. The bank is selected by bits B9 and B8. The output enable
control word format is:
TABLE 4. OUTPUT ENABLE FORMAT
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
3
7
2
1
5
9
0
4
8
0
1
6
1
0
O
O
O
O
11
15
10
14
1
1
O
O
12
13
Setting the O bit = 0 tri-states the output. Setting the O bit = 1 enables the output if the Global Output Enable bit is also set (the
N
N
individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage).
Setting the Gain
The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G
G
G
G
G
G
G
G
G
G
3
7
2
6
1
5
9
0
4
8
0
1
1
0
G
G
G
G
11
10
14
1
1
G
G
12
15
13
Set G = 0 for a gain of x1 or 1 for a gain of x2.
N
Broadcast Mode
The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is:
TABLE 6. BROADCAST FORMAT
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Enable Broadcast
0
1
1
I
I
I
I
0
0
0
0
0
0
0
0
0
3
2
1
0: Broadcast Mode Disabled
1: Broadcast Mode Enabled
I :I form the 4 bit word indicating the input channel (0 to 15) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to
3 0
enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments
are restored.
Control Word
The ISL59530’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the
following control word should be sent:
TABLE 7. CONTROL WORD FORMAT
B15 B14 B13 B12 B11 B10
B9
B8 B7 B6 B5 B4 B3 B2
B1
B0
1
1
1
0
0
0
Clamp
0
0
0
0
0
0
0
Power
Global Output Enable
0: Clamp Disabled
1: Clamp Enabled
0: Standby
0: All outputs tri-stated
1: Operational 1: Individual Output Enable bits control outputs
The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to V
.
REF
Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for
individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have
sync tips (the Chroma/C signal in S-video and the Pb, Pr signals in Component video), will be severely distorted if run through a
DC-Restore/clamp function.
FN6220.6
August 29, 2007
20
ISL59530
For this reason, the ISL59530 must be in DC-coupled
mode (Clamp Disabled) to be compatible with S-video
and component video signals.
Linear Operating Region
In addition to bandwidth optimization, to get the best linearity
the ISL59530 should be configured to operate in its most
linear operating region. Figure 48 shows the differential gain
curve. The ISL59530 is a single supply 5V design with its
most linear region between 0.1 and 2V. This range is fine for
most video signals whose nominal signal amplitude is 1V.
The most negative input level (the sync tip for composite
video) should be maintained at 0.3V or above for best
operation.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video
system means better video resolution. Four sets of
frequency response curves are shown in Figure 47.
Depending on the switch configurations and the routing (the
path from the input to the output), bandwidth can vary
between 100MHz and 350MHz. A short discussion of the
trade-offs — including matrix configuration, output buffer
gain selection, channel selection, and loading — follows.
2
MUX, A = 2
V
0
MUX, A = 1
V
BROADCAST,
= 1
-2
A
V
BROADCAST,
= 2
-4
-6
A
V
-8
FIGURE 48. DIFFERENTIAL GAIN RESPONSE
-10
1M
10M
100M
1G
In a DC-coupled application, it is the system designer’s
responsibility to ensure that the video signal is always in the
optimum range.
FREQUENCY (Hz)
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
When AC coupling, the ISL59530’s Clamp (also called “DC
restore”) function automatically and continuously adjusts the
DC level so that the most negative portion of the video is
In multiplexer mode, one input typically drives one output
channel, while in broadcast mode, one input drives all 16
outputs. As the number of outputs driven increases, the
parasitic loading on that input increases. Broadcast Mode is
the worst-case, where the capacitance of all 16 channels
loads one input, reducing the overall bandwidth. In addition,
due to internal device compensation, an output buffer gain of
x2 has higher bandwidth than a gain of x1. Therefore, the
highest bandwidth configuration is multiplexer mode (with
each input mapped to only one output) and an output buffer
gain of x2.
always equal to V
.
REF
A discussion of the benefits of the DC restoration function
begins by understanding the Clamp circuit shown in
Figure 49. The incoming video signal is typically terminated
into 75Ω, then AC coupled through C , at which point it is
1
connected to the base of the buffer’s differential pair. These
components form the video path.
The Clamp function consists of Q , D , Q , D , the two
current sources, and the 3 switches controlled by the Clamp
1
1
2
2
The relative locations of the input and output channels also
have significant impact on the device bandwidth (due to the
layout of the ISL59530 silicon). When the input and output
channels are further away, there are additional parasitics as
a result of the additional routing, resulting in lower
bandwidth.
Enable signal. The V voltage is level-shifted up two
REF
diode drops (Q and D ) to the base of Q . If the voltage at
1
1
2
the cathode of D goes below V
, Q and D will turn on,
2
REF
2 2
keeping the IN voltage at V
. If the voltage at IN is
x
REF
x
greater than V
, Q and D are off and the IN node is
REF
2
2
x
high impedance. This is how the clamp function forces the
lowest portion of the video signal (the sync tip) to always be
The bandwidth does not change significantly with resistive
loading, as shown in the “Typical Performance Curves”.
However several of the curves demonstrate that frequency
response is sensitive to capacitance loading. This is most
significant when laying out the PCB. If the PCB trace length
between the output of the crosspoint switch and the back-
termination resistor is not minimized, the additional parasitic
capacitance will result in some peaking and eventually a
reduction in overall bandwidth.
equal to or greater than V
.
REF
To make sure that the sync tip is always equal to (not equal
to or greater than) V ; i is constantly sinking ~2µA of
REF
1
current from C . This causes each sync tip to be slightly
1
lower voltage than the previous sync tip, causing Q and D
2
2
to turn on at each sync tip and raise the voltage to V
. The
REF
2µA pull-down with a 0.1µF capacitor and a 15kHz HSYNC
frequency results in 1.3mV of “droop” across every line, or
FN6220.6
August 29, 2007
21
ISL59530
0.2% of the video signal. Because 1.3mV is only 0.2% of a
0.7V video signal, this droop is imperceptible to the human
eye.
the result of C = 0.1µF delivering acceptable droop and
IN
C
= 0.001µF producing excessive droop.
IN
When the clamp function is disabled in the CONTROL
register (Clamp = 0) to allow DC-coupled operation, the
I
current sinks/sources are disabled and the input
CLAMP
passes through the DC Restore block unaffected. In this
application, V may be tied to GND.
REF
Overlay Operation
The ISL59530 features an overlay feature that allows an
external video signal or DC level to be inserted in place of
Q2
that output channel’s video. When the OVER signal is
D1
N
D2
taken high, the output signal on the OUT pin is replaced
N
VREF
~0.4V
with the signal on the VOVER pin.
N
Q1
(110µA)
0.1µF
C2
D3
SS12
There are several ways the overlay feature can be used.
Toggling the OVER signal at the frame rate or slower will
N
INPUT
TO
BUFFER
INx
replace the video frame(s) on the OUT pin with the video
supplied on the VOVER pin.
N
N
VIDEO
IN
C1
0.1µF
R1
75
Another option (for OSD displays, for example), is to put a
DC level on the VOVER line and toggle the OVER signal
N
N
at the pixel rate to create a monocolor image “overlaid” on
channel N’s output signal.
i1
CLAMP
Finally, by enabling the OVER signal for some portion of
N
ENABLE
each line over a certain amount of lines, a picture-in-picture
function can be constructed.
FIGURE 49. DC RESTORE BLOCK DIAGRAM
It’s important to note that the overlay inputs do not have the
DC Restore function previously described - the overlay
signal is DC coupled into the output. It is the system
designer’s responsibility to ensure that the video levels are
in the ISL59530’s linear region and matching the output
channel’s offset and amplitude. One easy way to do this is to
run the video to be overlaid through one of the ISL59530’s
This is how the video is “DC-restored” after being AC
coupled into the ISL59530. The sync tip voltage will be equal
to V on the right side of C , regardless of the DC level of
REF
1
the video on the left side of C . Due to various sources of
1
offset in the actual clamp function, the actual sync tip level is
typically about 75mV higher than V
REF
(for V = 0.4V).
REF
unused channels and then into the VOVER input.
N
The OVER pins all have weak pull-downs, so if they are
N
unused, they can either be left unconnected or tied to GND.
C
= 100nF
IN
Power Dissipation and Thermal Resistance
With a large number of switches, it is possible to exceed the
+150°C absolute maximum junction temperature under
certain load current conditions. Therefore, it is important to
calculate the maximum junction temperature for an
application to determine if load conditions or package types
need to be modified to assure operation of the crosspoint
switch in a safe operating area.
C
= 1nF
IN
FIGURE 50. DC RESTORE VIDEO WAVEFORMS
The maximum power dissipation allowed in a package is
determined according to Equation 1:
It is important to choose the correct value for C . Too small a
IN
value will generate too much droop, and the image will be
visibly darker on the right than on the left. A C value that is too
large may cause the clamp to fail to converge. The droop rate
T
– T
AMAX
IN
JMAX
--------------------------------------------
PD
=
MAX
Θ
JA
(EQ. 1)
(dV/dt) is i /C volts/second. In general, the droop voltage
1
IN
should be limited to <1 IRE over a period of one line of video; so
for 1 IRE = 7mV, I = 10µA maximum, and an NTSC waveform
B
we will set C > 10µA*60µs/7mV = 0.086µF. Figure 50 shows
IN
FN6220.6
August 29, 2007
22
ISL59530
Where:
• T
• T
= Maximum junction temperature = +125°C
= Maximum ambient temperature = +85°C
JMAX
AMAX
• θ = Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
n
V
OUTi
R
Li
-----------------
PD
= V × I
+
(V – V ) ×
OUTi
MAX
S
SMAX
S
∑
(EQ. 2)
i = 1
Where:
• V = Supply voltage = 5V
S
• I
SMAX
= Maximum quiescent supply current = 360mA
= Maximum output voltage of the application = 2V
• V
• R
OUT
= Load resistance tied to ground = 150
LOAD
• n = 1 to 16 channels
n
V
OUTi
R
Li
-----------------
= 2.44W
PD
= V × I
+
(V – V ) ×
OUTi
MAX
S
SMAX
S
∑
(EQ. 3)
i = 1
The required θ to dissipate 2.44W is:
JA
T
– T
AMAX
JMAX
--------------------------------------------
= 16.4(°C/W)
Θ
=
JA
PD
MAX
(EQ. 4)
Table 8 shows θ thermal resistance results with a
JA
Wakefield heatsink and without heatsink and various airflow.
At the thermal resistance equation shows, the required
thermal resistance depends on the maximum ambient
temperature.
TABLE 8. θ THERMAL RESISTANCE [°C/W]
JA
Airflow [LFM]
0
250
14.3
7.0
500
13.0
6.0
750
12.6
4.7
No Heatsink
18
Wakefield
658-25AB
Heatsink
16.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6220.6
August 29, 2007
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ISL59530
Package Outline Drawing
L72.10x10C
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 0, 7/07
10.00
9.75
A
EXPOSED PAD AREA
X
B
Z
72
72
1
1
6
6
PIN 1
INDEX AREA
PIN #1 INDEX AREA
9.75
10.00
68X 0.50
4
0.23
(4X)
0.15
72X 0.50 ±0.1 mm
6.00 REF.
(4X)
TOP VIEW
0.100 M
C A B
BOTTOM VIEW
PACKAGE OUTLINE
R0.200
6.00
C0.400 X 45°
(4X)
10.00
(68X 0.50)
(72X 0.23)
R0.200
TYP.
(72X 0.20)
(72X 0.70)
1
TYPICAL RECOMMENDED LAND PATTERN
DETAIL “X”
72
R0.115
TYP.
DETAIL “Z”
11° ±1° ALL AROUND
Y
9.75
10.00
R0.200 MAX
ALL AROUND
SIDE VIEW
0.100 C
NOTES:
1. Dimensions are in millimeters.
0.65
0.85
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to JESD-MO220.
3.
0.19~ 0.245
Unless otherwise specified, tolerance : Decimal ± 0.05;
body tolerance: ±0.1mm
SEATING
PLANE
0.08
C
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
e
0.25 ±0.02
C
b
0.100 M
0.050 M
C
C
A B
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
DETAIL “Y”
FN6220.6
August 29, 2007
24
356 Ld PBGA Package
相关型号:
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