ISL59911IRZ [INTERSIL]
250MHz Triple Differential Receiver/ Equalizer with I2C Interface; 250MHz的三差分接收器/均衡器与I2C接口
| 型号： | ISL59911IRZ |
| 厂家： | 
Intersil |
| 描述： | 250MHz Triple Differential Receiver/ Equalizer with I2C Interface |
| 文件： | 总17页 (文件大小：2556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
250MHz Triple Differential Receiver/ Equalizer with I C
Interface
ISL59911
Features
The ISL59911 is a triple channel differential receiver and
equalizer optimized for RGB and YPbPr video signals. It
contains three high speed differential receivers with
programmable frequency compensation. The ISL59911
features manual or automatic offset calibration and ±4dB of
gain adjustment range with a resolution of 0.1dB.
• 250MHz -3dB bandwidth
• 5 Adjustable EQ bands: 100MHz, 20MHz, 6MHz, 1MHz, and
200kHz
• 3rd-order lowpass filter at output with programmable corner
• ±4dB fine gain control with 0.1dB (7-bit) resolution
• Offset calibration minimizes output offset voltage
The ISL59911 has a bandwidth of 250MHz and consumes only
110mA from a ±5V supply in normal operation.
• Decodes H
and V signals embedded in common
SYNC
SYNC
mode
2
When deasserted, the ENABLE pin puts the amplifiers into a
low power, high impedance state, minimizing power when not
needed and also allowing multiple devices to be connected in
parallel, allowing two or more ISL59911 devices to function as
a multiplexer.
• I C interface with four unique addresses
• ±5V supplies @ 110mA
• 32 Ld 5mm x 6mm QFN package
The ISL59911 can also directly decode the sync signals
encoded onto the common modes of three pairs of Cat 5 cable
(by an ISL59311, EL4543, or similar device) or it can output
the actual common mode voltages for each of the three
channels.
Applications
• KVM monitor extension
• Digital signage
• General-purpose twisted-pair receiving and equalization
• High-resolution security video
The ISL59911 is available in a 32 Ld QFN package and is
specified for operation over the full -40°C to +85°C
temperature range.
TWISTED-PAIR RGB VIDEO RECEIVER
+5V
-5V
*
*
CBYPASS
CBYPASS
x3
*See “Power Supply Bypassing” on
page 10 for more information.
x3
TERMINATION
NETWORK
V+ V- and
THERMAL
PAD
ISL59920
ISL59921
ISL59922
or
RIN
+
ROUT
GOUT
BOUT
UP TO 300m OF
1k
50
50
CAT X CABLE
ISL59311
OR
EL4543
75 x3
ISL59923
ISL59911
50
0.1µF
RIN
-
VIDEO
DELAY
LINE
TRIPLE
DIFFERENTIAL
VIDEO
RREF
GREF
BREF
GIN
GIN
+
-
TERMINATION
NETWORK
DRIVER
74HC04 or
SIMILAR
BIN
BIN
+
-
TERMINATION
NETWORK
HSOUT/RCM
VSOUT/GCM
BCM
+5V +5V
ADDR0
ADDR1
RP
RP
SCL
SDA
SYSTEM
MICRO-
NC
CONTROLLER
I2C INTERFACE
ENABLE
GND
FIGURE 1. TYPICAL APPLICATION CIRCUIT
September 2, 2011
FN7548.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL59911
Block Diagram
CMR
CMG
CMB
HSOUT/RCM
VSOUT/GCM
BCM
Sync Decoding
Equalizer
Differential
to Single-
Ended
RIN+
RIN-
Gain (R)
Gain (G)
Gain (B)
ROUT
GOUT
BOUT
100MHz
Conversion
+
Common
Mode
GIN+
GIN-
Noise
Filter
20MHz
6MHz
1MHz
200kHz
1
2 3
BIN+
BIN-
RREF
GREF
BREF
Extraction
Control Logic
I2C Interface
ENABLE
SDA
SCL
ADDR0
ADDR1
Pin Configuration
Ordering Information
ISL59911
PART NUMBER
PART
PACKAGE
(32 LD QFN)
TOP VIEW
(Notes 1, 2, 3)
MARKING
(Pb-free)
PKG. DWG. #
L32.5x6C
ISL59911IRZ
59911 IRZ
32 Ld QFN
ISL59911IRZ-EVALZ
NOTES:
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
ADDR1
25 V+
24 R
1
2
3
4
5
6
7
8
9
R
V-
D
OUT
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
V-
23 V-
R
R
+
-
22
V-
IN
IN
IN
G
THERMAL
PAD
R
21 G
IN
OUT
G
+
-
20 V+
G
B
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL59911. For more information on MSL please see
techbrief TB363.
EXPOSED DIEPLATE
SHOULD BECONNECTED
TO V- (-5V)
G
19
18
17
V+
B
IN
B
+
-
OUT
V-
B
B
IN
FN7548.0
September 2, 2011
2
ISL59911
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
2
2
1
ADDR1
Digital Input. I C Address select bit 1, used with ADDR0 to select the ISL59911 I C address (see “ISL59911 Serial
Communication” on page 13).
Note: If power supply sequencing cannot be guaranteed, ADDR1 must be held low during power-up.
See “Power Supply Sequencing” on page 10 for more information.
2
V-
Power Supply Pin. -5V for internal digital logic (internal logic operates between GND and V- ). Connect to the
D
D
same -5V supply as V-.
3
4
V-
Power Supply Pin. -5V supply for analog core of chip, also tied to thermal pad. Connect to a -5V supply.
Analog Input. Red positive differential input
R
G
B
+
IN
5
R
-
Analog Input. Red negative differential input
IN
6
+
Analog Input. Green positive differential input
IN
7
G
-
Analog Input. Green negative differential input
IN
8
+
Analog Input. Blue positive differential input
IN
9
B
-
Analog Input. Blue negative differential input
IN
V+
/R
10
11
Power Supply Pin. +5V supply for analog core of chip. Connect to a +5V supply.
HS
VS
Output configuration (Note 4) = 0: Digital Output. Decoded Horizontal Sync signal
Output configuration (Note 4) = 1: Analog Output. Red common-mode voltage at inputs
OUT CM
12
13
14
/G
OUT CM
Output configuration (Note 4) = 0: Digital Output. Decoded Vertical Sync signal
Output configuration (Note 4) = 1: Analog Output. Green common-mode voltage at inputs
B
Output configuration (Note 4) = 0: Digital Output. Logic low
Output configuration (Note 4) = 1: Analog Output. Blue common-mode voltage at inputs
CM
ENABLE
GND
Digital Input. Chip enable logic signal.
0V: All analog circuitry turned off to reduce current.
5V: Normal operation.
15
Power Supply Pin. Ground reference for ISL59911. This pin must be tied to GND.
Analog Input. Blue channel analog offset reference voltage. Typically tied to GND.
Power Supply Pin. -5V supply for blue output buffer. Connect to the same -5V supply as V-.
16
B
REF
17
V-
B
18
B
Analog Output. Blue output voltage referenced to B pin.
REF
OUT
19
V+
Power Supply Pin. +5V supply for blue output buffer. Connect to the same +5V supply as V+.
Power Supply Pin. +5V supply for green output buffer. Connect to the same +5V supply as V+.
B
G
20
V+
21
G
Analog Output. Green output voltage referenced to G
pin.
REF
OUT
22
V-
Power Supply Pin. -5V supply for green output buffer. Connect to the same -5V supply as V-.
Power Supply Pin. -5V supply for red output buffer. Connect to the same -5V supply as V-.
G
R
23
V-
24
R
Analog Output. Red output voltage referenced to R
pin.
REF
OUT
25
V+
Power Supply Pin. +5V supply for red output buffer. Connect to the same +5V supply as V+.
Power Supply Pin. Ground reference for ISL59911.
R
26
GND
27
G
R
Analog Input. Green channel analog offset reference voltage. Typically tied to GND.
Analog Input. Red channel analog offset reference voltage. Typically tied to GND.
Power Supply Pin. Ground reference for ISL59911. This pin must be tied to GND.
REF
28
REF
29
GND
SCL
2
30
31
Digital Input. I C Clock Input
2
SDA
Digital Input/Open-Drain Digital Output. I C Data Input/Output
2
2
32
ADDR0
Thermal Pad
Digital Input. I C Address select bit 0, used with ADDR1 to select the ISL59911 I C address.
Thermal Pad
Power Supply Pin. Connect to -5V supply plane with multiple vias to reduce thermal resistance and more
effectively spread heat from the ISL59911 to the PCB.
NOTE:
4. Output Configuration is controlled via Configuration Register 0x01, bit 0.
FN7548.0
September 2, 2011
3
ISL59911
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V+ = V+ = V+ = V+ , V- = V- = V- = V- = V-
Thermal Resistance (Typical)
32 Ld QFN (Notes 5, 6) . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
JA (°C/W)
31
θ
JC (°C/W)
R
G
B
R
G
B
D
Supply Voltage between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Maximum Absolute Slew Rate of V+ and V- . . . . . . . . . . . . . . . . . . . ±1V/µs
Maximum Continuous Output Current per Channel. . . . . . . . . . . . . ±30mA
Power Dissipation. . . . . . . . . . . . . . . . See “Power Dissipation” on page 12
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Ratings
2.1
Human Body Model (tested per JESD22-A114) . . . . . . . . . . . . . . . 7000V
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22C101C) . . . . . . . . . . . . 2000V
Latch Up (Tested per JESD78; Class II, Level A) . . . . . . . . . . . . . . . . . . . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
V+ Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
V- Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.5V to -5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V+ = V+ = V+ = V+ = +5V, V- = V- = V- = V- = V- = -5V, T = +25°C, all registers at default settings
R
G
B
R
G
B
D
A
(equalizer stages set to minimum boost, noise filter set to max bandwidth, x2 gain mode, GAIN = 0dB), all analog inputs at 0V, auto offset
DC
calibration executed, R = 5pF || (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified.
L
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
POWER SUPPLY
Positive Supply
Voltage (V+)
V+ = V+ = V+ = V+
B
4.5
5.5
-5.5
140
130
3.5
V
R
G
Negative Supply
Voltage (V-)
V- = V- = V- = V- = V-
D
-4.5
V
R
G
B
Operating Current Sum of currents into all V+ pins
110
105
2.5
mA
mA
mA
mA
dB
(I +)
D
Operating Current Sum of currents out of all V- pins,
(I -)
including thermal pad
Disabled Current Sum of currents into all V+ pins
(I +
D
ENABLE = 0V
ENABLE = 0V
)
D
DISABLED
Disabled Current Sum of currents into all V- pins,
0.35
55
2.5
(I -
)
including thermal pad
D DISABLED
PSRR
DC
Power Supply Rejection Ratio
AC PERFORMANCE
BW
Full Power Bandwidth
250
26
MHz
dB
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
Maximum Boost @ 100MHz
Maximum Boost @ 20MHz
Maximum Boost @ 6MHz
Maximum Boost @ 1MHz
Maximum Boost @ 200kHz
DC Gain Adjustment Range
All three 100MHz filters set to maximum
20MHz filter set to maximum
6MHz filter set to maximum
100MHz
20MHz
9.5
7.5
3.1
0.75
±4
dB
dB
6MHz
1MHz filter set to maximum
dB
1MHz
200kHz filter set to maximum
dB
0.2MHz
DC
dB
f
f
-3dB Corner Freq of Noise Filter, High Noise Filter Register = 0x0
250
50
MHz
MHz
V/ns
dBc
NOISE_MIN
-3dB Corner Freq of Noise Filter, Low
Output Slew Rate
Noise Filter Register = 0xF
= -1V to +1V
NOISE_MAX
SR
V
1
DIFF
IN
THD
Total Harmonic Distortion
f = 10MHz, 0.7V
input sine wave
-45
-60
P-P
FN7548.0
September 2, 2011
4
ISL59911
Electrical Specifications V+ = V+ = V+ = V+ = +5V, V- = V- = V- = V- = V- = -5V, T = +25°C, all registers at default settings
R
G
B
R
G
B
D
A
(equalizer stages set to minimum boost, noise filter set to max bandwidth, x2 gain mode, GAIN = 0dB), all analog inputs at 0V, auto offset
DC
calibration executed, R = 5pF || (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified. (Continued)
L
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 7)
TYP
24
(Note 7)
UNIT
MHz
V/ns
BW
Common Mode Amplifier Bandwidth 10k || 5pF load
CM
SR
Common Mode Slew Rate
V
= -0.5V to +1.5V
0.1
CM
IN
INPUT CHARACTERISTICS
CMIR
Common-mode Input Range
Differential signal passed undistorted.
Effective headroom is reduced by the p-p
amplitude of differential swing divided by 2.
-3.2/+4.0
V
CMRR
Common-mode Rejection Ratio
Measured at 100kHz
Measured at 10MHz
88
58
0.5
20
dB
dB
pF
C
Differential Input Capacitance
Differential Input Resistance
Capacitance between V
and V
INP INM
INDIFF
R
Resistance between V + and V
IN
-
kΩ
INDIFF
IN
(due to common mode input resistance)
C
CM Input Capacitance
Capacitance from V + and V - to GND
IN IN
1.3
25
pF
kΩ
V
INCM
R
CM Input Resistance
Resistance from V + and V - to GND
IN IN
INCM
V
Max P-P Differential Input Range
Delta V + - V - when slope gain falls to 0.9
IN IN
1.9
-20
INDIFF_P-P
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
Output Drive Current
Output Offset Voltage
±2.75
±22
-8
V
OUT
I
R
= 10Ω, V + - V - = ±2V
IN IN
mA
mV
Ω
OUT
L
V(V
)
Post-offset calibration
+5
OUT OS
R(V
)
CM Output Resistance of VCM_R/G/B At 100kHz
(CM Output Mode)
2.5
CM
Gain
Gain
x1 mode
x2 mode
0.95
1.9
1.0
2.0
1.05
2.1
V/V
ΔGain
Channel-to-Channel Gain Mismatch
x1 and x2 modes
±3
%
O
Integrated Noise at Output
Inputs @ GND through 50Ω.
0m of Equalization (Nominal)
300m of Equalization
4
20
mV
RMS
NOISE
SYNCOUT
SYNCOUT
High Level output on VS/HS
10k || 5pF load, SYNC Output Mode
10k || 5pF load, SYNC Output Mode
V+ - 1.5
V
V
HI
OUT
Low Level output on VS/HS
0.4
LO
OUT
SCL, SDA PINS
2
f
Maximum I C Operating Frequency
SDA Output Low Level
Input High Level
400
3
kHz
V
MAX
V
V
V
V
V
= 6mA
0.4
1.5
±1
OL
SINK
V
IH
Input Low Level
V
IL
Input Hysteresis
0.55
V
HYST
LEAKAGE
I
Input Leakage Current
µA
ns
t
Maximum Width of Glitch on SCL (or
SDA) Guaranteed to be Rejected
50
3
GLITCH
ENABLE, ADDR0, ADDR1 PINS
V
V
Input High Level
V
V
IH
Input Low Level
0.8
±1
IL
I
Input Leakage Current
µA
LEAKAGE
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7548.0
September 2, 2011
5
ISL59911
Typical Performance Curves
12
10
8
10
5
x2
0
x1
-5
CODE 3
-10
-15
-20
-25
-30
-35
-40
6
CODE 2
4
2
CODE 1
100
0
CODE 0
-2
0.01
0.1
1
10
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. FREQUENCY RESPONSE vs 100MHz BITS 1:0
FIGURE 2. NOMINAL FREQUENCY RESPONSE WITH DEFAULT
SETTINGS
15
14
13
12
11
10
9
8
7
6
5
20
19
18
17
16
15
14
13
12
11
10
9
CODE 3
CODE 7
CODE 7
CODE 6
CODE 5
CODE 2
CODE 4
8
4
3
2
1
7
6
5
4
CODE 1
3
0
2
-1
-2
-3
-4
1
CODE 0
10
0
-1
-2
CODE 0
0.01
0.1
1
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 4. FREQUENCY RESPONSE vs 100MHz BITS 4:2
FIGURE 5. FREQUENCY RESPONSE vs 100MHz BITS 7:5
20
12
CODE 0F
19
18
17
16
15
14
13
12
11
10
9
11
10
9
CODE 0F
8
7
6
5
8
4
7
3
6
5
2
4
1
3
CODE 00
2
0
1
CODE 00
10
0
-1
0.1
1
10
100
1000
0.01
0.1
1
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 6. FREQUENCY RESPONSE vs 20MHz BITS 7:4
FIGURE 7. FREQUENCY RESPONSE vs 6MHz BITS 3:0
FN7548.0
September 2, 2011
6
ISL59911
Typical Performance Curves(Continued)
6
2.0
1.5
1.0
0.5
0
CODE 0F
5
CODE 0F
4
3
2
1
CODE 00
100
-0.5
-1.0
0
CODE 00
10
-1
0.01
0.1
1
100
1000
0.01
0.1
1
10
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 8. FREQUENCY RESPONSE vs 1MHz BITS 7:4
FIGURE 9. FREQUENCY RESPONSE vs 200kHz BITS 3:0
10
CODE 00
CODE 01
0
CODE 0A
-10
-20
-30
-40
-50
-60
CODE 0B
CODE 0F
CODE 09
10
100
FREQUENCY (MHz)
1000
FIGURE 10. FREQUENCY RESPONSE vs LOW PASS FILTER BITS 3:0
FN7548.0
September 2, 2011
7
ISL59911
Register Listing
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
3:0
7:4
0
FUNCTION NAME
Device Revision
Device ID
DESCRIPTION
0 = initial silicon, 1 = first revision, etc.
0x10 = ISL59911
0x00
Device ID (read only)
0x01
General Configuration (0x02)
Output Configuration 0: H
SYNC
+ V (like EL9111 and ISL59910)
SYNC
1: V (like EL9112 and ISL59913)
CM
1
Nominal Gain
Power Down
100MHz Stage 1
100MHz Stage 2
100MHz Stage 3
6MHz
0: 0dB (1V/V)
1: 6dB (2V/V)
2
0: Normal Operation
1: Low power mode, all amplifiers turned off
0x02
High Adjust (0x00)
1:0
4:2
7:5
3:0
7:4
3:0
7:4
3:0
00b: Min boost
11b: Max boost
000b: Min boost
111b: Max boost
000b: Min boost
111b: Max boost
0x03
0x04
Mid Adjust (0x00)
Low Adjust (0x00)
0000b: Min boost
1111b: Max boost
20MHz
0000b: Min boost
1111b: Max boost
200kHz
0000b: Min boost
1111b: Max boost
1MHz
0000b: Min boost
1111b: Max boost
0x05
0x06
Noise Filter Adjust (0x00)
Red Channel Gain (0x40)
Noise Filter
Adjusts -3dB frequency of noise filter at output
0x0: Max frequency
0xF: Min frequency
6:0
6:0
6:0
6:0
Red Gain
0x00: -6dB
0x40: 0dB
0x7F: +6dB
Note: Due to gain trim at production test, the minimum
guaranteed usable gain range is ±4dB.
0x07
0x08
0x09
Green Channel Gain (0x40)
Blue Channel Gain (0x40)
Green Gain
Blue Gain
Red Offset
0x00: -6dB
0x40: 0dB
0x7F: +6dB
Note: Due to gain trim at production test, the minimum
guaranteed usable gain range is ±4dB.
0x00: -6dB
0x40: 0dB
0x7F: +6dB
Note: Due to gain trim at production test, the minimum
guaranteed usable gain range is ±4dB.
Red Channel Manual Offset (0x00)
(Default is auto-calibrated)
0x00: -400mV Offset
0x7F: +400mV Offset
(Output Referred)
7
Manual Offset Control 0: Offset is auto calibrated - value in bits 6:0 is ignored
(Red)
1: Offset DAC set to value in bits 6:0
0x0A
Green Channel Manual Offset (0x00)
(Default is auto-calibrated)
6:0
Green Offset
0x00: -400mV Offset
0x7F: +400mV Offset
(Output Referred)
7
Manual Offset Control 0: Offset is auto calibrated - value in bits 6:0 is ignored
(Green) 1: Offset DAC set to value in bits 6:0
FN7548.0
September 2, 2011
8
ISL59911
Register Listing(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
6:0
FUNCTION NAME
Blue Offset
DESCRIPTION
0x0B
Blue Channel Manual Offset (0x00)
(Default is auto-calibrated)
0x00: -400mV Offset
0x7F: +400mV Offset
(Output Referred)
7
0
1
Manual Offset Control 0: Offset is auto calibrated - value in bits 6:0 is ignored
(Blue)
1: Offset DAC set to value in bits 6:0
0x0C
Offset Calibration Control (0x00)
Start Cal
Set to 1 to initiate offset calibration. Bit is reset to 0 when
calibration is complete (in ~3µs or less).
Cal Mode
0: Analog inputs disconnected from external pins and
internally shorted together during calibration.
1: Analog inputs remain connected to external circuitry
during calibration. Useful for calibrating out system-wide
offsets. External offsets of up to ~±160mV can be
eliminated.
2
Short Inputs
0: Normal operation
1: Inputs shorted together (independent of the Cal Mode bit)
0x0D - 0x12 Reserved
0x13 Initialization
7:0
7:0
Reserved
Reserved. Do not write anything to these addresses.
Initialization
After initial power on, write 0x06 to this register,
followed by a write of 0x00 to this register.
NOTE: All registers are read/write unless otherwise noted.
FN7548.0
September 2, 2011
9
ISL59911
Input Termination
Applications Information
The differential input signal from a Cat x cable should have a
characteristic impedance of 100Ω and is therefore terminated by
the two 50Ω resistors across the differential inputs, as shown in
Figure 1 on page 1. The 50Ω resistor and 0.1µF capacitor
connected to the midpoint keep the AC impedance low at high
frequencies, providing common-mode AC termination while
allowing the low-frequency component of the common mode
(containing the embedded H and V sync signals) to move freely.
The 1k resistor provides a higher-impedance DC path to ground,
so the common mode voltage is set to 0V when no cable is
connected.
ISL59911 Overview
Differential video signals sent over long distances of twisted pair
wire encounter are increasingly attenuated as frequency and
distance increase, resulting in loss of high frequency detail
(blurring). The exact loss characteristic is a function of the wire
gauge, whether the pairs are shielded or unshielded, the
dielectric of the insulation, and the length of the wire. The loss
mechanism is primarily skin effect.
The signal can be restored by applying a filter with the inverse
transfer function of the cable to the far end signal. The ISL59911
is designed to compensate for losses due to long cables, and
incorporates the functionality and flexibility to match a wide
variety of loss characteristics.
Device Initialization
To ensure that the ISL59911 functions properly, the following
steps must be taken after initial power-up:
Power Supply Sequencing
1. Ensure that the ENABLE pin is high.
Power to the ISL59911’s negative supply pins should be applied
before the positive supply ramps. As shown in Figure 11,
V- should reach -3V before V+ reaches 1V.
2. Through the serial interface, write 0x06 to register 0x13, then
write 0x00 to the same register. This ensures that the DC gain
of the device is accurate.
If this power supply sequence cannot be guaranteed, then the
ADDR1 pin must be held low during power-up until V- has crossed
-3V.
3. Perform an offset calibration by setting bit 0 of register 0x0C
to 1. The bit is automatically resets to 0 upon completion of
calibration. If offset calibration is not performed, the
ISL59911 may have large DC offsets.
V+
+1V
Communicating with the ISL59911
The ISL59911 is controlled through the industry standard I C
t > 0ms
2
V-
-3V
serial interface. Adjustments to the frequency response over five
distinct frequency bands, gain and offset fine-tuning, and several
other functions are made through this interface as described in
the Register Listing starting on page 8. This level of control
enables much more accurate and flexible response matching
than previous solutions.
FIGURE 11. POWER SUPPLY SEQUENCING
If this power supply sequencing requirement is not met and if
ADDR1 is high, there is a small chance that the ISL59911 factory
trim will become permanently corrupted.
The ISL59911 also has an external Chip Enable (ENABLE) pin,
allowing hardware control of whether the chip is operating or in a
low-power standby mode.
Power Supply Bypassing
For best performance, all ICs need bypass capacitors across
some or all of their power supply pins. The best high-frequency
decoupling is achieved with a 0.1μF capacitor between each
power supply pin and GND. Adjacent supply pins (pins 2 and 3,
19 and 20, 22 and 23, and 25 and 26) can share the same
decoupling capacitor. Keep the path to both pins as short as
possible to minimize inductance and resistance. Pins 3 and 10
provide power to the internal equalizer, while supply pins
between pin 17 and pin 25 provide power to the analog output
buffers. For best performance, the equalizer supplies should be
somewhat isolated from the buffer supplies. A separate path
back to the power source should be adequate.
Programming the ISL59911 for a Specific
Cable and Length
Determining the optimum settings for the ISL59911’s multiple
equalizer frequencies, gain, and low pass filter can initially seem
quite challenging. To equalize any cable type of any length,
transmit a step (a pure white screen works well, since the video
in H
region is black) and adjust the filters, starting at
SYNC
200kHz and working up to 100MHz, so that the response at the
receive end is as flat as possible. Once the response is flat, the
gain should be adjusted as necessary to compensate for the DC
losses.
A 10μF capacitor on each of the V+ and V- supplies provides
sufficient low-frequency decoupling. The 10μF capacitors do not
need to be particularly close to the ISL59911 to be effective, but
should still have a low-impedance path to the supply rails.
This technique is not usually practical in the field, where the best
solution is a lookup table for each cable type. Table 1 shows the
best values for a typical Cat 5 cable.
In many mixed-signal ICs, separation of the analog and digital
supplies and grounds is critical to prevent digital noise from
appearing on the analog signals. Because the digital logic in the
ISL59911 is only active during a one-time configuration, the
analog and digital supply pins (and grounds) can be connected
together, simplifying PCB layout and routing.
FN7548.0
September 2, 2011
10
ISL59911
similar delay line, termination to ground is not necessary,
TABLE 1. Cat 5 LOOK-UP TABLE
however, a ~75Ω series resistor at each output pin will help
isolate the outputs from the PCB trace capacitance, improving
the flatness of the frequency response.
Length
(m)
Reg
2
Reg
3
Reg
4
Reg
5
Reg
6-8
0
0x00
0x20
0x24
0x25
0x49
0x69
0x89
0x92
0x96
0x97
0xB7
0xD7
0xF7
0x00
0x11
0x22
0x33
0x44
0x55
0x75
0x86
0x96
0xA7
0xB8
0xC9
0xEA
0x00
0x10
0x21
0x31
0x42
0x53
0x62
0x72
0x82
0x93
0xB2
0xC3
0xD2
0x00
0x00
0x01
0x01
0x01
0x02
0x02
0x04
0x06
0x08
0x09
0x0A
0x0C
0x40
0x40
0x44
0x44
0x48
0x48
0x4C
0x4C
0x50
0x50
0x54
0x54
0x58
When ENABLE is low, the R , G
, and B outputs are put
OUT
OUT OUT
25
in a high-impedance state, allowing multiple ISL59911 devices
to be configured as a multiplexer by paralleling their outputs and
using ENABLE to select the active RGB channel.
50
75
Common Mode and H
/V
Outputs
SYNC SYNC
100
125
150
175
200
225
250
275
300
In addition to the incoming differential video signals, the
ISL59911 also processes the common mode voltage on the
differential inputs and can output the signal in one of two ways
(as determined by the Output Configuration bit in register 0x01).
When the Output Configuration bit is set to 0 (the default), the
common mode input voltages are sent to comparators that
decode the voltage into H
and V signals according to
SYNC
SYNC
the EL4543/ISL59311 standard encoding scheme shown in
Figure 13 and in Table 2 on page 11. The H signal appears
SYNC
signal on VS
on the HS
/R pin, the V
/G . The B
OUT CM SYNC
OUT CM
CM
output pin is held at a logic low (0v).
To minimize noise coupling into the analog section from the sync
Offset Calibration
output drivers, the HS and VS outputs have limited current
OUT
OUT
Historically, programmable video equalizer ICs have had large
and varying offset voltages, often requiring external circuitry
and/or manual trim to reduce the offset to acceptable levels. The
ISL59911 improves upon this by adding an offset calibration
drive, and should be buffered by 74HC04 or similar CMOS
buffers, as shown in Figure 1, before driving any significant loads
(such as a VGA cable).
When the Output Configuration bit is set to 1, buffered versions
of the three common mode input voltages are available on the
2
circuit that, when triggered by setting bit 0 of I C register 0x0C,
shorts the inputs together internally, compares the R , G
,
OUT OUT
R
, G , and B pins. Making the raw common mode signal
CM CM CM
and B
OUT
voltages to their corresponding R , G , and B
REF REF REF
available allows for custom encoding schemes and/or
transmission of analog signals on the video signals’ common
mode.
voltages and uses a DAC with a successive-approximation
technique to minimize the delta between them (see Figure 12).
VIN+
EQ AND
3.0V
VOUT
VIN-
BLUE CM
GAIN
2.0V
OUTPUT
BUFFER
INPUT
BUFFER
DAC
3.0V
GREEN CM
2.0V
SAR
LOGIC
3.0V
RED CM
2.0V
COMPARATOR
2.5V
VREF
V
SYNC
0V
2.5V
0V
FIGURE 12. OFFSET CALIBRATION (ONE CHANNEL SHOWN)
H
SYNC
When the ISL59911 is first powered up, the offset error is
undefined until an offset calibration is performed. The output
offset voltage of the ISL59911 also varies as the filter and gain
settings are adjusted. To minimize offset, always perform an
offset calibration after finalizing the filter and gain settings.
TIME (0.5ms/DIV)
FIGURE 13. H AND V SYNC SIGNAL ENCODING
TABLE 2. H AND V SYNC DECODING
An offset calibration only takes about 3μs, so offset calibrations
can be performed after every register write without adding
significant time to the adjustment process. This minimizes offset
throughout the entire equalization adjustment procedure.
RED CM
2.5V
GREEN CM
3.0V
BLUE CM
2.0V
H
V
SYNC
SYNC
Low
Low
High
High
Low
High
Low
High
3.0V
2.0V
2.5V
2.0V
3.0V
2.5V
Output Signals
2.5V
2.0V
3.0V
The R , G , and B
outputs can drive either a standard
OUT OUT OUT
75Ω video load in x1 gain mode or a 150Ω source-terminated
load (75Ω in series at source end [ISL59911 output pin], plus
75Ω termination to ground at receive end) in x2 mode. If the
output of the ISL59911 is going directly into an ISL59920 or
FN7548.0
September 2, 2011
11
ISL59911
Power Dissipation
The ISL59911 is designed to operate with ±5V supply voltages.
The supply currents are tested in production and guaranteed to
be less than 140mA per channel. Operating at ±5V power supply,
the total power dissipation is shown by Equation 1:
V
OUTMAX
R
L
------------------------
PD
= 2 × V × I
+ 3(V - V ) ×
OUTMAX
MAX
S
SMAX
S
(EQ. 1)
Where:
• PD
= Maximum power dissipation
MAX
• V = Supply voltage = 5V
S
• I
MAX
= Maximum quiescent supply current = 140mA
= Maximum output voltage swing of the
• V
OUTMAX
application = 2V
• The 3 term comes from the number of channels
• R = Load resistance = 150Ω
L
• PD
= 1.4W
required for long term reliable operation can be calculated.
MAX
θ
JA
This is done using Equation 2:
(EQ. 2)
θ
= (T – T ) ⁄ PD= (46°C) ⁄ W
J A
JA
Where:
T is the maximum junction temperature (+150°C)
J
T is the maximum ambient temperature (+85°C)
A
For a 32 Ld QFN package in a proper layout PCB heatsinking
copper area, 31°C/W θ thermal resistance can be achieved. To
JA
disperse the heat, the bottom heatspreader must be soldered to
the PCB. Heat flows through the heatspreader to the circuit board
copper, then spreads and converts to air. Thus the PCB copper
plane becomes the heatsink. This has proven to be a very
effective technique. A separate application note that details the
32 pin QFN PCB design considerations is available.
FN7548.0
September 2, 2011
12
ISL59911
recognizes its current address (1000101b) and respond
ISL59911 Serial Communication
normally, while the remaining devices will have an address of
1000100b and therefore ignore the communication. This
requires one additional GPIO for each ISL59911, but it permits
as many ISL59111 devices to be controlled as desired, without
any additional external logic.
Overview
The ISL59911 uses the I C serial bus protocol for
2
communication with its host (master). SCL is the Serial Clock
line, driven by the host, and SDA is the Serial Data line, which can
be driven by all devices on the bus. SDA is open drain to allow
multiple devices to share the same bus simultaneously.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START command
by taking SDA low while SCL is high (Figure 14). The ISL59911
continuously monitors the SDA and SCL lines for the start
condition and does not respond to any command until this
condition has been met. The host then transmits the 7-bit serial
address plus a R/W bit, indicating if the next transaction is a
Read (R/W = 1) or a Write (R/W = 0). If the address transmitted
matches that of any device on the bus, that device must respond
with an ACKNOWLEDGE (Figure 15).
Communication is accomplished in three steps:
1. The host selects the ISL59911 it wishes to communicate
with.
2. The host writes the initial ISL59911 Configuration Register
address it wishes to write to or read from.
3. The host writes to or reads from the ISL59911s Configuration
Register. The ISL59911s internal address pointer auto
increments, so to read registers 0x00 through 0x1B, for
example, one would write 0x00 in step 2, then repeat step
three 28 times, with each read returning the next register
value.
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be written
to or read from the slave. Communication with the selected
device in the selected direction (read or write) is ended by a STOP
command, where SDA rises while SCL is high (Figure 14), or a
second START command, which is commonly used to reverse
data direction without relinquishing the bus.
The ISL59911 has a 7-bit address on the serial bus,
10001<a1><a0>b, where 10001 is fixed and a0 and a1 are the
state of the ADDR0 and ADDR1 pins, respectively. This allows up
to four ISL59911 devices to be independently controlled by the
same serial bus.
2
The I C spec requires that data on the serial bus must be valid
for the entire time SCL is high (Figure 16). To ensure incoming
data has settled, data written to the ISL59911 is latched on a
delayed version of the rising edge of SCL.
To control more than four devices (or more than two, if ADDR1 is
tied low as discussed in “Power Supply Sequencing” on page 10)
2
from a single I C host, use a “chip select” signal for each device.
When the contents of the ISL59911 are being read, the SDA line
is updated after the falling edge of SCL, delayed and deglitched
in the same manner.
2
For example, in the firmware, the host can fix the I C address to
1000101b for all devices, selecting the device to be
communicated to by taking its ADDR0 pin high while the ADDR0
pins of all other devices remain low. The selected device
SCL
SDA
START
STOP
FIGURE 14. VALID START AND STOP CONDITIONS
SCL FROM
HOST
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN7548.0
September 2, 2011
13
ISL59911
SCL
SDA
DATA CHANGE
DATA STABLE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
Configuration Register Write
Figure 17 shows two views of the steps necessary to write one or
more words to the Configuration Register.
Signals the beginning of serial I/O
START Command
ISL59911 Serial Bus
R/W
ISL59911 Device Select Address Write
The first 7 bits of the first byte select the ISL59911 on the 2-wire
bus at the address set by the ADDR0 and ADDR1 pins. The
R/W bit is a 0, indicating that the next transaction will be a write.
0
1
0
0
0
1
ADDR1 ADDR0
ISL59911 Register Address Write
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
This is the address of the ISL59911’s Configuration Register
that the following byte will be written to.
ISL59911 Register Data Write(s)
This is the data to be written to the ISL59911’s Configuration
Register. Note: The ISL59911 Configuration Register’s address
pointer auto-increments after each data write. Repeat this step to
write multiple sequential bytes of data to the Configuration Register.
(Repeat if desired)
Signals the ending of serial I/O
STOP Command
S
T
A
R
T
S
T
O
P
Serial Bus
Address
Register
Address
Data
Write*
* The Data Write step can be repeated to write to the
ISL59911’s Configuration Register sequentially, beginning at
the Register Address written in the previous step.
Signals from
the Host
a a a a a a a 0 AAAAAAAA d d d d d d d d
SDA Bus
A
C
K
A
C
K
A
C
K
Signals from
the ISL59911
FIGURE 17. CONFIGURATION REGISTER WRITE
FN7548.0
September 2, 2011
14
ISL59911
Configuration Register Read
Figure 18 shows two views of the steps necessary to read one or
more words from the Configuration Register.
Signals the beginning of serial I/O
START Command
ISL59911 Serial Bus
R/W
ISL59911 Device Select Address Write
The first 7 bits of the first byte select the ISL59911 on the 2-wire
bus at the address set by the ADDR0 and ADDR1 pins.
R/W = 0, indicating that the next transaction will be a write.
0
1
0
0
0
1
ADDR1 ADDR0
ISL59911 Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0
This sets the initial address of the ISL59911’s Configuration
Register for subsequent reading.
Ends the previous transaction and starts a new one.
START Command
ISL59911 Serial Bus
R/W
ISL59911 Serial Bus Address Write
This is the same 7-bit address that was sent previously, however
the R/W bit is now a 1, indicating that the next transaction(s) will
be a read.
1
1
0
0
0
1
ADDR1 ADDR0
ISL59911 Register Data Read(s)
D7
D6
D5
D4
D3
D2
D1
D0
This is the data read from the ISL59911’s Configuration Register.
Note: The ISL59911 Configuration Register address pointer
auto-increments after each data read: repeat this step to read
multiple sequential bytes of data from the Configuration Register.
(Repeat if desired)
STOP Command
Signals the ending of serial I/O
R
E
S
T
A
R
T
S
T
A
R
T
S
Serial Bus
Address
Serial Bus
Address
Register
Address
Data
Read*
Signals from
the Host
* The Data Read step may be repeated to
T
read from the ISL59911’s Configuration
Register sequentially, beginning at the
Register Address written in the previous two
steps.
O
P
A
C
K
a a a a a a a 0 AAAAAAAA
a a a a a a a 1
SDA Bus
A
C
K
A
C
K
A
C
K
d d d d d d d d
Signals from
the ISL59911
FIGURE 18. CONFIGURATION REGISTER READ
FN7548.0
September 2, 2011
15
ISL59911
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7548.0
CHANGE
9/2/11
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL59911
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
FN7548.0
September 2, 2011
16
ISL59911
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x6C (One of 10 Packages in MDP0046)
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
SYMBOL
MIN
0.80
0.00
NOMINAL
0.90
MAX
1.00
0.05
NOTES
B
A
A1
D
-
0.02
-
1
2
3
5.00 BSC
3.50 REF
6.00 BSC
4.50 REF
0.40
-
PIN #1
I.D. MARK
D2
E
-
-
E
E2
L
-
0.35
0.23
0.45
0.27
-
b
0.25
-
2X
0.075 C
c
0.20 REF
0.50 BSC
32 REF
7 REF
-
e
-
2X
0.075 C
N
4
TOP VIEW
ND
NE
6
9 REF
5
0.10 M C A B
b
Rev 0 9/05
NOTES:
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
PIN #1 I.D.
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(E2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
5
NE
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
7
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
2
SEATING
PLANE
A
C
0.08 C
(L)
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
A1
DETAIL X
N LEADS
SIDE VIEW
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7548.0
September 2, 2011
17
相关型号：
ISL59920IRZ-TR
IC SPECIALTY CONSUMER CIRCUIT, PQCC20, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-20, Consumer IC:Other
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