ISL6172DRZA-T [INTERSIL]
Dual Supply Hot Swap Power Distribution Control to <1V;
| 型号： | ISL6172DRZA-T |
| 厂家： | 
Intersil |
| 描述： | Dual Supply Hot Swap Power Distribution Control to <1V |
| 文件： | 总15页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6172
®
Data Sheet
June 2004
FN9158
Dual Low Voltage Hot Swap Controller
Features
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V bias supply voltage range with a second lower
voltage rail down to less than 1V. It features a charge pump for
driving external N-Channel MOSFETs, regulated current
protection and duration, output undervoltage monitoring and
reporting, optional latch-off or retry response, and adjustable
soft-start.
• Dual Supply Hot Swap Power Distribution Control to <1V
• Less than 1µs Response Time to Dead Short
• Overcurrent Circuit Breaker Fault Isolation and
Programmable Current Regulation Level Protection
Functions
• Programmable Current Regulation Duration
• Charge Pump Allows the use of N-Channel MOSFETs
• Rail Independent Control, Monitoring and Reporting I/O
• Adjustable Ramp up for Inrush Protection During Turn On
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6172 offers a
latched output or indefinite auto retry mode of operation.
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Latch-off or Auto Reset Response to Fault Functions
• Adjustable Current Regulation Threshold as low as 20mV
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
Ordering Information
TEMP.
PKG.
PART NUMBER RANGE (°C)
PACKAGE
DWG. #
ISL6172DRZA *
ISL6172DRZA-T*
0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
ISL6172EVAL3 Evaluation Platform
• Pb-free
* Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap/Electronic Breaker Circuits
• Network Hubs, Routers, Switches
Pinout
28 LEAD QFN
• Hot Swap Bays, Cards and Modules
TOP VIEW
Rsns1
V1(out)
V1(in)
28
27
26
25
24
23
22
SNS2
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
VS1
SNS1 GT1 VO1
EN1EN2
UV1
PG1
RTR/LTCH
BIAS
FLT1
SS1
OCREF
SS2
CPQ+
19
SS2
18 GT2
17
CPQ-
CPVDD
ISL6172
GT1
FLT1
PG1
CT1
FLT2
FLT2
PG2
UV2
PGND
GND
16 PG2
15 CT2
CT1 CT2 VS2
SNS2 GT2 VO2
8
9
10
11
12
13
14
V2(OUT)
V2(in)
Rsns2
FIGURE 1. TYPICAL APPLICATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6172
Block Diagram
Io
LOAD
Vo
Vin
Rsns
Q
Rset
Iset
Current
Limit
10V
20uA
Amplifier
with “Quick-Slew”
Soft Start
Amplifier
-
CPVDD
-
+
10uA
30uA
SS1
+
3K
Css
+
-
WOC
FLT1
Comparator
OC
Timer
&
1.178V
+
-
Iref
OCREF
Rref
CPVDD
Logic
OC
Iref
4
Current
Mirror
Comparator
10uA
PG1
CT1
BIAS
+
-
10K
Ct
EN1
1.178V
633mV
Timeout
Comparator
Rs1
BIAS
-
10K
UV1
RTR/LTCH
BIAS
+
UV
Comparator
Rs2
CPQ+
Cp
10V(out)
X2
X2
Charge
Pump
Charge
Pump
CPQ-
CPVDD
Cv
633mV
1.178V
POR and
Bandgap
ISL6172
FIGURE 2. ISL6172 - INTERNAL BLOCK-DIAGRAM OF ONE CHANNEL
2
ISL6172
Pinout
28 LEAD QFN
TOP VIEW
28
27
26
25
24
23
22
SNS2
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
19
SS2
18 GT2
17
GT1
FLT1
PG1
CT1
FLT2
16 PG2
15 CT2
8
9
10
11
12
13
14
Pin Descriptions
PIN
NAME
FUNCTION
DESCRIPTION
1
SNS1
Current Sense Input
This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.
2
3
VO1
SS1
Output Voltage 1
This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for OC comparator input and for SS control.
Soft-Start Duration Set A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
Input
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor is
discharged. If common capacitor is used (by tying SS1, SS2 together and the capacitor to GND from
the connection) then both the outputs track each other as they ramp up.
4
5
6
7
GT1
FLT1
PG1
CT1
Gate Drive Output
Fault Output
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
VIN1+5.3V with a 20µA source.
This is an open drain output. It asserts (pulls low) once the current regulation duration (determined
by the CTx timeout cap) has expired.
Power Good Output
Timer Capacitor
This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
A capacitor from this pin to ground controls the current regulation duration from the onset of current
regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches
V
the GATE outputs are pulled down and the FLT(s) is asserted.
CT_Vth
The duration of current limit time-out = (C
*1.178)/10µA
TIM
When the OC comparator trips AND the RTR/LTCH pin is left floating (or pulled high), the IC’s faulty
channel remains shut down for 64 cycles (each cycle length is equal to the current limit time-out
duration).
8
9
RTR/
LTCH
Retry Or Latch Input
This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left
floating), the IC will shut down upon OC detection. If it is pulled low, the IC will go into retry mode
after an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down
for 64 cycles and will try to come out of it on 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.
GND
Chip Gnd
This pin is also internally shorted to the metal tab at the bottom of the IC.
3
ISL6172
Pin Descriptions (Continued)
PIN
NAME
PGND
CPQ-
FUNCTION
DESCRIPTION
Charge pump ground. Both GND and PGND must be tied together.
10
11
ChargePumpCapacitor Flying cap lowside
Low Side
12
BIAS
Chip Bias Voltage
Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a
supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
13
14
CPQ+
ChargePumpCapacitor Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.
High Side
CPVDD Charge Pump Output
This is the voltage used for some internal pullups and bias. Use of 0.47µF (minimum) is
recommended.
15
16
17
18
19
CT2
PG2
FLT2
GT2
SS2
Timer Capacitor
Power Good Output
Fault Output
Same function as pin 7
Same function as pin 6
Same as pin 5
Gate Drive Output
Same as pin 4
Soft-Start Duration Set Same as pin 3
Input
20
21
22
VO2
SNS2
VS2
Output Voltage 2
Same as pin 2
Same as pin 1
Current Sense Input
Current Sense
Reference
Voltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.
23
UV2
EN2
Undervoltage Monitor
Input
This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted.
24
25
Enable
This is an active low input. When asserted (pulled low), the SS and gate drive are released and the
output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.
OCREF Ref. Current Adj.
Allows adjustment of the reference current through R
and the internal current regulation set
SET
resistor, thus setting the thresholds for CR, OC and WOC.
26
27
EN1
UV1
Enable Input
Same as pin 24
Same as pin 23
Undervoltage Monitor
Input
28
VS1
Current Sense
Reference
Same as pin 22
4
ISL6172
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Notes 1, 4)
5x5 QFN Package . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
VBIAS/VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V
ENx, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,
θ
(°C/W)
42
θ
(°C/W)
JA
JC
12.5
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .1kV
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . .75V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . . 1.5kV
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . .+2.25V to +3.63V
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 2.5V to +3.3V, T = T = 0°C - 85°C, Unless Otherwise Specified.
DD
A
J
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
25
MAX
UNIT
CURRENT REGULATION CONTROL
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
CT Threshold Voltage
V
RISET = 1.25K 1%, I
= 20µA
20
-20
30
+20
55
mV
%
CRVTH_1
SET
SET
SET
SET
V
R
RISET = 1.25K 1%, I
RISET = 2.50K 1%, I
RISET = 2.50K 1%, I
= 20µA
= 20µA
= 20µA
CRVTH_1
V
45
50
mV
%
CRVTH_2
V
R
-10
+10
1.200
CRVTH_2
V
1.156
1.178
10
V
CT_Vth
CT Charging Current
I
µA
CT
GATE DRIVE
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
3
ns
GATE Response Time from WOC (Loaded)
pd_woc_load
pd_cr_load
GATE = 1nF
80
4
ns
GATE Response Time in Current Regulation
mode (Loaded)
GATE = 1nF
120% Load Current
ms
GATE Response Time in “Quick-Slew” pull-
down Mode (Loaded)
pd_oc_load
IGATE
GATE = 1nF
50
µs
22mV of overdrive on Amplifier
Input
GATE Turn-On Current
GATE = 2V
14
18.5
22
µA
VV = 2V
S
SNS
V
= 2.1V
Current Limit Amplifier Transconductance
Gm
VV - V
1 = -25mV
SNS
0.35
25
ms
S
GATE Pull Down Resistor (WOC, fault or off
conditions)
Ig_woc
T = 25°C
J
18
9
42
13
Ω
Gate = 2V
GATE Pull Down Resistor (“Quick-Slew”
mode)
Ig_qs
T = 25°C
J
11
kΩ
Gate = 2V
5
ISL6172
Electrical Specifications
PARAMETER
V
= 2.5V to +3.3V, T = T = 0°C - 85°C, Unless Otherwise Specified. (Continued)
DD
A
J
SYMBOL
TEST CONDITIONS
MIN
TYP
9.3
8
MAX
UNIT
V
GATE Voltage
V
Bias = 2.5V (see graph on page 7)
8.8
9.7
GATE
2.1 < Bias < 2.5
V
(see graph on page 7)
BIAS
Supply Current
POR Rising Threshold
POR Falling Threshold
POR Threshold Hysteresis
I/O
I
V
= 3.3V
5
10
2.1
2.0
mA
V
BIAS
BIAS
VIN_POR_L2H
VIN_POR_H2L
VIN_POR_HYS
V
10
mV
Undervoltage Comparator Falling Threshold
Undervoltage Comparator Hysteresis
EN Rising Threshold
EN Falling Threshold
EN Hysteresis
V
V
620
11
635
16
650
21
mV
mV
V
UV_VTHF
UV_HYST
PWR_Vth_R
PWR_Vth_F
PWR_HYST
V
V
V
= 2.5V
= 2.5V
= 2.5V
1.60
0.97
600
1.95
1.10
850
2.25
1.30
1100
0.4
BIAS
BIAS
BIAS
V
mV
V
PG Pull-Down Voltage
FLT Pull-Down Voltage (Note 3)
Soft-Start Charging Current
CHARGE PUMP
I
I
= 8mA
0.047
0.047
VOL_PG
PG
= 8mA
0.4
V
VOL_FLT
IQ_SS
FLT
VSS = 1V
10
µA
CPVDD
V_CPVDD
V_CPVDD
V_CPVDD
V
V
V
= 2.0V
= 3.3V
= 3.3V
3.6
4.9
3.8
5.2
5.0
4.0
5.5
V
V
V
BIAS
BIAS
BIAS
CPVDD
CPVDD
T = 25°C
External User Load = 6mA
Typical Performance Curves (at 25°C unless otherwise specified)
6
5
4
3
2
1
0
2.010
2.005
2.000
1.995
1.990
1.985
1.980
CPQ = 22nF, CPVDD = 0.1µF
2.8 3.2 3.7
V_BIAS (V)
1.0
1.5
1.8
2.3
0
25
40
TEMPERATURE (°C)
60
85
FIGURE 3. I_BIAS vs V_BIAS
FIGURE 4. POR RISING THRESHOLD vs TEMPERATURE
6
ISL6172
Typical Performance Curves (at 25°C unless otherwise specified) (Continued)
12
10
8
1.952
1.950
1.948
1.946
1.944
6
4
2
0
1.942
1.940
CPQ = 22nF, CPVDD = 0.1µF
1.8
2
2.2
2.4
2.8
3.2
3.6
4
4.5
0
25
40
60
85
V_BIAS (V)
TEMPERATURE (°C)
FIGURE 5. V
GATE
vs V_BIAS
FIGURE 6. POR FALLING THRESHOLD vs TEMPERATURE
19.2
19.0
18.8
18.6
18.4
18.2
17.8
17.6
17.4
0.25
I
= 8mA
PG
0.20
0.15
0.10
0.05
0.00
0
25
40
TEMPERATURE (°C)
60
85
0
25
40
60
85
TEMPERATURE (°C)
FIGURE 7. GATE DRIVE vs TEMPERATURE
FIGURE 8. PG_VOL vs TEMPERATURE
10000
1000
10000
1000
(I
SET
= 20µA, R
*I
= 22mV)
SET SET
100
100
10
1
10
1
26
29
31
35
40
IO*R
44
(mV)
56
68
77
84
0.01
1
3
5
(nF)
10
15
20
C
SNS
G
FIGURE 9. WOC RESPONSE vs LOAD CAPACITANCE
FIGURE 10. RESPONSE TIME vs I *R
SNS
O
7
ISL6172
Typical Performance Curves (at 25°C unless otherwise specified) (Continued)
24.0
23.5
23.0
22.5
22.0
0
25
40
60
85
TEMPERATURE (°C)
FIGURE 11. WOC PULLDOWN vs TEMPERATURE
FIGURE 12. SS LIMITED START-UP - SS CAP 0.033µF IN
PLACE
CH1: V 2, CH3: I
O
IN
FIGURE 13. CURRENT LIMITED START-UP: SS CAP REMOVED, I
SET
CR
CR
TO 2.2A. NOTE MAX INRUSH CURRENT REMAINS AT I
SET LEVEL (2.2A).
Figures 12 and 13 are actual scope shots under different circuit configurations that are possible with this IC. Figure 13 shows that the
part is capable of limiting the inrush current to the value set by the current regulation amplifier in absence of or very small sized SS
caps. Figure 13 is for the normal circuit shown on the front page.
8
ISL6172
1. Current Limit or Current Regulation (CR) Mode: When
Detailed Description of Operation
the load current reaches the current regulation threshold, the
current amplifier loop closes and the circuit behaves like a
current source. The current regulation threshold is set by
ISL6172 targets dual voltage hot-swap applications with a
bias of 2.1V to 3.6VDC and the voltages being controlled
down to 0.7VDC. The IC’s main function is to limit and
regulate the inrush current into the loads. This is achieved by
enhancing an external MOSFET in a controlled manner. In
order to fully enhance the MOSFET, the IC must provide
adequate gate to source voltage, which is typically 5V or
greater. Hence, the final steady-state voltage on Gate (GT)
pin must be 5V above the load voltage. Two internal charge-
pumps allow this to happen.
setting a reference current, I
, through R
by selecting
an appropriate resistor between OCREF and GND, which
SET
SET
sets I
. The relationship between I
and I
is I
=
REF
REF
= Vocref/Rocref = 1.178/Rocref. I
SET
REF
REF
4*I
, where I
SET
REF
would typically be set at 80µA.
Selecting appropriate values for R
and R
such that
(EQ. 1)
SET
SNS
when I = I
,
O
CR
VIN
VO
Io*R
= I
*R
SNS
SET SET
Q
Vin
Vo
-
+
+
Rsns
Q
Rset
Iset
CURRENT REGULATION
MODE:
Iset*Rset = Io*Rsns
-
VIN
10V
0
20µA
CPVDD
SOFT-
START
CPVDD
10µA
AMPLIFIER
CURRENT
LIMIT
10V
ISL6172
0
SS1
-
30µA
AMPLIFIER
+
20µA
(OTA)
+
-
+
-
3K
FIGURE 14. SOFT-START OPERATION
“QUICK SLEW”
10K
+
-
Iref
4
Controlled Soft-Start
Vqs
The output voltages are monitored through the Vo pins and
slew up at a rate determined by the capacitors on the Soft-
start (SS) pin, as illustrated in Figure 14. 20µA of gate
charge current is available. The soft-start amplifier controls
the output voltage by robbing some of the gate charge
current thus slowing down the MOSFET enhancement.
When the load voltage reaches its set level, as sensed by its
respective UV pin through an external resistor divider, the
Power Good (PG) output goes active, signaling that the
output voltage has reached its set limit.
Vqs =1.2*Iset*Rset
FIGURE 15. CURRENT REGULATION AND QUICK-SLEW
OPERATION
The operating mode is shown in Figure 15 (please ignore the
portion shown in dotted line for now). When the circuit enters
this mode, increased voltage drop across the MOSFET is
sensed by the OC comparator, which sets off the timer. CT
begins to charge from an internal 10µA current source. The
amount of time it takes for this cap to charge to 1.178V sets
up the current regulation duration and upon expiration of
which the MOSFET gate is pulled down by 80mA current sink
unless the load current level drops back to a level below the
current regulation threshold level prior to that. In that case, the
current regulation mode is no longer active, the MOSFET is
Current Monitoring and Protection
The IC monitors the load current (Io) by sensing the voltage-
drop across the low value current sense resistor (R
),
SNS
which is connected in series with the MOSFET mentioned
earlier and shown in the diagram on page 2, through Sense
(SNS) and voltage set (VS) pins. The latter is through a
allowed to fully enhance and the IC discharges the C Cap. If
resistor, R
, as shown. Three levels of overcurrent
T
SET
RTR/LTCH pin is left open or pulled to BIAS, the output
remains latched off after the expiration of the time-out period
detection are available to protect against all possible fault
scenarios. These levels are:
determined by C . If RTR/LTCH pin is pulled to GND, the IC
T
1. Current Limit or Current Regulation (CR)
2. “Quick Slew” Mode
3. Way Overcurrent (WOC)
automatically retries to turn on the MOSFET after a wait
period, during which C is charged and discharged 64 times
T
and the retry attempt takes place on the 65th time. This wait
period allows the MOSFET junction to cool down.
Each of these modes is described in detail as follows:
9
ISL6172
2. “Quick Slew” Mode: This mode comes into effect when
the di/dt of the load is too fast for the current regulation to
see and is 20% or more above the current regulation limit. It
shares the same circuit block as the current regulation
amplifier in the block diagram. The purpose of having this
mode is to ensure the current does not go too high for too
long. While in this mode, the gate of the MOSFET is allowed
to be pulled down passively with an internal resistor of
approximately 10K. Once the current level reaches the
current regulation set level, the current regulation amplifier
takes over.
The voltage on OCREF pin is the same as the internal band-
gap reference voltage, which is 1.178V (nominal). A resistor
to GND from this pin sets the reference current (and hence
reference voltage) for the current limit amplifier and
OC/WOC comparators. The current regulation (CR) duration
is set by the capacitor on CT pin to GND. Once the voltage
on this pin reaches 1.178V, the CR duration expires. Fault
(FLT) pin goes active (pulls low), signaling the load of a fault
condition and the gate (GT) pin gets pulled low.
Retry vs Latched Fault Operational Modes:
RTR/LTCH pin dictates the IC behavior after the gate (GT)
pin pulls down following a current regulation or OC or WOC
condition. If the RTR/LTCH pin is left floating, the gate pin
will remain latched off. It can only be released by de-
asserting and reasserting the enable (EN) input. If
RTR/LTCH pin is pulled to GND, then the Retry mode will be
activated. In this mode the IC will automatically attempt to
turn-on the MOSFET after a delay, determined by the
capacitor on CT pin. In the Retry mode, the internal logic
charges and discharges the CT cap 64 times during “wait”
period. On the 65th time, retry takes place. If the fault is
cleared, the normal power up will continue and fault will
clear. If not, the IC will continue to retry indefinitely.
3. Way Overcurrent (WOC) Mode: This mode is designed
to handle hard shorts on the load side, which can result in
very high di/dt. Typically, the current limit set for this mode is
300% of the current regulation limit. This mode uses a very
fast comparator, which directly looks at the voltage drop
across R
and pulls the gate very quickly to GND (as
SNS
shown in Figure 16) and immediately releases it. If the WOC
is still present, the IC enters current regulation mode and the
rest of the current regulation behavior follows as described
earlier under current regulation mode.
Io
Vo
Vin
-
+
Q
+
Rsns
Bias and Charge Pump Voltages:
Iset Rset
-
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on CPVDD pin. The
voltage on CPVDD pin is approximately 5V. It also provides
power to the POR and band-gap circuitry as shown in the
block diagram. A capacitor connected externally across
CPQ+ and CPQ- pins of the IC is the “flying” cap for the
charge-pump.
GATE
PULLDOWN
CURRENT
ISL6172
WOC
COMPARATOR
3K
-
The second charge-pump is used exclusively to drive the
gates of the MOSFETs through the 20µA current sources,
one for each channel. The output of this charge pump is
approximately 10V as shown in the block diagram.
+
25Ω
FIGURE 16. WOC OPERATION
Additionally, as shown in the block diagram, there is also an
“OC comparator”, which looks at the combined MOSFET
and Rsense voltage drop. When the MOSFET drop exceeds
the R
drop by 60mV, timeout circuit starts ticking and
SNS
CTx is allowed to charge. If the 60mV drop remains in effect
until after the time-out period expires (CTx voltage
exceeding 1.178V), the gate of the MOSFET is pulled down,
SSx capacitor is discharged, FLT is asserted and a new SS
sequence is allowed to begin after ENx recycle or by
keeping the RTR/LTCH pin pulled low.
10
ISL6172
TYPICAL HOT-PLUG POWER UP SEQUENCE
Tracking
1. When power is applied to the IC on BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled low (below it’s specified threshold),
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the Soft-start amplifier shown in the block diagram.
5. CTx cap begins to charge at the same time as the
corresponding SS cap.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise
CH1: V 1, CH2: V 2, T = 2ms/DIV, C = 0.066µF
SS
O
O
7. If the output voltage reaches its full value before the
corresponding CTx cap voltage reaches 1.178V, the
latter gets discharged and the FLT remains deasserted.
Else, the channel shuts down and FLT is asserted.
FIGURE 17. TRACKING MODE WAVEFORMS
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 17 above. If one channel goes down for any
reason, the other one will too. One important thing to note
here is that only the overcurrent latch-off mode will work.
Autoretry feature WILL NOT work. Retry must be controlled
manually through EN.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, Power Good (PG) output goes active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or CT timer is not timed out. The latter indicates
expiration of current regulation duration.
State Diagram
This is shown in Figure 18. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
11
ISL6172
IC Operation State Diagram
No
Power
Apply Power
Bias>1V
PG
&
FLT
Outputs
Valid
Bias>2V
EN De-asserted
FLT
Cleared
EN Asserted
Count 64
Pulses
&
Io>ICR
Soft Start
(Tss)
OC
Reset
Comp
Quick
Trip
Slew/CR
State
Valid
RTR/LTCH = L
Output
Voltage
Vout>(Vin-100mV)
AND
TSS>TCT
Available
Reset &
Latch
Off
Vout<(Vin-100mV)
t *<TcT
AND
Run
OC Timer
State
t *>TcT
State
FLT
RTR/LTCH = H
Vuv<633mV
Vuv>645mV
Asserted
State
Io>ICR
AND
PG
Asserted
IO<WOC
Io>ICR
* “t” is either equal to Tss or the
time for which the current
remains at ICR or greater level,
whichever is applicable
Io>>ICR
(WOC)
Gate
Pulldown
FIGURE 18.
12
ISL6172
Charge Pump Capacitor Selection (C and C )
Applications Information
Selection of External Components
Typical application circuit of Figure 2 has been used for this
section, which provides guidelines to select the external
component values.
P
V
C
is the “flying cap” and C is the smoothing cap of the
V
P
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on C value and its ESR, Charge-
P
pump switch resistance, frequency and ESR of the
smoothing cap, C . The output resistance can be
V
MOSFET (Q1)
This component should be selected on the basis of its
approximately calculated using the following equation:
r
specification at the expected Vgs (gate to source
R
= R
+ 4*ESR +ESR + [1/(f*C )]
INT P
C C
DS(ON)
voltage). One needs to ensure that the combined voltage
drop across the Rsense and r at the desired
OUT
Where,
P
V
DS(ON)
maximum current (including transients) will still keep the
output voltage above the minimum required level. Power
dissipation in the device under short circuit condition should
also be an important consideration especially in auto-retry
mode (RTR/LTCH pin pulled low). Using ISL6172 in latched
off mode results in lower power dissipation in the MOSFET.
R
R
= Output Resistance
OUT
= Combined Internal Resistance (25Ω)
INT
ESR
= ESR of C
= ESR of C
C
C
P
P
ESR
V
V
f = 450kHz
Current Sense Resistor (R
)
SNS
It is recommended that C be kept within 0.022µF
P
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the current regulation amplifier. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
(minimum) to 0.1µF (maximum) range. Only ceramic cap is
recommended. Use 0.1µF cap if CPVDD output is expected
to power an external circuit, in which case the current draw
from CPVDD must be kept below 10mA.
C
should at least be 0.47µF (ceramic only). Higher values
V
may be used if low ripple performance is desired.
current indefinitely. Hence, the power rating of this resistor
2
Time-out Capacitor Selection (C )
T
must be greater than I
*R
.
O(MAX)
SNS
This capacitor controls the time-out period. As shown in
Figure 2, when the voltage across this capacitor exceeds
1.178V, the time-out comparator detects it and pulls down
the gate voltage thus shutting down the channel. An internal
10µA current source charges this capacitor. Hence, the
value of this capacitor is determined by the following
equation:
Current Set Resistor (R
SET)
This resistor directly sets the threshold for the current
regulation amplifier and indirectly sets the same for the OC
and WOC comparators in conjunction with R
. Once
SNS
R
has been selected, use Equation 1 to calculate R
.
SET
SNS
Use 20µA for I
in a typical application.
SET
Reference Current Set Resistor (R
)
REF
This resistor sets up the current in the internal current
source, I /4, shown in Figure 2 for the comparators. The
C = (10µA * T
)/1.178
OUT
T
Where,
REF
voltage at the OCREF pin is the same as the internal
T
= Desired time-out period.
OUT
bandgap reference. The current (I
resistor is simply:
) flowing through this
REF
IMPORTANT NOTE: Selection of C and C should be such that
SS
T
the soft-start period is always shorter than the time-out period.
Otherwise the output will remain shut down.
I
= 1.178/R
REF
REF
Soft-Start Capacitor Selection (C
)
SS
This current, I
, should be set at 80µA to force 20µA in the
REF
The rate of change of voltage (dv/dt) on this cap, which is
determined by the internal 10µA current source, is the same
as that on the output cap. Hence, the value of this capacitor
directly controls the inrush current amplitude during hot
swap operation.
internal current source as shown in Figure 2, because of the
4:1 current mirror.
Selection of Rs1 and Rs2
These resistors should be selected based on where the user
wants to set the UV detect point. The UV comparator detects
the undervoltage condition when it sees the voltage at UV
pin drop below 0.633V. The resistor divider values should be
selected accordingly.
C
= C *(10µA/I )
INRUSH
SS
Where,
O
C
= Load Capacitance
O
I
= Desired Inrush Current
INRUSH
13
ISL6172
I
is the sum of the dc steady-state load current and
There are two input voltages, one for each channel plus
INRUSH
the load capacitance charging current. If the dc steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
there is optional “+5V” input. The latter is to test the pull-up
capability of FLT and PG outputs to +5V. The loop jumpers
are there to facilitate current measurement using an
oscilloscope current probe.
I
.
INRUSH
Pins SS1 and SS2 of the IC are available on header J2 as
test points so that they can be tied together to achieve
tracking between Vo1 and Vo2.
ISL6172 Evaluation Platform
The ISL6172EVAL3 is the primary evaluation board for this
family. The board is a standalone evaluation platform and it
only needs input bias and test voltages.
Each channel is preloaded with capacitive and resistive
loads. Extra load can be externally applied if necessary.
The outputs are brought out to banana sockets to allow
external loading if desired.
The evaluation board has been designed with a typical
application and accessibility to all the features in mind to
enable a user to understand and verify these features of the
IC. The circuit is designed for 2A for each input rail but it can
easily be scaled up or down by adjusting some component
values. LED indicators are provided to indicate Fault and/or
Power Good status. The switches are there to perform
Enable function for each channel and to select autoretry or
latchoff mode.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
ISL6172
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE C)
2X
0.15
C A
MILLIMETERS
D
A
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
9
D/2
A
A1
A2
A3
b
0.80
0.90
-
D1
-
-
-
-
D1/2
2X
-
9
N
0.15 C
B
6
0.20 REF
9
INDEX
AREA
1
2
3
E1/2
E/2
9
0.18
2.95
2.95
0.23
0.30
3.25
3.25
5,8
D
5.00 BSC
-
E1
E
B
D1
D2
E
4.75 BSC
9
3.10
7,8
2X
0.15 C
B
5.00 BSC
-
2X
TOP VIEW
E1
E2
e
4.75 BSC
9
0.15 C A
3.10
7,8
0
A2
4X
0.50 BSC
-
A
/ /
0.10 C
0.08 C
C
k
0.25
0.50
-
-
-
-
L
0.60
0.75
0.15
8
SEATING PLANE
A1
A3
SIDE VIEW
9
L1
N
-
28
7
7
-
10
2
5
NX b
0.10 M C A B
Nd
Ne
P
3
4X P
D2
D2
8
7
8
-
3
NX k
(DATUM B)
0.60
12
9
2
N
θ
-
-
9
4X P
1
Rev. 0 02/03
(DATUM A)
2
3
NOTES:
(Ne-1)Xe
REF.
E2
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
7
8
E2/2
NX L
8
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
N
e
9
(Nd-1)Xe
REF.
CORNER
OPTION 4X
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
L
L
10
10
L1
L1
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
15
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