ISL6323IRZ_技术文档

ISL6323

®

Hybrid SVI/PVI

Data Sheet

April 7, 2008

FN9278.2

Monolithic Dual PWM Hybrid Controller

Powering AMD SVI Split-Plane and PVI

Uniplane Processors

Features

• Processor Core Voltage Via Integrated Multi-Phase

Power Conversion

The ISL6323 dual PWM controller delivers high efficiency

and tight regulation from two synchronous buck DC/DC

converters. The ISL6323 supports hybrid power control of

AMD processors which operate from either a 6-bit parallel

VID interface (PVI) or a serial VID interface (SVI). The dual

output ISL6323 features a multi-phase controller to support

uniplane VDD core voltage and a single phase controller to

power the Northbridge (VDDNB) in SVI mode. Only the

multi-phase controller is active in PVI mode to support

uniplane VDD only processors.

• Configuration Flexibility

- 2-Phase Operation with Internal Drivers

- 3- or 4-Phase Operation with External PWM Drivers

• Serial VID Interface Inputs

- Two Wire, Clock and Data, Bus

- Conforms to AMD SVI Specifications

• Parallel VID Interface Inputs

- 6-bit VID input

- 0.775V to 1.55V in 25mV Steps

- 0.375V to 0.7625V in 12.5mV Steps

A precision uniplane core voltage regulation system is

provided by a two-to-four-phase PWM voltage regulator (VR)

controller. The integration of two power MOSFET drivers,

adding flexibility in layout, reduce the number of external

components in the multi-phase section. A single phase PWM

controller with integrated driver provides a second precision

voltage regulation system for the North Bridge portion of the

processor. This monolithic, dual controller with integrated

driver solution provides a cost and space saving power

management solution.

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

- Adjustable Reference-Voltage Offset

• Optimal Processor Core Voltage Transient Response

- Adaptive Phase Alignment (APA)

- Active Pulse Positioning Modulation

• Fully Differential, Continuous DCR Current Sensing

- Accurate Load Line Programming

For applications which benefit from load line programming to

reduce bulk output capacitors, the ISL6323 features output

voltage droop. The multi-phase portion also includes

advanced control loop features for optimal transient response

to load application and removal. One of these features is

highly accurate, fully differential, continuous DCR current

sensing for load line programming and channel current

balance. Dual edge modulation is another unique feature,

allowing for quicker initial response to high di/dt load

transients.

- Precision Channel Current Balancing

• Variable Gate Drive Bias: 5V to 12V

• Overcurrent Protection

• Multi-tiered Overvoltage Protection

• Selectable Switching Frequency up to 1MHz

• Simultaneous Digital Soft-Start of Both Outputs

• Processor NorthBridge Voltage Via Single Phase

Power Conversion

Ordering Information

• Precision Voltage Regulation

PART

NUMBER

(Note)

PART

MARKING

TEMP.

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over-Temperature

ISL6323CRZ* ISL6323 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7

ISL6323IRZ* ISL6323 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7

• Serial VID Interface Inputs

- Two Wire, Clock and Data, Bus

- Conforms to AMD SVI Specifications

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

• Overcurrent Protection

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach

materials and 100% matte tin plate PLUS ANNEAL - e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

• Continuous DCR Current Sensing

• Variable Gate Drive Bias: 5V to 12V

• Simultaneous Digital Soft-Start of Both Outputs

• Selectable Switching Frequency up to 1MHz

• Pb-Free (RoHS Compliant)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6323

Pinout

ISL6323

(48 LD QFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

FB_NB

ISEN_NB+

RGND_NB

VID0/VFIXEN

VID1/SEL

VID2/SVD

VID3/SVC

VID4

PWM4

1

2

36

35

34

33

32

31

30

29

28

27

26

25

PWM3

PWROK

PHASE1

UGATE1

BOOT1

LGATE1

PVCC1_2

LGATE2

BOOT2

UGATE2

PHASE2

3

4

5

6

49

GND

7

8

9

VID5

10

11

12

VCC

FS

RGND

13 14 15 16 17 18 19 20 21 22 23 24

Integrated Driver Block Diagram

PVCC

BOOT

UGATE

PHASE

PWM

20kΩ

SHOOT-

THROUGH

PROTECTION

SOFT-START

AND

GATE

CONTROL

LOGIC

FAULT LOGIC

10kΩ

LGATE

FN9278.2

April 7, 2008

2

ISL6323

Controller Block Diagram

RGND_NB

FB_NB

COMP_NB

NB_REF

∑

BOOT_NB

E/A

UGATE_NB

MOSFET

DRIVER

UV

LOGIC

OV

LOGIC

ISEN_NB+

ISEN_NB-

CURRENT

SENSE

PHASE_NB

LGATE_NB

RAMP

VDDPWRGD

APA

EN_12V

PVCC_NB

EN

APA

NB

FAULT

LOGIC

ENABLE

LOGIC

COMP

OFS

VCC

POWER-ON

RESET

OFFSET

PVCC1_2

SOFT-START

AND

FB

FAULT LOGIC

E/A

DVC

2X

BOOT1

∑

RGND

DROOP

CONTROL

UGATE1

MOSFET

DRIVER

LOAD APPLY

TRANSIENT

ENHANCEMENT

PHASE1

LGATE1

PWROK

VID0/VFIXEN

VID1/SEL

VID2/SVD

VID3/SVC

VID4

SVI

SLAVE

BUS

AND

PVI

CLOCK AND

TRIANGLE WAVE

GENERATOR

FS

DAC

VID5

PWM1

∑

NB_REF

BOOT2

OV

LOGIC

PWM2

PWM3

PWM4

UGATE2

MOSFET

DRIVER

∑

VSEN

RSET

PHASE2

LGATE2

UV

LOGIC

∑

OC

RESISTOR

MATCHING

PH3/PH4

POR

∑

I_TRIP

I_AVG

ISEN1+

ISEN1-

CH1

CURRENT

SENSE

EN_12V

CHANNEL

DETECT

ISEN3-

ISEN4-

ISEN2+

ISEN2-

CH2

CURRENT

SENSE

CHANNEL

CURRENT

BALANCE

I_AVG

1

N

PWM3

ISEN3+

ISEN3-

CH3

PWM3

PWM4

SIGNAL

LOGIC

CURRENT

SENSE

ISEN3-

∑

ISEN4+

ISEN4-

CH4

CURRENT

SENSE

PWM4

SIGNAL

LOGIC

ISEN4-

GND

FN9278.2

April 7, 2008

3

ISL6323

Typical Application - SVI Mode

+12V

FB

VSEN

COMP

ISEN3+

ISEN3-

PWM3

BOOT1

UGATE1

PHASE1

UGATE1

PHASE1

LGATE1

PWM1

PGND

APA

DVC

ISEN1-

ISEN1+

+5V

+12V

ISL6614

+12V

VDD

+12V

PVCC1_2

VCC

PVCC

VCC

BOOT2

OFS

UGATE2

GND

UGATE2

PHASE2

FS

CPU

LOAD

PHASE2

LGATE2

PWM2

LGATE2

RSET

VFIXEN

SEL

SVD

ISEN2-

ISEN2+

SVC

VID4

RGND

NC

VID5

PWROK

ISEN4+

ISEN4-

VDDPWRGD

GND

PWM4

+12V

ISL6323

+12V

PVCC_NB

EN

OFF

ON

BOOT_NB

UGATE_NB

PHASE_NB

VDDNB

LGATE_NB

ISEN_NB-

NB

LOAD

COMP_NB

ISEN_NB+

RGND_NB

FB_NB

FN9278.2

April 7, 2008

4

ISL6323

Typical Application - PVI Mode

+12V

FB

VSEN

COMP

ISEN3+

ISEN3-

PWM3

BOOT1

UGATE1

PHASE1

BOOT1

UGATE1

PHASE1

LGATE1

PWM1

APA

DVC

PGND

ISEN1-

ISEN1+

+5V

+12V

ISL6614

+12V

VDD

+12V

PVCC1_2

VCC

PVCC

BOOT2

VCC

BOOT2

GND

OFS

UGATE2

PHASE2

FS

CPU

LOAD

PHASE2

LGATE2

PWM2

LGATE2

RSET

VID0

VID1/SEL

VID2

ISEN2-

ISEN2+

VID3

VID4

RGND

VID5

NC

PWROK

ISEN4+

ISEN4-

VDDPWRGD

GND

PWM4

ISL6323

+12V

NORTH BRIDGE REGULATOR

DISABLED IN PVI MODE

PVCC_NB

EN

OFF

ON

BOOT_NB

UGATE_NB

PHASE_NB

VDDNB

LGATE_NB

ISEN_NB-

NB

LOAD

COMP_NB

ISEN_NB+

RGND_NB

FB_NB

FN9278.2

April 7, 2008

5

ISL6323

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Thermal Resistance

θ

(°C/W)

30

θ

(°C/W)

2

JA

JC

QFN Package (Notes 1, 2) . . . . . . . . . .

Absolute Boot Voltage (V

Phase Voltage (V

). . . . . . . .GND - 0.3V to GND + 36V

). . . . . . . . GND - 0.3V to 15V (PVCC = 12)

PHASE

BOOT

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT-PHASE

Upper Gate Voltage (V

). . . . V

UGATE

- 0.3V to V

PHASE

BOOT

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

Lower Gate Voltage (V

BOOT

) . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

Recommended Operating Conditions

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification

Human Body Model (Class 2) . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model (Class B) . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

Charged Device Model (Class IV) . . . . . . . . . . . . . . . . . . . . . .1kV

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%

Ambient Temperature (ISL6323CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL6323IRZ) . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. Limits should be considered typical and are not production tested.

Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

BIAS SUPPLIES

Input Bias Supply Current

I

; EN = high

VCC

15

1

22

30

3

mA

V

Gate Drive Bias Current - PVCC1_2 Pin

Gate Drive Bias Current - PVCC_NB Pin

VCC POR (Power-On Reset) Threshold

; EN = high

1.8

PVCC1_2

PVCC_NB

; EN = high

0.3

0.9

2

VCC Rising

VCC Falling

PVCC Rising

PVCC Falling

4.20

3.70

4.20

3.70

4.40

3.90

4.40

3.90

4.55

4.10

4.55

4.10

V

PVCC POR (Power-On Reset) Threshold

V

PWM MODULATOR

Oscillator Frequency Accuracy, f

R

= 100kΩ (±0.1%) to Ground, T = +25°C

225

240

0.08

250

270

275

300

1.0

kHz

SW

T

A

(Droop Enabled)

R

= 100kΩ (±0.1%) to VCC, T = +25°C

T

A

(Droop Disabled)

Typical Adjustment Range of Switching Frequency (Note 3)

MHz

V

Oscillator Ramp Amplitude, V

CONTROL THRESHOLDS

EN Rising Threshold

(Note 3)

1.50

P-P

0.80

70

0.88

130

1.1

0.92

190

V

mV

V

EN Hysteresis

PWROK Input HIGH Threshold

PWROK Input LOW Threshold

0.95

V

VDDPWRGD Sink Current

Open drain, V_VDDPWRGD = 400mV

4

mA

V

PWM Channel Disable Threshold

PIN_ADJUSTABLE OFFSET

V

, V

ISEN3- ISEN4-

4.4

OFS Source Current Accuracy (Positive Offset)

OFS Sink Current Accuracy (Negative Offset)

R

= 10kΩ (±0.1%) from OFS to GND

= 30kΩ (±0.1%) from OFS to VCC

27.5

50.5

31

34.5

56.5

µA

OFS

53.5

OFS

FN9278.2

April 7, 2008

6

ISL6323

Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued)

PARAMETER

REFERENCE AND DAC

TEST CONDITIONS

MIN

TYP

MAX

UNITS

System Accuracy (VDAC > 1.000V)

System Accuracy (0.600V < VDAC < 1.000V)

System Accuracy (VDAC < 0.600V)

DVC Voltage Gain

-0.6

-1.0

-2.0

0.6

1.0

2.0

%

V

VDAC = 1V

2.0

APA Current Tolerance

V

= 1V

90

100

108

µA

APA

ERROR AMPLIFIER

DC Gain

R

C

= 10k to ground, (Note 3)

96

20

dB

MHz

V/µs

V

L

Gain-Bandwidth Product (Note 3)

Slew Rate (Note 3)

= 100pF, R = 10k to ground, (Note 3)

L

= 100pF, Load = ±400µA, (Note 3)

8

Maximum Output Voltage

Minimum Output Voltage

Load = 1mA

Load = -1mA

3.80

2.2

4.20

1.3

1.6

4.0

0.5

V

SOFT-START RAMP

Soft-Start Ramp Rate

3.0

mV/µs

PWM OUTPUTS

PWM Output Voltage LOW Threshold

PWM Output Voltage HIGH Threshold

CURRENT SENSING - CORE CONTROLLER

I

= ±500µA

V

LOAD

4.5

Current Sense Resistance, R

(Note 3)

(Internal)

T

= +25°C

2400

77

Ω

ISEN

A

Average Sensed and Droop Current Tolerance

ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 77µA

68

87

µA

CURRENT SENSING - NB CONTROLLER

Current Sense Resistance, R

(Note 3)

(Internal)

T

= +25°C

2400

80

Ω

ISEN_NB

A

Sensed Current Tolerance

ISEN_NB = 80µA

µA

OVERCURRENT PROTECTION

Overcurrent Trip Level - Average Channel

Overcurrent Trip Level - Individual Channel

Normal Operation

83

100

130

142

190

111

µA

Dynamic VID Change (Note 3)

Normal Operation

Dynamic VID Change (Note 3)

POWER GOOD

Overvoltage Threshold

VSEN Rising (Core and North Bridge)

VSEN Falling (Core)

VDAC

+225mV

VDAC + VDAC +

V

250mV

275mV

Undervoltage Threshold

VDAC -

325mV

VDAC -

300mV

VDAC -

275mV

mV

VSEN Falling (North Bridge)

VDAC -

310mV

VDAC -

275mV

VDAC -

245mV

Power Good Hysteresis

50

OVERVOLTAGE PROTECTION

OVP Trip Level

1.73

350

1.80

400

1.84

V

OVP Lower Gate Release Threshold

mV

SWITCHING TIME (Note 3) [See “Timing Diagram” on page 8]

UGATE Rise Time

t

V

= 12V, 3nF Load, 10% to 90%

26

ns

RUGATE; PVCC

FN9278.2

April 7, 2008

7

ISL6323

Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

18

MAX

UNITS

ns

LGATE Rise Time

UGATE Fall Time

LGATE Fall Time

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

RLGATE; PVCC

V

18

ns

FUGATE; PVCC

V

12

ns

FLGATE; PVCC

UGATE Turn-On Non-overlap

LGATE Turn-On Non-overlap

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

MODE SELECTION

; V

= 12V, 3nF Load, Adaptive

10

ns

PDHUGATE PVCC

; V

10

ns

PDHLGATE PVCC

V

= 12V, 15mA Source Current

2.0

Ω

PVCC

= 12V, 15mA Sink Current

= 12V, 15mA Source Current

= 12V, 15mA Sink Current

1.65

1.25

0.80

VID1/SEL Input Low

EN taken from HI to LO, VDDIO = 1.5V

EN taken from LO to HI, VDDIO = 1.5V

0.45

V

VID1/SEL Input High

1.00

PVI INTERFACE

VIDx Pull-down

VDDIO = 1.5V

30

45

µA

V

VIDx Input Low

0.45

VIDx Input High

V

SVI INTERFACE

SVC, SVD Input LOW (VIL)

SVC, SVD Input HIGH (VIH)

Schmitt Trigger Input Hysteresis

SVD Low Level Output Voltage

Maximum SVC, SVD Leakage (Note 3)

0.4

V

1.10

0.14

0.35

±5

0.55

V

3mA Sink Current

0.285

V

µA

Timing Diagram

t

PDHUGATE

t

RUGATE

FUGATE

UGATE

LGATE

t

FLGATE

RLGATE

t

PDHLGATE

FN9278.2

April 7, 2008

8

ISL6323

depending on the desired MOSFET gate-drive level.

Decouple this pin with a quality 1.0µF ceramic capacitor.

Functional Pin Description

VID1/SEL

PVCC_NB

This pin selects SVI or PVI mode operation based on the state

of the pin prior to enabling the ISL6323. If the pin is LO prior to

enable, the ISL6323 is in SVI mode and the dual purpose pins

[VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode

related functions. If the pin held HI prior to enable, the

ISL6323 is in PVI mode and dual purpose pins use their VIDx

related functions to decode the correct DAC code.

The power supply pin for the internal MOSFET driver for the

Northbridge controller. Connect this pin to any voltage from

+5V to +12V depending on the desired MOSFET gate-drive

level. Decouple this pin with a quality 1.0µF ceramic capacitor.

GND

GND is the bias and reference ground for the IC. The GND

connection for the ISL6323 is through the thermal pad on the

bottom of the package.

VID0/VFIXEN

If VID1 is LO prior to enable [SVI Mode], the pin is functions

as the VFIXEN selection input from the AMD processor for

determining SVI mode versus VFIX mode of operation.

If VID1 is HI prior to enable [PVI Mode], the pin is used as

DAC input VID0. This pin has an internal 30µA pull-down

current applied to it at all times.

EN

This pin is a threshold-sensitive (approximately 0.85V) system

enable input for the controller. Held low, this pin disables both

CORE and NB controller operation. Pulled high, the pin

enables both controllers for operation.

VID2/SVD

When the EN pin is pulled high, the ISL6323 will be placed in

either SVI or PVI mode. The mode is determined by the

latched value of VID1 on the rising edge of the EN signal.

If VID1 is LO prior to enable [SVI Mode], this pin is the serial

VID data bi-directional signal to and from the master device on

AMD processor. If VID1 is HI prior to enable [PVI Mode], this

pin is used to decode the programmed DAC code for the

processor. In PVI mode, this pin has an internal 30µA pull-down

current applied to it. There is no pull-down current in SVI mode.

A third function of this pin is to provide driver bias monitor for

external drivers. A resistor divider with the center tap

connected to this pin from the drive bias supply prevents

enabling the controller before insufficient bias is provided to

external driver. The resistors should be selected such that

when the POR-trip point of the external driver is reached, the

voltage at this pin meets the above mentioned threshold level.

VID3/SVC

If VID1 is LO prior to enable [SVI Mode], this pin is the serial

VID clock input from the AMD processor. If VID1 is HI prior to

enable [PVI Mode], the ISL6323 is in PVI mode and this pin is

used to decode the programmed DAC code for the processor.

In PVI mode, this pin has an internal 30µA pull-down current

applied to it. There is no pull-down current in SVI mode.

FS

A resistor, placed from FS to Ground or from FS to VCC,

sets the switching frequency of both controllers. Refer to

Equation 1 for proper resistor calculation.

VID4

[10.61 – 1.035log(f )]

s

This pin is active only when the ISL6323 is in PVI mode.

When VID1 is HI prior to enable, the ISL6323 decodes the

programmed DAC voltage required by the AMD processor.

This pin has an internal 30µA pull-down current applied to it at

all times.

(EQ. 1)

R

= 10

T

With the resistor tied from FS to Ground, Droop is enabled.

With the resistor tied from FS to VCC, Droop is disabled.

VSEN and RGND

VID5

VSEN and RGND are inputs to the core voltage regulator

(VR) controller precision differential remote-sense amplifier

and should be connected to the sense pins of the remote

processor core(s), VDDFB[H,L].

This pin is active only when the ISL6323 is in PVI mode.

When VID1 is HI prior to enable, the ISL6323 decodes the

programmed DAC voltage required by the AMD processor.

This pin has an internal 30µA pull-down current applied to it at

all times.

FB and COMP

These pins are the internal error amplifier inverting input and

output respectively of the core VR controller. FB, VSEN and

COMP are tied together through external RC networks to

compensate the regulator.

VCC

VCC is the bias supply for the ICs small-signal circuitry.

Connect this pin to a +5V supply and decouple using a

quality 0.1µF ceramic capacitor.

APA

PVCC1_2

Adaptive Phase Alignment (APA) pin for setting trip level and

adjusting time constant. A 100µA current flows into the APA

pin and by tying a resistor from this pin to COMP the trip

level for the Adaptive Phase Alignment circuitry can be set.

The power supply pin for the multi-phase internal MOSFET

drivers. Connect this pin to any voltage from +5V to +12V

FN9278.2

April 7, 2008

9

ISL6323

than 20kΩ and no more than 80kΩ. A 0.1µF capacitor

should be placed in parallel to the R resistor.

OFS

SET

The OFS pin provides a means to program a DC current for

generating an offset voltage across the resistor between FB

and VSEN The offset current is generated via an external

resistor and precision internal voltage references. The polarity

of the offset is selected by connecting the resistor to GND or

VCC. For no offset, the OFS pin should be left unconnected.

VDDPWRGD

During normal operation this pin indicates whether both output

voltages are within specified overvoltage and undervoltage

limits. If either output voltage exceeds these limits or a reset

event occurs (such as an overcurrent event), the pin is pulled

low. This pin is always low prior to the end of soft-start.

ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,

ISEN4-, and ISEN4+

RGND_NB

These pins are used for differentially sensing the corresponding

channel output currents. The sensed currents are used for

channel balancing, protection, and core load line regulation.

This pin is an input to the NB VR controller precision

differential remote-sense amplifier and should be connected

to the sense pin of the North Bridge, VDDNBFBL.

Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node

between the RC sense elements surrounding the inductor of

their respective channel. Tie the ISEN+ pins to the VCORE

side of their corresponding channel’s sense capacitor.

DVC

The DVC pin is a buffered version of the reference to the error

amplifier. A series resistor and capacitor between the DVC pin

and FB pin smooth the voltage transition during VID-on-the-fly

operations.

UGATE1 and UGATE2

Connect these pins to the corresponding upper MOSFET

gates. These pins are used to control the upper MOSFETs

and are monitored for shoot-through prevention purposes.

Maximum individual channel duty cycle is limited to 93.3%.

FB_NB and COMP_NB

These pins are the internal error amplifier inverting input and

output respectively of the NB VR controller. FB_NB,

VDIFF_NB, and COMP_NB are tied together through

external RC networks to compensate the regulator.

BOOT1 and BOOT2

These pins provide the bias voltage for the corresponding

upper MOSFET drives. Connect these pins to appropriately

chosen external bootstrap capacitors. Internal bootstrap

diodes connected to the PVCC1_2 pin provide the

necessary bootstrap charge.

ISEN_NB-, ISEN_NB+

These pins are used for differentially sensing the North

Bridge output current. The sensed current is used for

protection and load line regulation if droop is enabled.

Connect ISEN_NB- to the node between the RC sense

element surrounding the inductor. Tie the ISEN_NB+ pin to

the VNB side of the sense capacitor.

PHASE1 and PHASE2

Connect these pins to the sources of the corresponding

upper MOSFETs. These pins are the return path for the

upper MOSFET drives.

UGATE_NB

Connect this pin to the corresponding upper MOSFET gate.

This pin provides the PWM-controlled gate drive for the

upper MOSFET and is monitored for shoot-through

prevention purposes.

LGATE1 and LGATE2

These pins are used to control the lower MOSFETs. Connect

these pins to the corresponding lower MOSFETs’ gates.

PWM3 and PWM4

BOOT_NB

Pulse-width modulation outputs. Connect these pins to the

PWM input pins of an Intersil driver IC if 3- or 4-phase

operation is desired. Connect the ISEN- pins of the channels

not desired to +5V to disable them and configure the core

VR controller for 2-phase or 3-phase operation.

This pin provides the bias voltage for the corresponding

upper MOSFET drive. Connect this pin to appropriately

chosen external bootstrap capacitor. The internal bootstrap

diode connected to the PVCC_NB pin provides the

necessary bootstrap charge.

PWROK

PHASE_NB

System wide Power Good signal. If this pin is low, the two

SVI bits are decoded to determine the “metal VID”. When the

pin is high, the SVI is actively running its protocol.

Connect this pin to the source of the corresponding upper

MOSFET. This pin is the return path for the upper MOSFET

drive. This pin is used to monitor the voltage drop across the

upper MOSFET for overcurrent protection.

RSET

Connect this pin to the VCC pin through a resistor (R

set the effective value of the internal R

ISEN

) to

current sense

LGATE_NB

SET

Connect this pin to the corresponding MOSFET’s gate. This

pin provides the PWM-controlled gate drive for the lower

MOSFET. This pin is also monitored by the adaptive

resistors. The values of the R

resistor should be no less

SET

FN9278.2

April 7, 2008

10

ISL6323

shoot-through protection circuitry to determine when the

lower MOSFET has turned off.

The output capacitors conduct the ripple component of the

inductor current. In the case of multi-phase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 2 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 3. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

Operation

The ISL6323 utilizes a multi-phase architecture to provide a

low cost, space saving power conversion solution for the

processor core voltage. The controller also implements a

simple single phase architecture to provide the Northbridge

voltage on the same chip.

Multi-phase Power Conversion

Microprocessor load current profiles have changed to the

point that the advantages of multi-phase power conversion

are impossible to ignore. The technical challenges

associated with producing a single-phase converter that is

both cost-effective and thermally viable have forced a

change to the cost-saving approach of multi-phase. The

ISL6323 controller helps simplify implementation by

integrating vital functions and requiring minimal external

components. The “Controller Block Diagram” on page 3

provides a top level view of the multi-phase power

conversion using the ISL6323 controller.

(V – N V

) V

OUT

IN

OUT

(EQ. 3)

I

= -----------------------------------------------------------

C(P – P)

Lf

V

S

IN

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multi-phase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

Interleaving

The converter depicted in Figure 2 delivers 1.5V to a 36A load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS input capacitor current. The single-phase converter

must use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

The switching of each channel in a multi-phase converter is

timed to be symmetrically out-of-phase with each of the other

channels. In a 3-phase converter, each channel switches 1/3

cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has a

combined ripple frequency three times greater than the ripple

frequency of any one phase. In addition, the peak-to-peak

amplitude of the combined inductor currents is reduced in

proportion to the number of phases (Equations 2 and 3).

Increased ripple frequency and lower ripple amplitude mean

that the designer can use less per-channel inductance and

lower total output capacitance for any performance

specification.

Figures 25, 26 and 27 in the section entitled “Input Capacitor

Selection” on page 31 can be used to determine the input

capacitor RMS current based on load current, duty cycle,

and the number of channels. They are provided as aids in

determining the optimal input capacitor solution.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The peak-to-peak current for each phase is

about 7A, and the DC components of the inductor currents

combine to feed the load.

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL1, 7A/DIV

To understand the reduction of ripple current amplitude in the

multi-phase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

PWM1, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

(V – V

) V

OUT

IN

OUT

(EQ. 2)

I

= -----------------------------------------------------

P – P

Lf

V

S

IN

In Equation 2, V and V

IN

are the input and output

OUT

voltages respectively, L is the single-channel inductor value,

and f is the switching frequency.

S

FN9278.2

April 7, 2008

11

ISL6323

To further improve the transient response, ISL6323 also

INPUT-CAPACITOR CURRENT, 10A/DIV

implements Intersil’s proprietary Adaptive Phase Alignment

(APA) technique, which turns on all phases together under

transient events with large step current. With both APP and

APA control, ISL6323 can achieve excellent transient

CHANNEL 3

INPUT CURRENT

10A/DIV

performance and reduce the demand on the output capacitors.

Adaptive Phase Alignment (APA)

To further improve the transient response, the ISL6323 also

implements Intersil’s proprietary Adaptive Phase Alignment

(APA) technique, which turns on all of the channels together

at the same time during large current step transient events.

As Figure 3 shows, the APA circuitry works by monitoring the

voltage on the APA pin and comparing it to a filtered copy of

the voltage on the COMP pin. The voltage on the APA pin is

a copy of the COMP pin voltage that has been negatively

offset. If the APA pin exceeds the filtered COMP pin voltage

an APA event occurs and all of the channels are forced on.

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 1

INPUT CURRENT

10A/DIV

1μs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

Active Pulse Positioning Modulated PWM Operation

ISL6323 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

The ISL6323 uses a proprietary Active Pulse Positioning (APP)

modulation scheme to control the internal PWM signals that

command each channel’s driver to turn their upper and lower

MOSFETs on and off. The time interval in which a PWM signal

can occur is generated by an internal clock, whose cycle time is

the inverse of the switching frequency set by the resistor

between the FS pin and ground. The advantage of Intersil’s

proprietary Active Pulse Positioning (APP) modulator is that the

PWM signal has the ability to turn on at any point during this

PWM time interval, and turn off immediately after the PWM

signal has transitioned high. This is important because it allows

the controller to quickly respond to output voltage drops

associated with current load spikes, while avoiding the ring

back affects associated with other modulation schemes.

APA

-

+

100µA

C

R

APA

V

APA,TRIP

APA

-

TO APA

CIRCUITRY

LOW

PASS

FILTER

COMP

ERROR

AMPLIFIER

FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION

The APA trip level is the amount of DC offset between the

COMP pin and the APA pin. This is the voltage excursion

that the APA and COMP pins must have during a transient

event to activate the Adaptive Phase Alignment circuitry.

The PWM output state is driven by the position of the error

amplifier output signal, V

, minus the current correction

COMP

signal relative to the proprietary modulator ramp waveform as

illustrated in Figure 3. At the beginning of each PWM time

This APA trip level is set through a resistor, R

, that

APA

interval, this modified V

signal is compared to the

COMP

connects from the APA pin to the COMP pin. A 100µA

current flows across R into the APA pin to set the APA

internal modulator waveform. As long as the modified V

COMP

APA

voltage is lower then the modulator waveform voltage, the

PWM signal is commanded low. The internal MOSFET driver

detects the low state of the PWM signal and turns off the

upper MOSFET and turns on the lower synchronous

trip level as described in Equation 4. An APA trip level of

500mV is recommended for most applications. A 0.1µF

capacitor, C

, should also be placed across the R

APA

resistor to help with noise immunity.

MOSFET. When the modified V

voltage crosses the

COMP

–6

(EQ. 4)

V

= R

⋅ 100 × 10

APA

modulator ramp, the PWM output transitions high, turning off

the synchronous MOSFET and turning on the upper

APA, TRIP

PWM Operation

MOSFET. The PWM signal will remain high until the modified

V

voltage crosses the modulator ramp again. When this

The timing of each core channel is set by the number of

active channels. Channel detection on the ISEN3- and

ISEN4- pins selects 2-channel to 4-channel operation for the

ISL6323. The switching cycle is defined as the time between

PWM pulse termination signals of each channel. The cycle

time of the pulse signal is the inverse of the switching

frequency set by the resistor between the FS pin and

COMP

occurs the PWM signal will transition low again.

During each PWM time interval the PWM signal can only

transition high once. Once PWM transitions high it can not

transition high again until the beginning of the next PWM

time interval. This prevents the occurrence of double PWM

pulses occurring during a single period.

FN9278.2

April 7, 2008

12

ISL6323

ground. The PWM signals command the MOSFET driver to

turn on/off the channel MOSFETs.

across the sense capacitor, V , can be shown to be

C

proportional to the channel current I , shown in Equation 6.

Ln

s ⋅ L

⎛

⎝

⎞

-------------

+ 1

For 4-channel operation, the channel firing order is 4-3-2-1:

PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2

output follows another 1/4 of a cycle after PWM3, and

PWM1 delays another 1/4 of a cycle after PWM2. For

3-channel operation, the channel firing order is 3-2-1.

⎠

DCR

-------------------------------------------------------

(EQ. 6)

(EQ. 7)

V

(s) =

⋅ K ⋅ DCR ⋅ I

C

L

n

(R ⋅ R )

⎛

⎜

⎝

⎞

1

2

-----------------------

s ⋅

⋅ C + 1

⎟

R

+ R

2

⎠

1

Where:

R

Connecting ISEN4- to VCC selects three channel operation

and the pulse times are spaced in 1/3 cycle increments. If

ISEN3- is connected to VCC, two channel operation is selected

and the PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.

2

--------------------

K =

R

+ R

1

2

I

V

IN

L

n

UGATE(n)

LGATE(n)

Continuous Current Sampling

L

DCR

V

MOSFET

DRIVER

OUT

In order to realize proper current-balance, the currents in

each channel are sampled continuously every switching

cycle. During this time, the current-sense amplifier uses the

ISEN inputs to reproduce a signal proportional to the

INDUCTOR

C

OUT

-

V (s)

L

-

V

(s)

C

inductor current, I . This sensed current, I

, is simply a

SEN

L

R

1

scaled version of the inductor current.

R

2

ISL6323 INTERNAL CIRCUIT

I

n

PWM

SAMPLE

SWITCHING PERIOD

+

-

ISENn-

-

V

(s)

C

I

L

ISENn+

VCC

R

ISEN

I

SEN

I

RSET

SEN

R

SET

C

SET

TIME

FIGURE 5. INDUCTOR DCR CURRENT SENSING

CONFIGURATION

FIGURE 4. CONTINUOUS CURRENT SAMPLING

The ISL6323 supports Inductor DCR current sensing to

continuously sample each channel’s current for channel-current

balance. The internal circuitry, shown in Figure 6 represents

Channel N of an N-Channel converter. This circuitry is repeated

for each channel in the converter, but may not be active

depending on how many channels are operating.

If the RC network components are selected such that the RC

time constant matches the inductor L/DCR time constant

(see Equation 8), then V is equal to the voltage drop across

C

the DCR multiplied by the ratio of the resistor divider, K. If a

resistor divider is not being used, the value for K is 1.

R

⋅ R

2

L

1

-------------

--------------------

⋅ C

=

(EQ. 8)

DCR

R + R

1 2

Inductor windings have a characteristic distributed

resistance or DCR (Direct Current Resistance). For

simplicity, the inductor DCR is considered as a separate

lumped quantity, as shown in Figure 6. The channel current

The capacitor voltage V , is then replicated across the

C

effective internal sense resistor, R

. This develops a

ISEN

current through R

which is proportional to the inductor

, is continuously sensed and is

SEN

ISEN

current. This current, I

I

, flowing through the inductor, passes through the DCR.

Ln

Equation 5 shows the S-domain equivalent voltage, V ,

L

then used by the controller for load-line regulation, channel-

current balancing, and overcurrent detection and limiting.

Equation 9 shows that the proportion between the channel

across the inductor.

(EQ. 5)

V (s) = I ⋅ (s ⋅ L + DCR)

L

n

current, I , and the sensed current, I

value of the effective sense resistance, R

of the inductor.

, is driven by the

L

SEN

A simple RC network across the inductor (R , R and C)

extracts the DCR voltage, as shown in Figure 6. The voltage

1

2

, and the DCR

ISEN

FN9278.2

April 7, 2008

13

ISL6323

correction for Channel 1 represented. In the figure, the cycle

average current, I , is compared with the Channel 1

DCR

(EQ. 9)

-----------------

I

= I

⋅

SEN

L

R

AVG

sample, I , to create an error signal I

ISEN

.

1

ER

The filtered error signal modifies the pulse width

commanded by V to correct any unbalance and force

The effective internal R

ISEN

resistance is important to the

current sensing process because it sets the gain of the load

line regulation loop when droop is enabled as well as the

gain of the channel-current balance loop and the overcurrent

COMP

toward zero. The same method for error signal

I

ER

correction is applied to each active channel.

trip level. The effective internal R

resistance is user

ISEN

programmable and is set through use of the RSET pin.

Placing a single resistor, R , from the RSET pin to the

VID Interface

SET

VCC pin programs the effective internal R

according to Equation 10.

resistance

The ISL6323 supports hybrid power control of AMD

processors which operate from either a 6-bit parallel VID

interface (PVI) or a serial VID interface (SVI). The VID1/SEL

pin is used to command the ISL6323 into either the PVI

mode or the SVI mode. Whenever the EN pin is held LOW,

both the multi-phase Core and single-phase North Bridge

Regulators are disabled and the ISL6323 is continuously

sampling voltage on the VID1/SEL pin. When the EN pin is

toggled HIGH, the status of the VID1/SEL pin will latch the

ISL6323 into either PVI or SVI mode. This latching occurs on

the rising edge of the EN signal.If the VID1/SEL pin is held

LOW during the latch, the ISL6323 will be placed into SVI

mode. If the VID1/SEL pin is held HIGH during the latch, the

ISL6323 will be placed into PVI mode. For the ISL6323 to

properly enter into either mode, the level on the VID1/SEL

pin must be stable no less that 1µs prior to the EN signal

transitioning from low to high.

ISEN

3

400

---------

R

=

⋅ R

ISEN

SET

(EQ. 10)

The North Bridge regulator samples the load current in the

same manner as the Core regulator does. The R resistor

SET

resistors to the

will program all the effective internal R

same value.

ISEN

Channel-Current Balance

One important benefit of multi-phase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

+

PWM1

V

COMP

TO GATE

CONTROL

LOGIC

6-bit Parallel VID Interface (PVI)

+

-

MODULATOR

RAMP

-

With the ISL6323 in PVI mode, the single-phase North

Bridge regulator is disabled. Only the multi-phase controller

is active in PVI mode to support uniplane VDD only

processors. Table 1 shows the 6-bit parallel VID codes and

the corresponding reference voltage.

WAVEFORM

FILTER f(s)

I

4

3

2

I

ER

I

AVG

Σ

÷ N

I

-

+

TABLE 1. 6-BIT PARALLEL VID CODES

I

VID5

0

VID4

0

VID3

0

VID2

0

VID1

0

VID0

0

VREF

1.5500

1.5250

1.5000

1.4750

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

I

1

NOTE: Channel 3 and 4 are optional.

0

1

0

1

0

FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

0

1

0

1

0

In order to realize the thermal advantage, it is important that

each channel in a multi-phase converter be controlled to

carry about the same amount of current at any load level. To

achieve this, the currents through each channel must be

sampled every switching cycle. The sampled currents, I ,

from each active channel are summed together and divided

by the number of active channels. The resulting cycle

0

1

0

1

0

1

0

1

n

0

1

0

1

0

1

average current, I

, provides a measure of the total load

0

1

0

1

0

AVG

current demand on the converter during each switching

cycle. Channel-current balance is achieved by comparing

the sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current

balance method is illustrated in Figure 6, with error

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FN9278.2

April 7, 2008

14

ISL6323

TABLE 1. 6-BIT PARALLEL VID CODES (Continued)

VID5

0

1

VID4

1

0

1

VID3

0

1

0

1

0

1

VID2

0

1

0

1

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VREF

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

VID5

VID4

VID3

VID2

VID1

VID0

VREF

0.4125

0.4000

0.3875

0.3750

1

0

1

0

1

0

1

Serial VID Interface (SVI)

The on-board Serial VID interface (SVI) circuitry allows the

processor to directly drive the core voltage and Northbridge

voltage reference level within the ISL6323. The SVC and SVD

states are decoded with direction from the PWROK and

VFIXEN inputs as described in the following sections. The

ISL6323 uses a digital to analog converter (DAC) to generate a

reference voltage based on the decoded SVI value. See

Figure 7 for a simple SVI interface timing diagram.

FN9278.2

April 7, 2008

15

ISL6323

1

2

3

4

5

6

7

8

9

10

11

12

VCC

SVC

SVD

ENABLE

PWROK

VDD AND VDDNB

VDDPWRGD

V_SVI

METAL_VID

VFIXEN

FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP

PRE-PWROK METAL VID

The VDD and VDDNB planes will linearly decrease to near

zero.

Typical motherboard start-up occurs with the VFIXEN input

low. The controller decodes the SVC and SVD inputs to

determine the Pre-PWROK metal VID setting. Once the

POR circuitry is satisfied, the ISL6323 begins decoding the

inputs per Table 2. Once the EN input exceeds the rising

enable threshold, the ISL6323 saves the Pre-PWROK metal

VID value in an on-board holding register and passes this

target to the internal DAC circuitry.

VFIX MODE

In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed

external to the controller through jumpers to either GND or

VDDIO. These inputs are not expected to change, but the

ISL6323 is designed to support the potential change of state

of these inputs. If VFIXEN is high, the IC decodes the SVC

and SVD states per Table 3.

TABLE 2. PRE-PWROK METAL VID CODES

Once enabled, the ISL6323 begins to soft-start both VDD

and VDDNB planes to the programmed VFIX level. The

internal soft-start circuitry slowly stair steps the reference up

to the target value and this results in a controlled ramp of the

power planes. Once soft-start has ended and both output

planes are within regulation limits, the VDDPWRGD pin

transitions high. If the EN input falls below the enable falling

threshold, then the controller ramps both VDD and VDDNB

down to near zero.

SVC

SVD

OUTPUT VOLTAGE (V)

0

1

0

1

0

1

1.1

1.0

0.9

0.8

The Pre-PWROK metal VID code is decoded and latched on

the rising edge of the enable signal. Once enabled, the

ISL6323 passes the Pre-PWROK metal VID code on to

internal DAC circuitry. The internal DAC circuitry begins to

ramp both the VDD and VDDNB planes to the decoded

Pre-PWROK metal VID output level. The digital soft-start

circuitry actually stair steps the internal reference to the

target gradually over a fix interval. The controlled ramp of

both output voltage planes reduces in-rush current during

the soft-start interval. At the end of the soft-start interval, the

VDDPWRGD output transitions high indicating both output

planes are within regulation limits.

TABLE 3. VFIXEN VID CODES

SVC

SVD

OUTPUT VOLTAGE (V)

0

1

0

1

0

1

1.4

1.2

1.0

0.8

SVI MODE

Once the controller has successfully soft-started and

VDDPWRGD transitions high, the Northbridge SVI interface

can assert PWROK to signal the ISL6323 to prepare for SVI

commands. The controller actively monitors the SVI

If the EN input falls below the enable falling threshold, the

ISL6323 ramps the internal reference voltage down to near

zero. The VDDPWRGD de-asserts with the loss of enable.

FN9278.2

April 7, 2008

16

ISL6323

interface for set VID commands to move the plane voltages

to start-up VID values. Details of the SVI Bus protocol are

provided in the AMD Design Guide for Voltage Regulator

Controllers Accepting Serial VID Codes specification.

remains asserted. The Northbridge voltage plane must

remain active during this time.

If the PWROK input is de-asserted, then the controller steps

both VDD and VDDNB planes back to the stored

Once the set VID command is received, the ISL6323

Pre-PWROK metal VID level in the holding register from

initial soft-start. No attempt is made to read the SVC and

SVD inputs during this time. If PWROK is reasserted, then

the on-board SVI interface waits for a set VID command.

decodes the information to determine which plane and the

VID target required. See Table 4. The internal DAC circuitry

steps the required output plane voltage to the new VID level.

During this time one or both of the planes could be targeted.

In the event the core voltage plane, VDD, is commanded to

power off by serial VID commands, the VDDPWRGD signal

If VDDPWRGD deasserts during normal operation, both

voltage planes are powered down in a controlled fashion.

The internal DAC circuitry stair steps both outputs down to

near zero.

TABLE 4. SERIAL VID CODES

SVID[6:0]

000_0000b

000_0001b

000_0010b

000_0011b

000_0100b

000_0101b

000_0110b

000_0111b

000_1000b

000_1001b

000_1010b

000_1011b

000_1100b

000_1101b

000_1110b

000_1111b

001_0000b

001_0001b

001_0010b

001_0011b

001_0100b

001_0101b

001_0110b

001_0111b

001_1000b

001_1001b

001_1010b

001_1011b

001_1100b

001_1101b

001_1110b

001_1111b

VOLTAGE (V)

1.5500

1.5375

1.5250

1.5125

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

SVID[6:0]

010_0000b

010_0001b

010_0010b

010_0011b

010_0100b

010_0101b

010_0110b

010_0111b

010_1000b

010_1001b

010_1010b

010_1011b

010_1100b

010_1101b

010_1110b

010_1111b

011_0000b

011_0001b

011_0010b

011_0011b

011_0100b

011_0101b

011_0110b

011_0111b

011_1000b

011_1001b

011_1010b

011_1011b

011_1100b

011_1101b

011_1110b

011_1111b

VOLTAGE (V)

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

SVID[6:0]

100_0000b

100_0001b

100_0010b

100_0011b

100_0100b

100_0101b

100_0110b

100_0111b

100_1000b

100_1001b

100_1010b

100_1011b

100_1100b

100_1101b

100_1110b

100_1111b

101_0000b

101_0001b

101_0010b

101_0011b

101_0100b

101_0101b

101_0110b

101_0111b

101_1000b

101_1001b

101_1010b

101_1011b

101_1100b

101_1101b

101_1110b

101_1111b

VOLTAGE (V)

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875*

0.4750*

0.4625*

0.4500*

0.4375*

0.4250*

0.4125*

0.4000*

0.3875*

0.3750*

0.3625*

SVID[6:0]

110_0000b

110_0001b

110_0010b

110_0011b

110_0100b

110_0101b

110_0110b

110_0111b

110_1000b

110_1001b

110_1010b

110_1011b

110_1100b

110_1101b

110_1110b

110_1111b

111_0000b

111_0001b

111_0010b

111_0011b

111_0100b

111_0101b

111_0110b

111_0111b

111_1000b

111_1001b

111_1010b

111_1011b

111_1100b

111_1101b

111_1110b

111_1111b

VOLTAGE (V)

0.3500*

0.3375*

0.3250*

0.3125*

0.3000*

0.2875*

0.2750*

0.2625*

0.2500*

0.2375*

0.2250*

0.2125*

0.2000*

0.1875*

0.1750*

0.1625*

0.1500*

0.1375*

0.1250*

0.1125*

0.1000*

0.0875*

0.0750*

0.0625*

0.0500*

0.0375*

0.0250*

0.0125*

OFF

NOTE: * Indicates a VID not required for AMD Family 10h processors.

FN9278.2

April 7, 2008

17

ISL6323

The magnitude of the spike is dictated by the ESR and ESL

Voltage Regulation

of the output capacitors selected. By positioning the no-load

voltage level near the upper specification limit, a larger

negative spike can be sustained without crossing the lower

limit. By adding a well controlled output impedance, the

output voltage under load can effectively be level shifted

down so that a larger positive spike can be sustained without

crossing the upper specification limit.

The integrating compensation network shown in Figure 8

insures that the steady-state error in the output voltage is

limited only to the error in the reference voltage and offset

errors in the OFS current source, remote-sense and error

amplifiers. Intersil specifies the guaranteed tolerance of the

ISL6323 to include the combined tolerances of each of these

elements.

As shown in Figure 8, with the FS resistor tied to ground, the

The output of the error amplifier, V

, is used by the

COMP

average current of all active channels, I

, flows from FB

AVG

modulator to generate the PWM signals. The PWM signals

control the timing of the Internal MOSFET drivers and

regulate the converter output so that the voltage at FB is equal

to the voltage at REF. This will regulate the output voltage to

be equal to Equation 11. The internal and external circuitry

that controls voltage regulation is illustrated in Figure 8.

through a load-line regulation resistor R . The resulting

FB

voltage drop across R is proportional to the output current,

FB

effectively creating an output voltage droop with a steady-

state value defined as in Equation 12:

V

= I

⋅ R

AVG FB

(EQ. 12)

DROOP

(EQ. 11)

V

= V

– V

OFS DROOP

OUT

REF

The regulated output voltage is reduced by the droop voltage

The ISL6323 incorporates differential remote-sense

V

. The output voltage as a function of load current is

DROOP

shown in Equation 13.

amplification in the feedback path. The differential sensing

removes the voltage error encountered when measuring the

output voltage relative to the controller ground reference point

resulting in a more accurate means of sensing output voltage.

I

⎛

⎜

⎝

⎞

⎟

⎠

400

3

1

OUT

N

⎛

⎝

⎞

⎠

-------------

--------- --------------

V

= V

– V

–

⋅ DCR ⋅

⋅

⋅ K ⋅ R

FB

OUT

REF

OFS

R

SET

(EQ. 13)

EXTERNAL CIRCUIT

FS

ISL6323 INTERNAL CIRCUIT

In Equation 13, V

programmed offset voltage, I

is the reference voltage, V

OFS

is the

REF

is the total output current

OUT

of the converter, K is the DC gain of the RC filter across the

inductor (K is defined in Equation 7), N is the number of

active channels, and DCR is the Inductor DCR value.

TO

R

DROOP

CONTROL

FS

OSCILLATOR

COMP

Output-Voltage Offset Programming

The ISL6323 allows the designer to accurately adjust the

C

offset voltage by connecting a resistor, R

, from the OFS

is connected between OFS

I

OFS

AVG

pin to VCC or GND. When R

OFS

and VCC, the voltage across it is regulated to 1.6V. This

causes a proportional current (I ) to flow into the FB pin

R

C

I

OFS

FB

OFS

is connected to ground, the

-

V

COMP

and out of the OFS pin. If R

OFS

voltage across it is regulated to 0.3V, and I

+

flows into the

ERROR

AMPLIFIER

OFS

OFS pin and out of the FB pin. The offset current flowing

through the resistor between VDIFF and FB will generate the

desired offset voltage which is equal to the product

+

(V

-

R

+ V

)

FB

DROOP

OFS

(I

x R ). These functions are shown in Figures 9 and

FB

OFS

10.

+

VID

DAC

∑

VSEN

RGND

+

Once the desired output offset voltage has been determined,

use Equations 14 and 15 to set R

V

OUT

-

:

OFS

For Positive Offset (connect R

to GND):

OFS

FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

0.3 × R

FB

(EQ. 14)

(EQ. 15)

--------------------------

R

=

OFS

V

OFFSET

Load-Line (Droop) Regulation

For Negative Offset (connect R

to VCC):

By adding a well controlled output impedance, the output

voltage can effectively be level shifted in a direction which

works to achieve a cost-effective solution can help to reduce

the output-voltage spike that results from fast load-current

demand changes.

OFS

1.6 × R

FB

--------------------------

R

=

OFS

V

OFFSET

FN9278.2

April 7, 2008

18

ISL6323

To further improve dynamic VID performance, ISL6323 also

VDIFF

implements a proprietary DAC smoothing feature. The

external series RC components connected between DVC

and FB limit any stair-stepping of the output voltage during a

VID-on-the-Fly transition.

-

V

R

OFS

+

FB

VREF

+

-

E/A

Compensating Dynamic VID Transitions

FB

During a VID transition, the resulting change in voltage on

the FB pin and the COMP pin causes an AC current to flow

through the error amplifier compensation components from

the FB to the COMP pin. This current then flows through the

I

OFS

+

-

feedback resistor, R , and can cause the output voltage to

FB

VCC

overshoot or undershoot at the end of the VID transition. In

order to ensure the smooth transition of the output voltage

during a VID change, a VID-on-the-fly compensation

network is required. This network is composed of a resistor

-

R

OFS

+

1.6V

+

-

0.3V

OFS

and capacitor in series, R

and the FB pin.

and C , between the DVC

DVC

ISL6323

GND

VCC

I

= I

DVC

C

R

FB

VSEN

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

I

C

I

DVC

R

V

C

OUT

C

R

DVC

FB

COMP

+

V

R

OFS

-

FB

+

-

VREF

E/A

2X

-

FB

OFS

+

ERROR

AMPLIFIER

I

+

-

VDAC+RGND

ISL6323 INTERNAL CIRCUIT

FIGURE 11. DYNAMIC VID COMPENSATION NETWORK

-

This VID-on-the-fly compensation network works by

-

sourcing AC current into the FB node to offset the effects of

the AC current flowing from the FB to the COMP pin during a

VID transition. To create this compensation current the

ISL6323 sets the voltage on the DVC pin to be 2x the voltage

on the REF pin. Since the error amplifier forces the voltage

on the FB pin and the REF pin to be equal, the resulting

voltage across the series RC between DVC and FB is equal

to the REF pin voltage. The RC compensation components,

1.6V

+

-

0.3V

OFS

ISL6323

R

OFS

GND

VCC

GND

FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

R

and C , can then be selected to create the desired

DVC

Dynamic VID

amount of compensation current.

The AMD processor does not step the output voltage

The amount of compensation current required is dependant

on the modulator gain of the system, K1, and the error

commands up or down to the target voltage, but instead

passes only the target voltage to the ISL6323 through either

the PVI or SVI interface. The ISL6323 manages the resulting

VID-on-the-Fly transition in a controlled manner, supervising

a safe output voltage transition without discontinuity or

disruption. The ISL6323 begins slewing the DAC at

3.25mV/µs until the DAC and target voltage are equal. Thus,

the total time required for a dynamic VID transition is

dependent only on the size of the DAC change.

amplifier RC components, R and C , that are in series

C

between the FB and COMP pins. Use Equations 16, 17 and

18 to calculate the RC component values, R and C

,

DVC

for the VID-on-the-fly compensation network. For these

equations: V is the input voltage for the power train; V

IN P-P

is the oscillator ramp amplitude (1.5V); and R and C are

C

the error amplifier RC components between the FB and

COMP pins.

FN9278.2

April 7, 2008

19

ISL6323

V

(EQ. 16)

K1

K1 – 1

IN

ISL6323 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

---------------

----------------

K1 =

A =

V

P – P

R

= A × R

(EQ. 17)

(EQ. 18)

RCOMP

C

PVCC1_2

C

-------

=

C

RCOMP

A

PVCC_NB

+12V

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

POR

CIRCUIT

The integrated drivers incorporate a unique adaptive deadtime

control technique to minimize deadtime, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFET body-diode conduction, and to prevent the upper and

lower MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

ENABLE

COMPARATOR

10.7kΩ

EN

+

-

1.00kΩ

V

EN_THR

ISEN3-

ISEN4-

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V (forward/reverse

inductor current). At this time the UGATE is released to rise. An

CHANNEL

DETECT

SOFT-START

AND

FAULT LOGIC

auto-zero comparator is used to correct the r

drop in the

DS(ON)

phase voltage preventing false detection of the -0.3V phase

level during r conduction period. In the case of zero

FIGURE 12. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

DS(ON)

current, the UGATE is released after 35ns delay of the LGATE

dropping below 0.5V. When LGATE first begins to transition

low, this quick transition can disturb the PHASE node and

cause a false trip, so there is 20ns of blanking time once

LGATE falls until PHASE is monitored.

The bias voltage applied to the PVCC1_2 and PVCC_NB

pins power the internal MOSFET drivers of each output

channel. In order for the ISL6323 to begin operation, both

PVCC inputs must exceed their POR rising threshold to

guarantee proper operation of the internal drivers.

Hysteresis between the rising and falling thresholds assure

that once enabled, the ISL6323 will not inadvertently turn off

unless the PVCC bias voltage drops substantially (see

“Electrical Specifications” on page 6). Depending on the

number of active CORE channels determined by the Phase

Detect block, the external driver POR checking is supported

by the Enable Comparator.

Once the PHASE is high, the advanced adaptive

shoot-through circuitry monitors the PHASE and UGATE

voltages during a PWM falling edge and the subsequent

UGATE turn-off. If either the UGATE falls to less than 1.75V

above the PHASE or the PHASE falls to less than +0.8V, the

LGATE is released to turn-on.

Initialization

Enable Comparator

Prior to initialization, proper conditions must exist on the EN,

VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When

the conditions are met, the controller begins soft-start. Once

the output voltage is within the proper window of operation,

the controller asserts VDDPWRGD.

The ISL6323 features a dual function enable input (EN) for

enabling the controller and power sequencing between the

controller and external drivers or another voltage rail. The

enable comparator holds the ISL6323 in shutdown until the

voltage at EN rises above 0.86V. The enable comparator has

about 110mV of hysteresis to prevent bounce. It is important

that the driver ICs reach their rising POR level before the

ISL6323 becomes enabled. The schematic in Figure 12

demonstrates sequencing the ISL6323 with the ISL66xx

family of Intersil MOSFET drivers, which require 12V bias.

Power-On Reset

The ISL6323 requires VCC, PVCC1_2, and PVCC_NB

inputs to exceed their rising POR thresholds before the

ISL6323 has sufficient bias to guarantee proper operation.

The bias voltage applied to VCC must reach the internal

power-on reset (POR) rising threshold. Once this threshold

is reached, the ISL6323 has enough bias to begin checking

the driver POR inputs, EN, and channel detect portions of

the initialization cycle. Hysteresis between the rising and

falling thresholds assure the ISL6323 will not advertently

turn off unless the bias voltage drops substantially (see

“Electrical Specifications” on page 6).

When selecting the value of the resistor divider the driver

maximum rising POR threshold should be used for

calculating the proper resistor values. This will prevent

improper sequencing events from creating false trips during

soft-start.

If the controller is configured for 2-phase CORE operation,

then the resistor divider can be used for sequencing the

FN9278.2

April 7, 2008

20

ISL6323

controller with another voltage rail. The resistor divider to EN

should be selected using a similar approach as the previous

driver discussion.

After the DAC voltage reaches the final VID setting,

VDDPWRGD will be set to high.

The EN pin is also used to force the ISL6323 into either PVI

or SVI mode. The mode is set upon the rising edge of the EN

signal. When the voltage on the EN pin rises above 0.86V,

the mode will be set depending upon the status of the

VID1/SEL pin.

V

NB

400mV/DIV

V

CORE

400mV/DIV

Phase Detection

TDA

TDB

EN

5V/DIV

The ISEN3- and ISEN4- pins are monitored prior to soft-start

to determine the number of active CORE channel phases.

VDDPWRGD

5V/DIV

If ISEN4- is tied to VCC, the controller will configure the

channel firing order and timing for 3-phase operation. If

ISEN3- and ISEN4- are tied to VCC, the controller will set

the channel firing order and timing for 2-phase operation

(see “PWM Operation” on page 12 for details). If Channel 4

and/or Channel 3 are disabled, then the corresponding

PWMn and ISENn+ pins may be left unconnected

100µs/DIV

FIGURE 13. SOFT-START WAVEFORMS

Pre-Biased Soft-Start

Soft-Start Output Voltage Targets

The ISL6323 also has the ability to start up into a

Once the POR and Phase Detect blocks and enable

comparator are satisfied, the controller will begin the

soft-start sequence and will ramp the CORE and NB output

voltages up to the SVI interface designated target level if the

controller is set SVI mode. If set to PVI mode, the North

Bridge regulator is disabled and the core is soft started to the

level designated by the parallel VID code.

pre-charged output, without causing any unnecessary

disturbance. The FB pin is monitored during soft-start, and

should it be higher than the equivalent internal ramping

reference voltage, the output drives hold both MOSFETs off.

Once the internal ramping reference exceeds the FB pin

potential, the output drives are enabled, allowing the output to

ramp from the pre-charged level to the final level dictated by

the DAC setting. Should the output be pre-charged to a level

exceeding the DAC setting, the output drives are enabled at

the end of the soft-start period, leading to an abrupt correction

in the output voltage down to the DAC-set level.

SVI MODE

Prior to soft-starting both CORE and NB outputs, the

ISL6323 must check the state of the SVI interface inputs to

determine the correct target voltages for both outputs. When

the controller is enabled, the state of the VFIXEN, SVD and

SVC inputs are checked and the target output voltages set

for both CORE and NB outputs are set by the DAC (see

“Serial VID Interface (SVI)” on page 15). These targets will

only change if the EN signal is pulled low or after a POR

reset of VCC.

Both CORE and NB output support start up into a

pre-charged output.

OUTPUT PRECHARGED

ABOVE DAC LEVEL

Soft-Start

OUTPUT PRECHARGED

BELOW DAC LEVEL

The soft-start sequence is composed of three periods, as

shown in Figure 13. At the beginning of soft-start, the DAC

immediately obtains the output voltage targets for both

outputs by decoding the state of the SVI or PVI inputs. A

100µs fixed delay time, TDA, proceeds the output voltage

rise. After this delay period the ISL6323 will begin ramping

both CORE and NB output voltages to the programmed DAC

level at a fixed rate of 3.25mV/µs. The amount of time

required to ramp the output voltage to the final DAC voltage

is referred to as TDB, and can be calculated as shown in

Equation 19.

V

CORE

400mV/DIV

EN

5V/DIV

100µs/DIV

FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323-BASED

MULTIPHASE CONVERTER

V

DAC

------------------------------

TDB =

(EQ. 19)

–3

3.25 × 10

FN9278.2

April 7, 2008

21

ISL6323

Overvoltage Protection

The ISL6323 constantly monitors the sensed output voltage

on the VSEN pin to detect if an overvoltage event occurs.

When the output voltage rises above the OVP trip level and

exceeds the VDDPWRGD OV limit actions are taken by the

ISL6323 to protect the microprocessor load.

142µA

-

OCL

+

I

1

REPEAT FOR EACH

CORE CHANNEL

100µA

-

OCP

At the inception of an overvoltage event, both on-board

lower gate pins are commanded low as are the active PWM

outputs to the external drivers, the VDDPWRGD signal is

driven low, and the ISL6323 latches off normal PWM action.

This turns on the all of the lower MOSFETs and pulls the

output voltage below a level that might cause damage to the

load. The lower MOSFETs remain driven ON until VDIFF

falls below 400mV. The ISL6323 will continue to protect the

load in this fashion as long as the overvoltage condition

recurs. Once an overvoltage condition ends the ISL6323

latches off, and must be reset by toggling POR, before a

soft-start can be re-initiated.

+

I

100µA

NB

-

OCP

+

I

AVG

CORE ONLY

NB ONLY

SOFT-START, FAULT

AND CONTROL LOGIC

DUPLICATED FOR

NB AND CORE

+

1.8V

OVP

-

+

DAC + 250mV

DAC - 300mV

Pre-POR Overvoltage Protection

OV

-

Prior to PVCC and VCC exceeding their POR levels, the

ISL6323 is designed to protect either load from any

overvoltage events that may occur. This is accomplished by

means of an internal 10kΩ resistor tied from PHASE to

LGATE, which turns on the lower MOSFET to control the

output voltage until the overvoltage event ceases or the input

power supply cuts off. For complete protection, the low side

MOSFET should have a gate threshold well below the

maximum voltage rating of the load/microprocessor.

-

VSEN

UV

+

VDDPWRGD

ISL6323 INTERNAL CIRCUITRY

FIGURE 15. POWER GOOD AND PROTECTION CIRCUITRY

Fault Monitoring and Protection

The ISL6323 actively monitors both CORE and NB output

voltages and currents to detect fault conditions. Fault

monitors trigger protective measures to prevent damage to

either load. One common power good indicator is provided

for linking to external system monitors. The schematic in

Figure 15 outlines the interaction between the fault monitors

and the power good signal.

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at VDAC - 300mV typical.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, VDDPWRGD gets pulled low. No

other action is taken by the controller. VDDPWRGD will

return high if the output voltage rises above VDAC - 250mV

typical.

Power Good Signal

The power good pin (VDDPWRGD) is an open-drain logic

output that signals whether or not the ISL6323 is regulating

both NB and CORE output voltages within the proper levels,

and whether any fault conditions exist. This pin should be

tied to a +5V source through a resistor.

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6323 is designed to detect this

and shut down the controller. This event is detected by

monitoring small currents that are fed out the VSEN and

RGND pins. In the event of an open sense line fault, the

controller will continue to remain off until the fault goes away,

at which point the controller will re-initiate a soft-start

sequence.

During shutdown and soft-start, VDDPWRGD pulls low and

releases high after a successful soft-start and both output

voltages are operating between the undervoltage and

overvoltage limits. VDDPWRGD transitions low when an

undervoltage, overvoltage, or overcurrent condition is

detected on either output or when the controller is disabled

by a POR reset or EN. In the event of an overvoltage or

overcurrent condition, the controller latches off and

VDDPWRGD will not return high. Pending a POR reset of

the ISL6323 and successful soft-start, the VDDPWRGD will

return high.

Overcurrent Protection

The ISL6323 takes advantage of the proportionality between

the load current and the average current, I

, to detect an

AVG

overcurrent condition. See “Continuous Current Sampling”

FN9278.2

April 7, 2008

22

ISL6323

on page 13 and “Channel-Current Balance” on page 14 for

more detail on how the average current is measured. Once

the average current exceeds 100µA, a comparator triggers

the converter to begin overcurrent protection procedures.

The Core regulator and the North Bridge regulator have the

same type of overcurrent protection.

Note that the energy delivered during trip-retry cycling is

much less than during full-load operation, so there is no

thermal hazard.

OUTPUT CURRENT, 50A/DIV

The overcurrent trip threshold is dictated by the DCR of the

inductors, the number of active channels, the K gain (which

I

is determined by the R

resistor) the DC gain of the

SET

inductor RC filter and the internal R resistor. The

ISEN

overcurrent trip threshold is shown in Equation 20.

0A

N

DCR

1

K

3

⎛

(EQ. 20)

⎞

------------- --- ---------

⋅ R

SET

I

= 100μA ⋅

⋅

OCP

⎝

400

⎠

OUTPUT VOLTAGE,

500mV/DIV

Where:

R

2

See “Continuous Current Sampling” on

page 13.

K = --------------------

+ R

0V

R

1

2

3ms/DIV

FIGURE 16. OVERCURRENT BEHAVIOR IN HICCUP MODE

Equation 20 is valid for both the Core regulator and the

North Bridge regulator. For the North Bridge regulator, N is 1.

NORTH BRIDGE REGULATOR OVERCURRENT

The overcurrent shutdown sequence for the North Bridge

regulator is identical to the Core regulator with the exception

that it is a single phase regulator and will only disable the

MOSFET drivers for the North Bridge. Once 7 retry attempts

have been executed unsuccessfully, the controller will disable

UGATE and LGATE signals for both Core and North Bridge

and will latch off requiring a POR of VCC to reset the ISL6323.

During soft-start, the overcurrent trip point is boosted by a

factor of 1.4. Instead of comparing the average measured

current to 100µA, the average current is compared to 140µA.

Immediately after soft-start is over, the comparison level

changes to 100µA. This is done to allow for start-up into an

active load while still supplying output capacitor in-rush

current.

Note that the energy delivered during trip-retry cycling is

much less than during full-load operation, so there is no

thermal hazard.

CORE REGULATOR OVERCURRENT

At the beginning of overcurrent shutdown, the controller sets

all of the UGATE and LGATE signals low, puts PWM3 and

PWM4 (if active) in a high-impedance state, and forces

VDDPWRGD low. This turns off all of the upper and lower

MOSFETs. The system remains in this state for fixed period of

12ms. If the controller is still enabled at the end of this wait

period, it will attempt a soft-start, as shown in Figure 16. If the

fault remains, the trip-retry cycles will continue until either the

fault is cleared or for a total of seven attempts. If the fault is

not cleared on the final attempt, the controller disables

UGATE and LGATE signals for both Core and North Bridge

and latches off requiring a POR of VCC to reset the ISL6323.

Individual Channel Overcurrent Limiting

The ISL6323 has the ability to limit the current in each

individual channel of the Core regulator without shutting

down the entire regulator. This is accomplished by

continuously comparing the sensed currents of each channel

with a constant 140µA OCL reference current. If a channel’s

individual sensed current exceeds this OCL limit, the UGATE

signal of that channel is immediately forced low, and the

LGATE signal is forced high. This turns off the upper

MOSFET(s), turns on the lower MOSFET(s), and stops the

rise of current in that channel, forcing the current in the

channel to decrease. That channel’s UGATE signal will not

be able to return high until the sensed channel current falls

back below the 140µA reference.

It is important to note that during soft start, the overcurrent

trip point is increased by a factor of 1.4. If the fault draws

enough current to trip overcurrent during normal run mode, it

may not draw enough current during the soft-start ramp

period to trip overcurrent while the output is ramping up. If a

fault of this type is affecting the output, then the regulator will

complete soft-start and the trip-retry counter will be reset to

zero. Once the regulator has completed soft-start, the

overcurrent trip point will return to it’s nominal setting and an

overcurrent shutdown will be initiated. This will result in a

continuous hiccup mode.

General Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following. In addition to this guide, Intersil provides complete

reference designs that include schematics, bills of materials,

and example board layouts for all common microprocessor

applications.

FN9278.2

April 7, 2008

23

ISL6323

higher portion of the upper-MOSFET losses are dependent

Power Stages

on switching frequency, the power calculation is more

complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode reverse

The first step in designing a multiphase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

the maximum amount of load current. Generally speaking,

the most economical solutions are those in which each

phase handles between 25A and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and heat

dissipating surfaces.

recovery charge, Q , and the upper MOSFET r

rr

DS(ON)

conduction loss.

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 23,

the required time for this commutation is t and the

1

approximated associated power loss is P

.

UP(1)

t

⎞

1

I

⎛

M

P – P

2

⎛

⎝

⎞

(EQ. 23)

P

≈ V

⋅

⋅ f

⎜ ---- ⎟

S

----- + -------------

UP(1)

IN

⎠

2

N

⎝

⎠

At turn-on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 24, the

MOSFETS

2

approximate power loss is P

.

UP(2)

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

I

t

2

⎠

⎛I

⎞

⎛

⎞

P – P

2

M

(EQ. 24)

P

≈ V

⋅

⋅ f

S

⎜

⎝

-------------⎟ ⎜ ---- ⎟

----- –

UP(2)

IN

N

⎠

⎝

A third component involves the lower MOSFET

LOWER MOSFET POWER CALCULATION

reverse-recovery charge, Q . Since the inductor current has

rr

fully commutated to the upper MOSFET before the

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

lower-MOSFET body diode can recover all of Q , it is

rr

conducted through the upper MOSFET across VIN. The

power dissipated as a result is P

Equation 25.

as shown in

(r

). In Equation 21, I is the maximum continuous

UP(3)

DS(ON)

output current, I

M

is the peak-to-peak inductor current (see

P-P

Equation 2), and d is the duty cycle (V

/V ).

(EQ. 25)

OUT IN

P

= V ⋅ Q ⋅ f

UP(3) IN rr S

2

I

⋅ (1 – d)

(EQ. 21)

⎛

⎜

⎝

⎞

⎟

⎠

I

L(P – P)

M

Finally, the resistive part of the upper MOSFET is given in

Equation 26 as P

P

= r

⋅

DS(ON)

⋅ (1 – d) + ----------------------------------------------

-----

LOW, 1

12

N

.

UP(4)

2

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

⎛

⎜

⎝

⎞

⎟

⎠

I

P – P

M

(EQ. 26)

P

≈ r

⋅

DS(ON)

⋅ d +

-------------

-----

UP(4)

12

N

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 23, 24, 25 and 26. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

diode forward voltage at I , V

, the switching

M

D(ON)

frequency, f , and the length of dead times, t and t , at

S

d1 d2

the beginning and the end of the lower-MOSFET conduction

interval respectively.

⎛

⎜

⎝

⎞

⎟

⎠

⎛I

⎞

⎟

⎠

I

M

P

= V

⋅ f

⋅

S

P + P

2

P – P

2

⋅ t

+

⋅ t

⎜

---------------

------ –

------ + ---------------

LOW, 2

D(ON)

d1

d2

⎝ N

N

(EQ. 22)

Internal Bootstrap Device

All three integrated drivers feature an internal bootstrap

Schottky diode. Simply adding an external capacitor across

the BOOT and PHASE pins completes the bootstrap circuit.

The bootstrap function is also designed to prevent the

bootstrap capacitor from overcharging due to the large

negative swing at the PHASE node. This reduces voltage

stress on the boot to phase pins.

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of P and P

.

LOW,1 LOW,2

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the upper

DS(ON)

MOSFET losses are due to currents conducted across the

input voltage (V ) during switching. Since a substantially

IN

FN9278.2

April 7, 2008

24

ISL6323

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 4V and its capacitance value can be

chosen from Equation 27:

When designing the ISL6323 into an application, it is

recommended that the following calculations is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

Q

GATE

-------------------------------------

C

≥

P

, due to the gate charge of MOSFETs and the

BOOT_CAP

ΔV

Qg_TOT

BOOT_CAP

(EQ. 27)

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 28

and 29, respectively.

Q

• PVCC

G1

-----------------------------------

Q

=

• N

Q1

GATE

V

GS1

P

= P

+ P

+ I ⋅ VCC

Qg_Q2 Q

(EQ. 28)

Qg_TOT

Qg_Q1

where Q is the amount of gate charge per upper MOSFET

G1

3

2

at V

gate-source voltage and N is the number of

--

P

=

⋅ Q

⋅ PVCC ⋅ f

⋅ N

Q1 PHASE

GS1

control MOSFETs. The ΔV

Q1

Qg_Q1

G1

SW

term is defined as the

BOOT_CAP

allowable droop in the rail of the upper gate drive.

P

= Q

⋅ PVCC ⋅ f

⋅ N

PHASE

Qg_Q2

G2

SW

Q2

1.6

(EQ. 29)

1.4

1.2

1.0

0.8

0.6

3

2

⎛

⎝

⎞

--

I

=

⋅ Q

⋅ N

+ Q

⋅ N

⋅ f

+ I

DR

G1

G2

Q2

⎠

PHASE SW Q

Q1

In Equations 28 and 29, P

power loss and P

Qg_Q2

loss; the gate charge (Q and Q ) is defined at the

particular gate to source drive voltage PVCC in the

is the total upper gate drive

is the total lower gate drive power

Qg_Q1

G1 G2

corresponding MOSFET data sheet; I is the driver total

Q

= 100nC

quiescent current with no load at both drive outputs; N and

Q1

GATE

0.4

N

are the number of upper and lower MOSFETs per phase,

Q2

respectively; N

50nC

is the number of active phases. The

PHASE

0.2

0.0

20nC

I *VCC product is the quiescent power of the controller

Q

without load on the drives.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

PVCC

BOOT

ΔV (V)

BOOT_CAP

D

FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

C

GD

R

HI1

G

Gate Drive Voltage Versatility

UGATE

C

DS

The ISL6323 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

R

LO1

R

GI1

C

G1

GS

Q1

S

PHASE

FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

Package Power Dissipation

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of three

drivers in the controller package, the total power dissipated

by all three drivers must be less than the maximum

allowable power dissipation for the QFN package.

PVCC

D

C

GD

R

HI2

G

LGATE

C

DS

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of +125°C. The maximum allowable IC power

dissipation for the 7x7 QFN package is approximately 3.5W

at room temperature. See “Layout Considerations” on

page 32 for thermal transfer improvement suggestions.

R

LO2

R

GI2

C

G2

GS

Q2

S

FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

FN9278.2

April 7, 2008

25

ISL6323

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in

the controller itself is the power dissipated in the upper drive

2. Calculate the value for resistor R using Equation 32:

1

L

NB

⋅ C

NB

(EQ. 32)

resistor using Equation

(EQ. 33)

-------------------------------------

R

=

1

DCR

NB

path resistance (P

) the lower drive path resistance

) and in the boot strap diode (P ). The rest of

3. Calculate the value for the R

SET

DR_UP

39: (Derived from Equation 20).

(P

DR_UP

BOOT

the power will be dissipated by the external gate resistors

(R and R ) and the internal gate resistors (R and

I

OCP

400

NB

--------- ---------------------

R

=

⋅

⋅ DCR

⋅ K

NB

SET

G1 G2 GI1

3

100μA

R

) of the MOSFETs. Figures 18 and 19 show the typical

GI2

Where:

K = 1

upper and lower gate drives turn-on transition path. The total

power dissipation in the controller itself, P , can be roughly

4. Using Equation 34 (also derived from Equation 20),

DR

estimated as Equation 30:

calculate the value of K for the Core regulator.

P

= P

+ P

+ (I ⋅ VCC)

100μA

-------------------------- ----------------------------- ---------

⋅ R

SET

N

3

⎝

400

(EQ. 34)

⎛

⎞

DR

DR_UP

DR_LOW

BOOT

Q

K =

⋅

⎠

I

DCR

Core

CORE

OCP

P

Qg_Q1

---------------------

P

=

BOOT

3

5. Choose a capacitor value for the Core RC filters. A 0.1µF

capacitor is a recommended starting point.

R

P

⎛

⎞

HI1

LO1

Qg_Q1

-------------------------------------- --------------------------------------- ---------------------

P

=

+

⋅

⎜

⎝

⎟

⎠

DR_UP

R

+ R

R

+ R

EXT1

3

6. Calculate the values for R and R for Core.

HI1

EXT1

LO1

1

2

Equations 41 and 42 will allow for their computation.

R

P

Qg_Q2

⎛

⎜

⎝

⎞

R

HI2

LO2

2

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

⋅

⎟

Core

+ R

(EQ. 35)

DR_LOW

R

+ R

R

+ R

EXT2

2

----------------------------------------------

K =

⎠

HI2

EXT2

LO2

R

1

2

Core

R

GI1

GI2

-------------

R

⋅ R

2

= R

+

R

= R

G2

+

1

L

EXT1

G1

EXT2

N

Core

(EQ. 36)

Q1

Q2

--------------------------

----------------------------------------------

=

⋅ C

Core

DCR

Core

R

+ R

2

1

(EQ. 30)

Core

Inductor DCR Current Sensing Component

CASE 2

Selection and R

Value Calculation

SET

resistor setting the value of the

I

Core

MAX

(EQ. 37)

With the single R

--------------------------

I

⋅ DCR

>

⋅ DCR

Core

SET

NB

N

MAX

effective internal sense resistors for both the North Bridge

and Core regulators, it is important to set the R value

SET

In Case 2, the DC voltage across the North Bridge inductor

at full load is greater than the DC voltage across a single

phase of the Core regulator while at full load. Here, the DC

voltage across the North Bridge inductor must be scaled

down to match the DC voltage across the Core inductors,

which will be impressed across the ISEN pins without any

and the inductor RC filter gain, K, properly. See “Continuous

Current Sampling” on page 13 and “Channel-Current

Balance” on page 14 for more details on the application of

the R

SET

resistor and the RC filter gain.

There are 3 separate cases to consider when calculating

these component values.

gain. So, the R resistor for the Core inductor RC filters is

2

left unpopulated and K = 1.

CASE 1

1. Choose a capacitor value for the Core RC filter. A 0.1µF

capacitor is a recommended starting point.

I

Core

MAX

(EQ. 31)

--------------------------

⋅ DCR

Core

I

⋅ DCR

<

NB

N

MAX

2. Calculate the value for resistor R :

1

In Case 1, the DC voltage across the North Bridge inductor

at full load is less than the DC voltage across a single phase

of the Core regulator while at full load. Here, the DC voltage

across the Core inductors must be scaled down to match the

DC voltage across the North Bridge inductor, which will be

impressed across the ISEN_NB pins without any gain. So,

L

Core

(EQ. 38)

-----------------------------------------------

R

=

1

DCR

⋅ C

Core

3. Calculate the value for the R

I

resistor using Equation 39:

SET

OCP

DCR

400

CORE

N

(EQ. 39)

--------- ------------------------------ -----------------------------

⋅ K

R

=

⋅

SET

3

100μA

the R resistor for the North Bridge inductor RC filter is left

unpopulated and K = 1.

2

Where:

K = 1

(Derived from Equation 20).

1. Choose a capacitor value for the North Bridge RC filter. A

0.1µF capacitor is a recommended starting point.

FN9278.2

April 7, 2008

26

ISL6323

4. Using Equation 40 (also derived from Equation 20),

to an inductor with higher DCR. If the R

resistor is

SET

that is less than

calculate the value of K for the North bridge regulator.

greater than 80kΩ, then a value of R

SET

80kΩ must be chosen and a resistor divider across both

North Bridge and Core inductors must be set up with proper

gain. This gain will represent the variable “K” in all equations.

100μA

--------------------- --------------------- ---------

⋅ R

SET

1

3

⎝

400

⎛

⎞

(EQ. 40)

K =

⋅

⎠

I

DCR

Core

NB

It is also very important that the R

between the RSET pin and the VCC pin of the ISL6323.

resistor be tied

SET

5. Choose a capacitor value for the North Bridge RC filter. A

0.1µF capacitor is a recommended starting point.

6. Calculate the values for R and R for North Bridge.

1

2

Inductor DCR Current Sensing Component Fine

Tuning

Equations 41 and 42 will allow for their computation.

R

2

I

NB

V

(EQ. 41)

IN

L

------------------------------------

K =

n

R

+ R

1

2

UGATE(n)

LGATE(n)

NB

L

DCR

V

OUT

MOSFET

DRIVER

R

⋅ R

2

1

L

NB

(EQ. 42)

---------------------

------------------------------------

⋅ C

=

INDUCTOR

NB

C

DCR

NB

R

+ R

OUT

1

2

-

NB

V (s)

L

-

V

(s)

C

CASE 3

I

Core

R

1

MAX

(EQ. 43)

--------------------------

⋅ DCR

Core

I

⋅ DCR

=

NB

MAX

NB

N

R

2

ISL6323 INTERNAL CIRCUIT

In Case 3, the DC voltage across the North Bridge inductor

at full load is equal to the DC voltage across a single phase

of the Core regulator while at full load. Here, the full scale

DC inductor voltages for both North Bridge and Core will be

I

n

SAMPLE

impressed across the ISEN pins without any gain. So, the R

resistors for the Core and North Bridge inductor RC filters

are left unpopulated and K = 1 for both regulators.

2

+

-

ISENn-

-

V

(s)

C

For this Case, it is recommended that the overcurrent trip

point for the North Bridge regulator be equal to the

overcurrent trip point for the Core regulator divided by the

number of core phases.

ISENn+

VCC

R

ISEN

I

SEN

RSET

R

SET

1. Choose a capacitor value for the North Bridge RC filter. A

0.1µF capacitor is a recommended starting point.

C

SET

2. Calculate the value for the North Bridge resistor R :

1

FIGURE 20. DCR SENSING CONFIGURATION

L

NB

(EQ. 44)

-------------------------------------

R

=

1

Due to errors in the inductance and/or DCR it may be

necessary to adjust the value of R and R to match the time

DCR

⋅ C

NB

1

2

constants correctly. The effects of time constant mismatch

can be seen in the form of droop overshoot or undershoot

during the initial load transient spike, as shown in Figure 21.

Follow the steps below to ensure the RC and inductor

L/DCR time constants are matched accurately.

3. Choose a capacitor value for the Core RC filter. A 0.1µF

capacitor is a recommended starting point.

4. Calculate the value for the Core resistor R :

1

L

Core

(EQ. 45)

-----------------------------------------------

R

=

1

DCR

⋅ C

Core

1. If the regulator is not utilizing droop, modify the circuit by

placing the frequency set resistor between FS and

Ground for the duration of this procedure.

3. Calculate the value for the R

resistor using Equation 46:

(EQ. 46)

SET

I

OCP

400

3

NB

2. Capture a transient event with the oscilloscope set to

about L/DCR/2 (sec/div). For example, with L = 1µH and

DCR = 1mΩ, set the oscilloscope to 500µs/div.

--------- ---------------------

R

=

⋅

⋅ DCR

⋅ K

NB

SET

100μA

Where:

K = 1

3. Record ΔV1 and ΔV2 as shown in Figure 21.Select new

values, R

and R

) for the time constant

NOTE: The values of R

SET

must be greater than 20kΩ and

1(NEW)

2(NEW

less than 80kΩ. For all of the 3 cases above, if the calculated

value of R is less than 20kΩ, then either the OCP trip

SET

point needs to be increased or the inductor must be changed

FN9278.2

April 7, 2008

27

ISL6323

resistors based on the original values, R

and

1(OLD)

C

(OPTIONAL)

2

R

using Equations 47 and 48.

2(OLD)

ΔV

1

(EQ. 47)

---------

R_1(NEW)= R_1(OLD)

⋅

C

R

ΔV

C

2

COMP

FB

ΔV

(EQ. 48)

1

---------

R_2(1)(NEW)= R_2(OLD)

⋅

ΔV

2

ISL6323

R

FB

4. Replace R and R with the new values and check to see

1

2

that the error is corrected. Repeat the procedure if

necessary.

VSEN

FIGURE 22. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6323 CIRCUIT

ΔV

2

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the LC

poles and the ESR zero of the voltage mode approximation,

yields a solution that is always stable with very close to ideal

transient performance.

ΔV

1

V

OUT

I

TRAN

ΔI

Select a target bandwidth for the compensated system, f .

0

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR

Loadline Regulation Resistor

The loadline regulation resistor, labeled R in Figure 8,

FB

sets the desired loadline required for the application.

compensation components depend on the relationships of f

to the LC pole frequency and the ESR zero frequency. For

each of the following three, there is a separate set of

equations for the compensation components.

0

Equation 49 can be used to calculate R

.

FB

V

DROOP

MAX

R

= ---------------------------------------------------------------------

(EQ. 49)

FB

I

In Equation 50, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

OUT

400

3

DCR

MAX

--------- ------------------------- --------------

⋅ K

⋅

N

R

SET

the bulk output filter capacitance; and V

is the peak-to-

Where K is defined in Equation 7.

P-P

peak sawtooth signal amplitude as described in the

“Electrical Specifications” table on page 6.

If no loadline regulation is required, FS resistor should be

tied between the FS pin and VCC. To choose the value for

Once selected, the compensation values in Equation 50

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

R

in this situation, please refer to “Compensation Without

FB

Loadline Regulation” on page 29.

Compensation With Loadline Regulation

improved by making adjustments to R . Slowly increase the

C

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter LC resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

value of R while observing the transient performance on an

oscilloscope until no further improvement is noted. Normally,

C

will not need adjustment. Keep the value of C from

C

Equation 50 unless some performance issue is noted.

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (see Figure 22). Keep

compensation components, R and C .

C

a position available for C , and be prepared to install a high

2

frequency capacitor of between 22pF and 150pF in case any

leading edge jitter problem is noted.

FN9278.2

April 7, 2008

28

ISL6323

too much phase shift below the system bandwidth as shown in

Equation 51.

1

------------------------------- > f

0

2 ⋅ π ⋅ L ⋅ C

Case 1:

C ⋅ ESR

L ⋅ C – C ⋅ ESR

2 ⋅ π ⋅ f ⋅ V

⋅ L ⋅ C

-------------------------------------------

⋅

FB

R

= R

0

pp

1

-------------------------------------------------------

⋅

FB

R

C

= R

C

0.66 ⋅ V

IN

0.66 ⋅ V

IN

L ⋅ C – C ⋅ ESR

= ----------------------------------------------------

C

= -------------------------------------------

C

1

2 ⋅ π ⋅ V

⋅ R ⋅ f

0

R

PP

FB

1

0.75 ⋅ V

-------------------------------

2 ⋅ π ⋅ L ⋅ C

≤ f < -------------------------------------

IN

0

2 ⋅ π ⋅ C ⋅ ESR

C

= --------------------------------------------------------------------------------------------------------

Case 2:

2

(2 ⋅ π) ⋅ f ⋅ f

⋅ ( L ⋅ C) ⋅ R ⋅ V

0

HF

FB P – P

(EQ. 51)

2

V

⋅ (2 ⋅ π) ⋅ f ⋅ L ⋅ C

0

PP

----------------------------------------------------------------

⋅

FB

R

C

= R

(EQ. 50)

C

0.66 ⋅ V

2

IN

⎛ ⎞

⋅ 2π

⋅ f ⋅ f

⋅ L ⋅ C ⋅ R

FB

V

0

HF

PP

⎝

⎠

0.66 ⋅ V

R

C

= ----------------------------------------------------------------------------------------

IN

C

= -------------------------------------------------------------------------------------

(2 ⋅ π) ⋅ f ⋅ V

⋅

⋅ (2 ⋅ π ⋅ f

⋅

L ⋅ C–1)

0.75

V

IN

HF

2

⋅ R

⋅ L ⋅ C

0

PP

FB

0.75 ⋅ V ⋅ (2 ⋅ π ⋅ f

⋅ L ⋅ C–1)

1

IN

HF

Case 3:

f

> -------------------------------------

= --------------------------------------------------------------------------------------------------------

0

2 ⋅ π ⋅ C ⋅ ESR

2

(2 ⋅ π) ⋅ f ⋅ f

⋅ ( L ⋅ C) ⋅ R ⋅ V

0

HF

FB P – P

2 ⋅ π ⋅ f ⋅ V ⋅ L

0

pp

--------------------------------------------

⋅

FB

R

C

= R

In the solutions to the compensation equations, there is a

single degree of freedom. For the solutions presented in

C

0.66 ⋅ V ⋅ ESR

IN

0.66 ⋅ V ⋅ ESR ⋅

C

IN

Equation 52, R is selected arbitrarily. The remaining

FB

= ----------------------------------------------------------------

2 ⋅ π ⋅ V ⋅ R ⋅ f

⋅

0

L

compensation components are then selected according to

Equation 52.

PP

FB

Compensation Without Loadline Regulation

In Equation 52, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent-series resistance of

The non load-line regulated converter is accurately modeled

as a voltage-mode regulator with two poles at the LC

resonant frequency and a zero at the ESR frequency. A

type-III controller, as shown in Figure 23, provides the

necessary compensation.

the bulk output-filter capacitance; and V

is the peak-to-

P-P

peak sawtooth signal amplitude as described in “Electrical

Specifications” on page 6.

C

2

Output Filter Design

1

C

------------------------------- > f

R

Case 1:

C

0

COMP

FB

2 ⋅ π ⋅ L ⋅ C

2 ⋅ π ⋅ f ⋅ V

⋅ L ⋅ C

0

pp

-------------------------------------------------------

⋅

FB

R

C

= R

C

0.66 ⋅ V

IN

C

1

0.66 ⋅ V

ISL6323

IN

= ----------------------------------------------------

2 ⋅ π ⋅ V

⋅ R ⋅ f

0

PP

FB

R

FB

1

-------------------------------

≤ f < -------------------------------------

VSEN

0

2 ⋅ π ⋅ C ⋅ ESR

Case 2:

2 ⋅ π ⋅ L ⋅ C

2

V

⋅ (2 ⋅ π) ⋅ f ⋅ L ⋅ C

0

PP

----------------------------------------------------------------

⋅

FB

R

C

= R

(EQ. 52)

C

0.66 ⋅ V

FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE

REGULATION

IN

0.66 ⋅ V

IN

= -------------------------------------------------------------------------------------

(2 ⋅ π) ⋅ f ⋅ V

2

⋅ R

⋅ L ⋅ C

The first step is to choose the desired bandwidth, f , of the

0

PP

FB

0

compensated system. Choose a frequency high enough to

assure adequate transient performance but not higher than 1/3

of the switching frequency. The type-III compensator has an

1

Case 3:

f > -------------------------------------

0

2 ⋅ π ⋅ C ⋅ ESR

extra high-frequency pole, f . This pole can be used for added

HF

noise rejection or to assure adequate attenuation at the error

amplifier high-order pole and zero frequencies. A good general

2 ⋅ π ⋅ f ⋅ V ⋅ L

0

pp

--------------------------------------------

⋅

FB

R

C

= R

C

0.66 ⋅ V ⋅ ESR

IN

rule is to choose f = 10f , but it can be higher if desired.

HF

0

0.66 ⋅ V ⋅ ESR ⋅

C

IN

Choosing f to be lower than 10f can cause problems with

= ----------------------------------------------------------------

2 ⋅ π ⋅ V ⋅ R ⋅ f

HF

0

⋅

0

L

PP

FB

FN9278.2

April 7, 2008

29

ISL6323

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

ΔV

. This places an upper limit on inductance.

MAX

Equation 55 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 56

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ΔI,

the load-current slew rate, di/dt, and the maximum allowable

output-voltage deviation under transient loading, ΔV

.

MAX

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

2 ⋅ N ⋅ C ⋅ V

O

(EQ. 55)

---------------------------------

L ≤

⋅ ΔV

– (ΔI ⋅ ESR)

MAX

2

(

)

ΔI

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total output

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount

as shown in Equation 53:

⋅ N ⋅ C

1.25

(EQ. 56)

⎛ ⎞

– (ΔI ⋅ ESR) ⋅ V – V

IN O

----------------------------

L ≤

⋅ ΔV

MAX

2

⎝

⎠

(

)

ΔI

Switching Frequency

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper MOSFET loss calculation. These effects are

outlined in “MOSFETs” on page 24, and they establish the

upper limit for the switching frequency. The lower limit is

established by the requirement for fast transient response

and small output-voltage ripple as outlined in “Output Filter

Design” on page 29. Choose the lowest switching frequency

that allows the regulator to meet the transient-response

requirements.

di

----

(EQ. 53)

ΔV ≈ ESL ⋅ + ESR ⋅ ΔI

dt

The filter capacitor must have sufficiently low ESL and ESR

so that ΔV < ΔV

.

MAX

Switching frequency is determined by the selection of the

frequency-setting resistor, R . Figure 24 and Equation 57

T

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

are provided to assist in selecting the correct value for R .

T

[

]

10.61 – (1.035 ⋅ log(f ))

(EQ. 57)

S

R

= 10

T

1k

100

10

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see “Interleaving” on

page 11 and Equation 3), a voltage develops across the bulk

capacitor ESR equal to I

(ESR). Thus, once the output

C,PP

capacitors are selected, the maximum allowable ripple

voltage, V , determines the lower limit on the

P-P(MAX)

inductance.

60k

100k

SWITCHING FREQUENCY (Hz)

1M

2M

⎛

⎝

⎞

V

⋅

V

– N ⋅ V

IN

OUT

⎠

(EQ. 54)

L

-------------------------------------------------------------------

≥ ESR ⋅

f

⋅ V ⋅ V

IN P – P(MAX)

FIGURE 24. R vs SWITCHING FREQUENCY

S

T

FN9278.2

April 7, 2008

30

ISL6323

Input Capacitor Selection

0.3

0.2

0.1

0

I

= 0

I

= 0.5 I

O

L(P-P)

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

= 0.25 I

= 0.75 I

O

L(P-P)

O

L(P-P)

0.3

I

= 0

= 0.25 I

I

= 0.5 I

O

L(P-P)

= 0.75 I

O

0.2

0.1

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O

IN/

FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 3-PHASE CONVERTER

Low capacitance, high-frequency ceramic capacitors are

needed in addition to the input bulk capacitors to suppress

leading and falling edge voltage spikes. The spikes result from

the high current slew rate produced by the upper MOSFET

turn on and off. Select low ESL ceramic capacitors and place

one as close as possible to each upper MOSFET drain to

minimize board parasitics and maximize suppression.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O/ IN

FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT

vs DUTY CYCLE FOR 4-PHASE CONVERTER

For a four-phase design, use Figure 25 to determine the

input-capacitor RMS current requirement set by the duty

0.3

0.2

0.1

cycle, maximum sustained output current (I ), and the ratio

O

of the peak-to-peak inductor current (I

) to I . Select a

L(P-P)

O

bulk capacitor with a ripple current rating which will minimize

the total number of input capacitors required to support the

RMS current calculated.

The voltage rating of the capacitors should also be at least

1.25x greater than the maximum input voltage. Figures 26

and 27 provide the same input RMS current information for

three-phase and two-phase designs respectively. Use the

same approach for selecting the bulk capacitor type and

number.

I

= 0

L(P-P)

= 0.5 I

O

= 0.75 I

O

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

IN/

O

FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9278.2

April 7, 2008

31

ISL6323

they belong to a high-impedance circuit loop, sensitive to EMI

pick-up.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which

the current transitions from one device to another causes

voltage spikes across the interconnecting impedances and

parasitic circuit elements. These voltage spikes can degrade

efficiency, radiate noise into the circuit and lead to device

overvoltage stress. Careful component selection, layout, and

placement minimizes these voltage spikes. Consider, as an

example, the turnoff transition of the upper PWM MOSFET.

Prior to turnoff, the upper MOSFET was carrying channel

current. During the turn-off, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET. Any

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful component

selection, tight layout of the critical components, and short, wide

circuit traces minimize the magnitude of voltage spikes.

A multi-layer printed circuit board is recommended. Figure 27

shows the connections of the critical components for the

converter. Note that capacitors C and C

could each

IN OUT

represent numerous physical capacitors. Dedicate one solid

layer, usually the one underneath the component side of the

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from the

PHASE terminal to output inductors short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring.

Routing UGATE, LGATE, and PHASE Traces

There are two sets of critical components in a DC/DC converter

using a ISL6323 controller. The power components are the

most critical because they switch large amounts of energy. Next

are small signal components that connect to sensitive nodes or

supply critical bypassing current and signal coupling.

Great attention should be paid to routing the UGATE, LGATE,

and PHASE traces since they drive the power train MOSFETs

using short, high current pulses. It is important to size them as

large and as short as possible to reduce their overall

impedance and inductance. They should be sized to carry at

least one ampere of current (0.02” to 0.05”). Going between

layers with vias should also be avoided, but if so, use two vias

for interconnection when possible.

The power components should be placed first, which include

the MOSFETs, input and output capacitors, and the inductors. It

is important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each.

Symmetrical layout allows heat to be dissipated equally

across all power trains. Equidistant placement of the controller

to the CORE and NB power trains it controls through the

integrated drivers helps keep the gate drive traces equally

short, resulting in equal trace impedances and similar drive

capability of all sets of MOSFETs.

Extra care should be given to the LGATE traces in particular

since keeping their impedance and inductance low helps to

significantly reduce the possibility of shoot-through. It is also

important to route each channels UGATE and PHASE traces

in as close proximity as possible to reduce their inductances.

Current Sense Component Placement and Trace

Routing

When placing the MOSFETs try to keep the source of the upper

FETs and the drain of the lower FETs as close as thermally

One of the most critical aspects of the ISL6323 regulator

layout is the placement of the inductor DCR current sense

components and traces. The RC current sense components

must be placed as close to their respective ISEN+ and

ISEN- pins on the ISL6323 as possible.

possible. Input high-frequency capacitors, C , should be

HF

placed close to the drain of the upper FETs and the source of

the lower FETs. Input bulk capacitors, CBULK, case size

typically limits following the same rule as the high-frequency

input capacitors. Place the input bulk capacitors as close to the

drain of the upper FETs as possible and minimize the distance

to the source of the lower FETs.

The sense traces that connect the RC sense components to

each side of the output inductors should be routed on the

bottom of the board, away from the noisy switching

components located on the top of the board. These traces

should be routed side by side, and they should be very thin

traces. It’s important to route these traces as far away from

any other noisy traces or planes as possible. These traces

should pick up as little noise as possible.

Locate the output inductors and output capacitors between the

MOSFETs and the load. The high-frequency output decoupling

capacitors (ceramic) should be placed as close as practicable

to the decoupling target, making use of the shortest connection

paths to any internal planes, such as vias to GND next or on the

capacitor solder pad.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal GND

pad of the ISL6323 to the ground plane with multiple vias is

recommended. This heat spreading allows the part to achieve

its full thermal potential. It is also recommended that the

controller be placed in a direct path of airflow if possible to help

thermally manage the part.

The critical small components include the bypass capacitors

(C

) for VCC and PVCC, and many of the components

FILTER

surrounding the controller including the feedback network and

current sense components. Locate the VCC/PVCC bypass

capacitors as close to the ISL6323 as possible. It is especially

important to locate the components associated with the

feedback circuit close to their respective controller pins, since

FN9278.2

April 7, 2008

32

ISL6323

R

FB

C

2

+12V

C

R

C

R

C

3_2

IN

FB

C

VSEN

BOOT

C

BOOT

COMP

ISEN3+

ISEN3-

PWM3

C

IN

C

BOOT1

R

BOOT1

3

3_1

UGATE1

PHASE1

UGATE1

PHASE1

LGATE1

R

C

APA

R

1_1

APA

C

LGATE1

PGND

1

PWM1

APA

DVC

R

1_2

ISEN1-

ISEN1+

+12V

ISL6614

+12V

V_CORE

+5V

C

+12V

PVCC1_2

VCC

C

FILTER

IN

BOOT2

PVCC

VCC

OFS

C

IN

C

BOOT

C

BOOT

C

FILTER

BOOT2

C

BULK

HF

R

OFS

R

UGATE2

PHASE2

GND

UGATE2

FS

CPU

LOAD

PHASE2

LGATE2

FS

PWM2

C

R

4

4_1

C

2_1

2

LGATE2

R

SET

RSET

R

4_2

R

2_2

VFIXEN

SEL

ISEN2-

ISEN2+

SVD

SVC

VID4

RGND

NC

VID5

PWROK

VDDPWRGD

ISEN4+

ISEN4-

GND

PWM4

+12V

ISL6323

+12V

KEY

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

PVCC_NB

R

EN1

EN2

C

FILTER

C

IN

EN

OFF

BOOT_NB

ON

BOOT_NB

UGATE_NB

V_NB

PHASE_NB

LGATE_NB

C

BULK

C

R

HF

1_NB

C

1_NB

RED COMPONENTS:

LOCATE CLOSE TO IC TO

MINIMIZE CONNECTION PATH

R

2_NB

NB

LOAD

ISEN_NB-

ISEN_NB+

RGND_NB

BLUE COMPONENTS:

COMP_NB

FB_NB

LOCATE NEAR LOAD

(MINIMIZE CONNECTION PATH)

R

C_NB

C

C_NB

MAGENTA COMPONENTS:

LOCATE CLOSE TO SWITCHING TRANSISTORS

(MINIMIZE CONNECTION PATH)

R

FB_NB

FIGURE 28. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9278.2

April 7, 2008

33

ISL6323

Package Outline Drawing

L48.7x7

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

4X

5.5

7.00

A

44X

6

0.50

B

PIN #1 INDEX AREA

37

48

6

1

36

PIN 1

INDEX AREA

4. 30 ± 0 . 15

12

25

(4X)

0.15

13

24

0.10 M C A B

48X 0 . 40± 0 . 1

TOP VIEW

4

0.23 +0.07 / -0.05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

BASE PLANE

( 6 . 80 TYP )

SEATING PLANE

0.08 C

(

4 . 30 )

SIDE VIEW

( 44X 0 . 5 )

0 . 2 REF

5

C

( 48X 0 . 23 )

( 48X 0 . 60 )

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN9278.2

April 7, 2008

34


型号：	ISL6323IRZ
厂家：	Intersil
描述：	Hybrid SVI/PVI 混合SVI / PVI 开关
文件：	总34页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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