ISL6324 [RENESAS]

Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI;
ISL6324
型号: ISL6324
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI

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DATASHEET  
2
ISL6324 Hybrid SVI/PVI with I C  
FN6518  
Rev 3.00  
April 9, 2015  
Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI  
The ISL6324 dual PWM controller delivers high efficiency  
and tight regulation from two synchronous buck DC/DC  
Features  
• Processor Core Voltage Via Integrated Multiphase Power  
Conversion  
converters. The ISL6324 supports hybrid power control of  
AMD processors which operate from either a 6-bit parallel  
VID interface (PVI) or a serial VID interface (SVI). The dual  
output ISL6324 features a multiphase controller to support  
uniplane VDD core voltage and a single phase controller to  
power the Northbridge (VDDNB) in SVI mode. Only the  
multiphase controller is active in PVI mode to support  
uniplane VDD only processors.  
• Configuration Flexibility  
- 2-Phase Operation with Internal Drivers  
- 3- or 4-Phase Operation with External PWM Drivers  
• Serial VID Interface Inputs  
- Two Wire, Clock and Data, Bus  
- Conforms to AMD SVI Specifications  
A precision uniplane core voltage regulation system is provided  
by a 2- to 4-phase PWM voltage regulator (VR) controller. The  
integration of two power MOSFET drivers, adding flexibility in  
layout, reduce the number of external components in the  
multiphase section. A single phase PWM controller with  
integrated driver provides a second precision voltage regulation  
system for the North Bridge portion of the processor. This  
monolithic, dual controller with integrated driver solution  
provides a cost and space saving power management solution.  
• Parallel VID Interface Inputs  
- 6-bit VID input  
- 0.775V to 1.55V in 25mV Steps  
- 0.375V to 0.7625V in 12.5mV Steps  
• Precision Core Voltage Regulation  
- Differential Remote Voltage Sensing  
- ±0.5% System Accuracy Over-Temperature  
- Adjustable Reference-Voltage Offset  
For applications which benefit from load line programming to  
reduce bulk output capacitors, the ISL6324 features output  
voltage droop. The multiphase portion also includes advanced  
control loop features for optimal transient response to load  
application and removal. One of these features is highly  
accurate, fully differential, continuous DCR current sensing for  
load line programming and channel current-balance. Dual  
edge modulation is another unique feature, allowing for  
quicker initial response to high di/dt load transients. The  
• Optimal Processor Core Voltage Transient Response  
- Adaptive Phase Alignment (APA)  
- Active Pulse Positioning Modulation  
2
• I C bus for Voltage Margining Offset  
• Fully Differential, Continuous DCR Current Sensing  
- Accurate Load Line Programming  
- Precision Channel Current Balancing  
2
• Variable Gate Drive Bias: 5V to 12V  
• Overcurrent Protection  
ISL6324 incorporates an I C bus™ that allows independent  
programmable output voltage offset for both Core and  
2
Northbridge. The I C bus can also be used to set the  
• Multi-tiered Overvoltage Protection  
• Selectable Switching Frequency up to 1MHz  
PGOOD and OVP levels.  
• Simultaneous Digital Soft-Start of Both Outputs  
Ordering Information  
• Processor NorthBridge Voltage Via Single Phase Power  
Conversion  
PART  
NUMBER  
(Note)  
PART  
MARKING  
TEMP.  
(°C)  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
• Precision Voltage Regulation  
ISL6324CRZ* ISL6324 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7  
ISL6324IRZ* ISL6324 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7  
- Differential Remote Voltage Sensing  
- ±0.5% System Accuracy Over-Temperature  
2
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on  
reel specifications.  
• I Cbus for Voltage Margining Offset  
• Serial VID Interface Inputs  
- Two Wire, Clock and Data, Bus  
- Conforms to AMD SVI Specifications  
NOTE: These Intersil Pb-free plastic packaged products employ  
special Pb-free material sets, molding compounds/die attach  
materials, and 100% matte tin plate plus anneal (e3 termination  
finish, which is RoHS compliant and compatible with both SnPb and  
Pb-free soldering operations). Intersil Pb-free products are MSL  
classified at Pb-free peak reflow temperatures that meet or exceed  
the Pb-free requirements of IPC/JEDEC J STD-020.  
• Overcurrent Protection  
• Continuous DCR Current Sensing  
• Variable Gate Drive Bias: 5V to 12V  
• Simultaneous Digital Soft-Start of Both Outputs  
• Selectable Switching Frequency up to 1MHz  
• Pb-Free (RoHS Compliant)  
FN6518 Rev 3.00  
April 9, 2015  
Page 1 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Pinout  
ISL6324 HYBRID SVI AND PVI  
(48 LD QFN)  
TOP VIEW  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
36  
35  
34  
33  
FB_NB  
ISEN_NB+  
SDA  
PWM4  
PWM3  
3
PWROK  
PHASE1  
4
VID0/VFIXEN  
VID1/SEL  
VID2/SVD  
5
32 UGATE1  
49  
GND  
6
31  
30  
29  
BOOT1  
7
VID3/SVC  
VID4  
LGATE1  
PVCCI_2  
8
VID5  
9
28 LGATE2  
BOOT2  
VCC  
10  
27  
26 UGATE2  
PHASE2  
25  
FS 11  
RGND  
12  
13 14 15 16 17 18 19 20 21 22 23 24  
FN6518 Rev 3.00  
April 9, 2015  
Page 2 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Functional Pin Description  
PIN NUMBER  
SYMBOL  
DESCRIPTION  
1, 48  
FB_NB and COMP_NB These pins are the internal error amplifier inverting input and output respectively of the NB VR  
controller. FB_NB, VDIFF_NB, and COMP_NB are tied together through external R-C networks to  
compensate the regulator.  
2, 47  
ISEN_NB+, ISEN_NB1- These pins are used for differentially sensing the North Bridge output current. The sensed current is  
used for protection and load line regulation if droop is enabled.  
Connect ISEN_NB- to the node between the RC sense element surrounding the inductor. Tie the  
ISEN_NB+ pin to the VNB side of the sense capacitor.  
2
3
4
SDA  
Connect this pin to the bidirectional data line of the I C bus, which is a logic level input/output signal.  
2
All I C data is sent over this line, including the address of the device the bus is trying to communicate  
with, and what functions the device should perform.  
VID0/VFIXEN  
If VID1 is LO prior to enable [SVI Mode], the pin is functions as the VFIXEN selection input from the  
AMD processor for determining SVI mode versus VFIX mode of operation.  
If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has an internal  
30µA pull-down current applied to it at all times.  
5
VID1/SEL  
This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6324.  
If the pin is LO prior to enable, the ISL6324 is in SVI mode and the dual purpose pins [VID0/VFIXEN,  
VID2/SVC, VID3/SVD] use their SVI mode related functions. If the pin held HI prior to enable, the  
ISL6324 is in PVI mode and dual purpose pins use their VIDx related functions to decode the correct  
DAC code.  
6
7
VID2/SVD  
VID3/SVC  
VID4, VID5  
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional signal to and from  
the master device on AMD processor. If VID1 is HI prior to enable [PVI Mode], this pin is used to  
decode the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-  
down current applied to it. There is no pull-down current in SVI mode.  
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the AMD processor.  
If VID1 is HI prior to enable [PVI Mode], the ISL6324 is in PVI mode and this pin is used to decode  
the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-down  
current applied to it. There is no pull-down current in SVI mode.  
8, 9  
These pins are active only when the ISL6324 is in PVI mode. When VID1 is HI prior to enable, the  
ISL6324 decodes the programmed DAC voltage required by the AMD processor. These pins have an  
internal 30µA pull-down current applied to them at all times.  
10  
11  
VCC  
FS  
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and  
decouple using a quality 0.1µF ceramic capacitor.  
A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of both  
controllers. Refer to Equation 1 for proper resistor calculation.  
10.61 1.035logf   
s
(EQ. 1)  
R
= 10  
T
With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from FS to VCC,  
Droop is disabled.  
12, 13  
RGND, VSEN  
VSEN and RGND are inputs to the core voltage regulator (VR) controller precision differential remote-  
sense amplifier and should be connected to the sense pins of the remote processor core(s),  
VDDFB[H,L].  
2
14  
15  
SCL  
DVC  
Connect this pin to the clock signal for the I C bus, which is a logic level input signal. The clock signal  
2
tells the controller when data is available on the I C bus.  
The DVC pin is a buffered version of the reference to the error amplifier. A series resistor and  
capacitor between the DVC pin and FB pin smooth the voltage transition during VID-on-the-fly  
operations.  
16  
17, 18  
19  
RSET  
FB, COMP  
APA  
Connect this pin to the VCC pin through a resistor (RSET) to set the effective value of the internal  
RISEN current sense resistors. The values of the RSET resistor should be no less than 20kand no  
more than 80k. A 0.1µF capacitor should be placed in parallel to the RSET resistor.  
These pins are the internal error amplifier inverting input and output respectively of the core VR  
controller. FB, VSEN and COMP are tied together through external R-C networks to compensate the  
regulator.  
Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A 100µA current  
flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive  
Phase Alignment circuitry can be set.  
FN6518 Rev 3.00  
April 9, 2015  
Page 3 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Functional Pin Description (Continued)  
PIN NUMBER  
SYMBOL  
DESCRIPTION  
20, 21, 22, 23,  
43, 44, 45, 46  
ISEN1+, ISEN1-,  
ISEN2+, ISEN2-,  
ISEN3-, ISEN3+,  
ISEN4-, ISEN4+  
These pins are used for differentially sensing the corresponding channel output currents. The sensed  
currents are used for channel balancing, protection, and core load line regulation.  
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense elements  
surrounding the inductor of their respective channel. Tie the ISEN+ pins to the VCORE side of their  
corresponding channel’s sense capacitor.  
24  
EN  
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held  
low, this pin disables both CORE and NB controller operation. Pulled high, the pin enables both  
controllers for operation.  
When the EN pin is pulled high, the ISL6324 will be placed in either SVI or PVI mode. The mode is  
determined by the latched value of VID1 on the rising edge of the EN signal.  
A third function of this pin is to provide driver bias monitor for external drivers. A resistor divider with  
the center tap connected to this pin from the drive bias supply prevents enabling the controller before  
insufficient bias is provided to external driver. The resistors should be selected such that when the  
POR-trip point of the external driver is reached, the voltage at this pin meets the above mentioned  
threshold level.  
25, 33  
26, 32  
PHASE2 and PHASE1 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return  
path for the upper MOSFET drives.  
UGATE2 and UGATE1 Connect these pins to the corresponding upper MOSFET gates. These pins are used to control the  
upper MOSFETs and are monitored for shoot-through prevention purposes. Maximum individual  
channel duty cycle is limited to 93.3%.  
27, 31  
BOOT2 and BOOT1  
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins  
to appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the  
PVCC1_2 pin provide the necessary bootstrap charge.  
28, 30  
29  
LGATE2 and LGATE1 These pins are used to control the lower MOSFETs. Connect these pins to the corresponding lower  
MOSFETs’ gates.  
PVCC1_2  
The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to any voltage  
from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality  
1.0µF ceramic capacitor.  
34  
PWROK  
System wide Power-Good signal. If this pin is low, the two SVI bits are decoded to determine the  
“metal VID”. When the pin is high, the SVI is actively running its protocol.  
35, 36  
PWM3 and PWM4  
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver IC if  
3- or 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to  
disable them and configure the core VR controller for 2-phase or 3-phase operation.  
37  
38  
VDDPWRGD  
PHASE_NB  
During normal operation this pin indicates whether both output voltages are within specified  
overvoltage and undervoltage limits. If either output voltage exceeds these limits or a reset event  
occurs (such as an overcurrent event), the pin is pulled low. This pin is always low prior to the end of  
soft-start.  
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return path for the  
upper MOSFET drive. This pin is used to monitor the voltage drop across the upper MOSFET for  
overcurrent protection.  
39  
40  
UGATE_NB  
BOOT_NB  
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled  
gate drive for the upper MOSFET and is monitored for shoot-through prevention purposes.  
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to  
appropriately chosen external bootstrap capacitor. The internal bootstrap diode connected to the  
PVCC_NB pin provides the necessary bootstrap charge.  
41  
42  
49  
LGATE_NB  
PVCC_NB  
GND  
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate  
drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection  
circuitry to determine when the lower MOSFET has turned off.  
The power supply pin for the internal MOSFET driver for the Northbridge controller. Connect this pin  
to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this  
pin with a quality 1.0µF ceramic capacitor.  
GND is the bias and reference ground for the IC. The GND connection for the ISL6324 is through the  
thermal pad on the bottom of the package.  
FN6518 Rev 3.00  
April 9, 2015  
Page 4 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Integrated Driver Block Diagram  
PVCC  
BOOT  
UGATE  
PHASE  
PWM  
20k  
SHOOT-  
THROUGH  
PROTECTION  
SOFT-START  
AND  
GATE  
CONTROL  
LOGIC  
FAULT LOGIC  
10k  
LGATE  
FN6518 Rev 3.00  
April 9, 2015  
Page 5 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Controller Block Diagram  
FB_NB  
COMP_NB  
NB_OVP  
SCL  
SDA  
CORE_OVP  
DAC_OFS  
2
I C  
LGATE_NB  
BOOT_NB  
E/A  
MOSFET  
DRIVER  
ISEN_NB+  
ISEN_NB-  
UV  
LOGIC  
OV  
LOGIC  
CURRENT  
SENSE  
NB_REF  
UGATE_NB  
PHASE_NB  
RAMP  
NB_CS  
VDDPWRGD  
APA  
EN_12V  
PVCC_NB  
EN  
APA  
NB  
FAULT  
LOGIC  
ENABLE  
LOGIC  
COMP  
VCC  
POWER-ON  
RESET  
VDDPWRGD_MOD  
PVCC1_2  
SOFT-START  
AND  
FB  
FAULT LOGIC  
E/A  
DVC  
2X  
BOOT1  
RGND  
DROOP  
UGATE1  
CONTROL  
MOSFET  
DRIVER  
LOAD APPLY  
TRANSIENT  
ENHANCEMENT  
PHASE1  
LGATE1  
PWROK  
VID0/VFIXEN  
VID1/SEL  
VID2/SVD  
VID3/SVC  
VID4  
SVI  
SLAVE  
BUS  
AND  
PVI  
CLOCK AND  
TRIANGLE WAVE  
GENERATOR  
DAC_OFS  
FS  
DAC  
VID5  
PWM1  
NB_REF  
BOOT2  
OV  
LOGIC  
PWM2  
PWM3  
PWM4  
CORE_OVP  
NB_CS  
UGATE2  
MOSFET  
DRIVER  
VSEN  
RSET  
PHASE2  
LGATE2  
UV  
LOGIC  
OC  
RESISTOR  
MATCHING  
PH3/PH4  
POR  
CH1  
CURRENT  
SENSE  
I_TRIP I_AVG  
ISEN1+  
ISEN1-  
EN_12V  
CHANNEL  
DETECT  
ISEN3-  
ISEN4-  
CH2  
ISEN2+  
ISEN2-  
CURRENT  
SENSE  
CHANNEL  
CURRENT  
BALANCE  
I_AVG  
1
N
PWM3  
ISEN3+  
ISEN3-  
CH3  
PWM3  
PWM4  
SIGNAL  
LOGIC  
CURRENT  
SENSE  
ISEN3-  
ISEN4+  
ISEN4-  
CH4  
CURRENT  
SENSE  
PWM4  
SIGNAL  
LOGIC  
ISEN4-  
GND  
FN6518 Rev 3.00  
April 9, 2015  
Page 6 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Typical Application - SVI Mode  
+12V  
+12V  
FB  
VSEN  
COMP  
ISEN3+  
ISEN3-  
PWM3  
BOOT1  
BOOT1  
UGATE1  
UGATE1  
PHASE1  
PHASE1  
LGATE1  
LGATE1  
PGND  
PWM1  
APA  
DVC  
ISEN1-  
ISEN1+  
+5V  
+12V  
ISL6614  
+12V  
VDD  
+12V  
PVCC1_2  
VCC  
PVCC  
BOOT2  
VCC  
BOOT2  
UGATE2  
PHASE2  
UGATE2  
GND  
FS  
CPU  
LOAD  
PHASE2  
LGATE2  
PWM2  
LGATE2  
RSET  
VFIXEN  
SEL  
SVD  
ISEN2-  
ISEN2+  
SVC  
VID4  
RGND  
NC  
NC  
VID5  
PWROK  
ISEN4+  
ISEN4-  
VDDPWRGD  
GND  
SCL  
SDA  
PWM4  
+12V  
ISL6324  
+12V  
PVCC_NB  
EN  
OFF  
ON  
BOOT_NB  
UGATE_NB  
PHASE_NB  
LGATE_NB  
VDDNB  
NB  
LOAD  
ISEN_NB-  
ISEN_NB+  
COMP_NB  
FB_NB  
FN6518 Rev 3.00  
April 9, 2015  
Page 7 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Typical Application - PVI Mode  
+12V  
+12V  
FB  
VSEN  
COMP  
ISEN3+  
ISEN3-  
PWM3  
BOOT1  
UGATE1  
PHASE1  
BOOT1  
UGATE1  
PHASE1  
LGATE1  
LGATE1  
PWM1  
APA  
DVC  
PGND  
ISEN1-  
ISEN1+  
+5V  
+12V  
ISL6614  
+12V  
VDD  
+12V  
PVCC1_2  
VCC  
PVCC  
BOOT2  
VCC  
BOOT2  
GND  
UGATE2  
PHASE2  
UGATE2  
FS  
CPU  
LOAD  
PHASE2  
LGATE2  
PWM2  
LGATE2  
RSET  
VID0  
VID1/SEL  
VID2  
ISEN2-  
ISEN2+  
VID3  
VID4  
RGND  
VID5  
NC  
PWROK  
ISEN4+  
ISEN4-  
VDDPWRGD  
GND  
SCL  
SDA  
PWM4  
ISL6324  
+12V  
+12V  
NORTH BRIDGE REGULATOR  
DISABLED IN PVI MODE  
PVCC_NB  
EN  
OFF  
ON  
BOOT_NB  
UGATE_NB  
PHASE_NB  
LGATE_NB  
VDDNB  
NB  
LOAD  
ISEN_NB-  
ISEN_NB+  
COMP_NB  
FB_NB  
FN6518 Rev 3.00  
April 9, 2015  
Page 8 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Absolute Maximum Ratings  
Thermal Information  
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V  
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V  
Thermal Resistance  
(°C/W)  
27  
(°C/W)  
2
JA  
JC  
QFN Package (Notes 1, 2) . . . . . . . . . .  
Absolute Boot Voltage (V  
Phase Voltage (V  
). . . . . . . .GND - 0.3V to GND + 36V  
). . . . . . . GND - 0.3V to 24V (PVCC = 12V)  
PHASE  
BOOT  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C  
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C  
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
GND - 8V (<400ns, 20µJ) to 31V (<200ns, V  
= 5V)  
BOOT-PHASE  
Upper Gate Voltage (V  
). . . . V  
UGATE  
- 0.3V to V  
+ 0.3V  
+ 0.3V  
PHASE  
BOOT  
V
- 3.5V (<100ns Pulse Width, 2µJ) to V  
PHASE  
Lower Gate Voltage (V  
BOOT  
) . . . . . . . GND - 0.3V to PVCC + 0.3V  
LGATE  
Recommended Operating Conditions  
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V  
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%  
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%  
Ambient Temperature  
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V  
ISL6324CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C  
ISL6324IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and  
result in failures not covered by warranty.  
NOTES:  
1. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See  
JA  
Tech Brief TB379.  
2. For , the “case temp” location is the center of the exposed metal pad on the package underside.  
JC  
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.  
MIN  
MAX  
PARAMETER  
TEST CONDITIONS  
(Note 3)  
TYP  
(Note 3) UNITS  
BIAS SUPPLIES  
Input Bias Supply Current  
I
I
I
; EN = high  
VCC  
15  
1
22  
30  
3
mA  
mA  
mA  
V
Gate Drive Bias Current - PVCC1_2 Pin  
Gate Drive Bias Current - PVCC_NB Pin  
VCC POR (Power-On Reset) Threshold  
; EN = high  
1.8  
PVCC1_2  
PVCC_NB  
; EN = high  
0.3  
0.9  
2
VCC Rising  
VCC Falling  
PVCC Rising  
PVCC Falling  
4.20  
3.70  
4.20  
3.70  
4.40  
3.90  
4.40  
3.90  
4.55  
4.10  
4.55  
4.10  
V
PVCC POR (Power-On Reset) Threshold  
V
V
PWM MODULATOR  
Oscillator Frequency Accuracy, f  
R
= 100k(±0.1%) to Ground, T = +25°C  
225  
240  
0.08  
250  
270  
275  
300  
1.0  
kHz  
kHz  
SW  
T
A
(Droop Enabled)  
R
= 100k(±0.1%) to VCC, T = +25°C  
T
A
(Droop Disabled)  
Typical Adjustment Range of Switching Frequency (Note 4)  
MHz  
V
Oscillator Ramp Amplitude, V  
Maximum Duty Cycle  
CONTROL THRESHOLDS  
EN Rising Threshold  
EN Hysteresis  
(Note 4)  
(Note 4)  
1.50  
99.5  
P-P  
%
0.80  
70  
0.88  
130  
1.1  
0.92  
190  
V
mV  
V
PWROK Input HIGH Threshold  
PWROK Input LOW Threshold  
VDDPWRGD Sink Current  
0.95  
V
Open drain, V_VDDPWRGD = 400mV  
4
mA  
V
PWM Channel Disable Threshold  
V
, V  
ISEN3- ISEN4-  
4.4  
FN6518 Rev 3.00  
April 9, 2015  
Page 9 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued)  
MIN  
(Note 3)  
MAX  
(Note 3) UNITS  
PARAMETER  
REFERENCE AND DAC  
TEST CONDITIONS  
TYP  
System Accuracy (VDAC > 1.000V)  
System Accuracy (0.600V < VDAC < 1.000V)  
System Accuracy (VDAC < 0.600V)  
DVC Voltage Gain  
-0.6  
-1.0  
-2.0  
0.6  
1.0  
2.0  
%
%
%
V
VDAC = 1V  
2.0  
APA Current Tolerance  
V
= 1V  
90  
100  
108  
µA  
APA  
ERROR AMPLIFIER  
DC Gain  
R
C
C
= 10k to ground, (Note 4)  
96  
20  
dB  
MHz  
V/µs  
V
L
L
L
Gain-Bandwidth Product (Note 4)  
Slew Rate (Note 4)  
= 100pF, R = 10k to ground, (Note 4)  
L
= 100pF, Load = ±400µA, (Note 4)  
8
Maximum Output Voltage  
Minimum Output Voltage  
Load = 1mA  
Load = -1mA  
3.80  
2.2  
4.20  
1.3  
1.6  
4.0  
0.5  
V
SOFT-START RAMP  
Soft-Start Ramp Rate  
3.0  
mV/µs  
PWM OUTPUTS  
PWM Output Voltage LOW Threshold  
PWM Output Voltage HIGH Threshold  
CURRENT SENSING - CORE CONTROLLER  
I
I
= ±500µA  
= ±500µA  
V
V
LOAD  
4.5  
LOAD  
Current Sense Resistance, R  
(Note 4)  
(Internal)  
T
= +25°C  
2400  
77  
ISEN  
A
Sensed Current Tolerance  
ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 77µA  
68  
87  
µA  
CURRENT SENSING - NB CONTROLLER  
Current Sense Resistance, R  
(Note 4)  
(Internal)  
T
= +25°C  
2400  
80  
ISEN_NB  
A
Sensed Current Tolerance  
DROOP CURRENT  
Tolerance  
ISEN_NB = 80µA  
µA  
ISEN1+ = ISEN2+ = ISEN3+ = ISEN4+ = 77µA  
68  
83  
77  
87  
µA  
OVERCURRENT PROTECTION  
Overcurrent Trip Level - Average Channel  
Overcurrent Trip Level - Individual Channel  
Normal Operation  
100  
130  
142  
190  
111  
µA  
µA  
µA  
µA  
Dynamic VID Change (Note 4)  
Normal Operation  
Dynamic VID Change (Note 4)  
POWER-GOOD  
Overvoltage Threshold  
VSEN Rising (Core and North Bridge)  
Bit 6 of I C data = 0  
VDAC  
+225mV  
VDAC + VDAC +  
V
2
250mV  
275mV  
Undervoltage Threshold  
VSEN Falling (Core)  
Bit 6 of I C data = 0  
VDAC -  
325mV  
VDAC -  
300mV  
VDAC -  
275mV  
mV  
mV  
mV  
2
VSEN Falling (North Bridge)  
VDAC -  
310mV  
VDAC -  
275mV  
VDAC -  
245mV  
2
Bit 6 of I C data = 0  
Power-Good Hysteresis  
OVERVOLTAGE PROTECTION  
OVP Trip Level  
50  
2
Bit 7 of I C data = 0, VDAC 1.55V  
1.73  
1.80  
1.84  
V
FN6518 Rev 3.00  
April 9, 2015  
Page 10 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. (Continued)  
MIN  
MAX  
PARAMETER  
TEST CONDITIONS  
(Note 3)  
TYP  
(Note 3) UNITS  
OVP Lower Gate Release Threshold  
350  
400  
mV  
SWITCHING TIME (Note 2) [See “Timing Diagram” on page 12]  
UGATE Rise Time  
t
t
t
t
t
t
V
= 12V, 3nF Load, 10% to 90%  
= 12V, 3nF Load, 10% to 90%  
= 12V, 3nF Load, 90% to 10%  
= 12V, 3nF Load, 90% to 10%  
26  
18  
18  
12  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
RUGATE; PVCC  
LGATE Rise Time  
V
RLGATE; PVCC  
UGATE Fall Time  
V
FUGATE; PVCC  
LGATE Fall Time  
V
FLGATE; PVCC  
UGATE Turn-On Non-overlap  
LGATE Turn-On Non-overlap  
GATE DRIVE RESISTANCE (Note 2)  
Upper Drive Source Resistance  
Upper Drive Sink Resistance  
Lower Drive Source Resistance  
Lower Drive Sink Resistance  
MODE SELECTION  
; V  
= 12V, 3nF Load, Adaptive  
= 12V, 3nF Load, Adaptive  
PDHUGATE PVCC  
; V  
PDHLGATE PVCC  
V
V
V
V
= 12V, 15mA Source Current  
2.0  
PVCC  
PVCC  
PVCC  
PVCC  
= 12V, 15mA Sink Current  
= 12V, 15mA Source Current  
= 12V, 15mA Sink Current  
1.65  
1.25  
0.80  
VID1/SEL Input Low  
EN taken from HI to LO, VDDIO = 1.5V  
EN taken from LO to HI, VDDIO = 1.5V  
0.45  
V
V
VID1/SEL Input High  
1.00  
1.00  
PVI INTERFACE  
VIDx Pull-down  
VDDIO = 1.5V  
VDDIO = 1.5V  
VDDIO = 1.5V  
30  
45  
µA  
V
VIDx Input Low  
0.45  
VIDx Input High  
V
SVI INTERFACE  
SVC, SVD Input LOW (VIL)  
SVC, SVD Input HIGH (VIH)  
Schmitt Trigger Input Hysteresis  
SVD Low Level Output Voltage  
Maximum SVC, SVD Leakage (Note 4)  
0.4  
V
V
1.10  
0.14  
0.35  
±5  
0.55  
V
3mA Sink Current  
0.285  
V
µA  
2
I C bus  
SCL, SDA Input LOW (VIL)  
SCL, SDA Input HIGH (VIH)  
Schmitt Trigger Input Hysteresis  
SDA Low Level Output Voltage  
Maximum SCL, SDA Leakage (Note 4)  
NOTES:  
1.10  
V
V
1.75  
0.18  
0.35  
±5  
0.50  
0.2  
V
3mA Sink Current  
V
µA  
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization  
and are not production tested.  
4. Limits should be considered typical and are not production tested.  
FN6518 Rev 3.00  
April 9, 2015  
Page 11 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Timing Diagram  
t
PDHUGATE  
t
t
RUGATE  
FUGATE  
UGATE  
LGATE  
t
t
FLGATE  
RLGATE  
t
PDHLGATE  
To understand the reduction of ripple current amplitude in the  
multiphase circuit, examine the equation representing an  
individual channel peak-to-peak inductor current.  
Operation  
The ISL6324 utilizes a multiphase architecture to provide a low  
cost, space saving power conversion solution for the processor  
core voltage. The controller also implements a simple single  
phase architecture to provide the Northbridge voltage on the  
same chip.  
V V  
V  
OUT  
IN  
OUT  
(EQ. 2)  
I
= -----------------------------------------------------  
P-P  
Lf  
V
S
IN  
In Equation 2, V and V  
IN  
are the input and output voltages  
OUT  
respectively, L is the single-channel inductor value, and f is  
the switching frequency.  
S
Multiphase Power Conversion  
Microprocessor load current profiles have changed to the point  
that the advantages of multiphase power conversion are  
impossible to ignore. The technical challenges associated with  
producing a single-phase converter that is both cost-effective  
and thermally viable have forced a change to the cost-saving  
approach of multiphase. The ISL6324 controller helps simplify  
implementation by integrating vital functions and requiring  
minimal external components. The “Controller Block Diagram”  
on page 6 provides a top level view of the multiphase power  
conversion using the ISL6324 controller.  
The output capacitors conduct the ripple component of the  
inductor current. In the case of multiphase converters, the  
capacitor current is the sum of the ripple currents from each of  
the individual channels. Compare Equation 2 to the expression  
for the peak-to-peak current after the summation of N  
symmetrically phase-shifted inductor currents in Equation 3.  
Peak-to-peak ripple current decreases by an amount  
proportional to the number of channels. Output voltage ripple is  
a function of capacitance, capacitor equivalent series  
resistance (ESR), and inductor ripple current. Reducing the  
inductor ripple current allows the designer to use fewer or less  
costly output capacitors.  
Interleaving  
The switching of each channel in a multiphase converter is timed  
to be symmetrically out-of-phase with each of the other channels.  
In a 3-phase converter, each channel switches 1/3 cycle after the  
previous channel and 1/3 cycle before the following channel. As a  
result, the 3-phase converter has a combined ripple frequency 3x  
greater than the ripple frequency of any one phase. In addition,  
the peak-to-peak amplitude of the combined inductor currents is  
reduced in proportion to the number of phases (Equations 2 and  
3). Increased ripple frequency and lower ripple amplitude mean  
that the designer can use less per-channel inductance and lower  
total output capacitance for any performance specification.  
V N V  
V  
OUT  
IN  
OUT  
(EQ. 3)  
I
= -----------------------------------------------------------  
CP-P  
Lf  
V
S
IN  
Another benefit of interleaving is to reduce input ripple current.  
Input capacitance is determined in part by the maximum input  
ripple current. Multiphase topologies can improve overall  
system cost and size by lowering input ripple current and  
allowing the designer to reduce the cost of input capacitance.  
The example in Figure 2 illustrates input currents from a 3-  
phase converter combining to reduce the total input ripple  
current.  
Figure 1 illustrates the multiplicative effect on output ripple  
frequency. The 3-channel currents (IL1, IL2, and IL3) combine  
to form the AC ripple current and the DC load current. The  
ripple component has 3x the ripple frequency of each  
The converter depicted in Figure 2 delivers 1.5V to a 36A load  
from a 12V input. The RMS input capacitor current is 5.9A.  
Compare this to a single-phase converter also stepping down  
12V to 1.5V at 36A. The single-phase converter has 11.9A  
RMS  
individual channel current. Each PWM pulse is terminated 1/3  
of a cycle after the PWM pulse of the previous phase. The peak-  
to-peak current for each phase is about 7A, and the DC  
components of the inductor currents combine to feed the load.  
input capacitor current. The single-phase converter must use an  
input capacitor bank with twice the RMS current capacity as the  
equivalent 3-phase converter.  
Figures 26, 27 and 28 in the section entitled “Input Capacitor  
Selection” on page 35 can be used to determine the input  
capacitor RMS current based on load current, duty cycle, and  
the number of channels. They are provided as aids in  
determining the optimal input capacitor solution.  
FN6518 Rev 3.00  
April 9, 2015  
Page 12 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
modulator waveform. As long as the modified V  
COMP  
voltage is  
lower then the modulator waveform voltage, the PWM signal is  
commanded low. The internal MOSFET driver detects the low  
state of the PWM signal and turns off the upper MOSFET and  
turns on the lower synchronous MOSFET. When the modified  
IL1 + IL2 + IL3, 7A/DIV  
IL3, 7A/DIV  
PWM3, 5V/DIV  
V
voltage crosses the modulator ramp, the PWM output  
COMP  
transitions high, turning off the synchronous MOSFET and  
turning on the upper MOSFET. The PWM signal will remain high  
IL2, 7A/DIV  
PWM2, 5V/DIV  
until the modified V  
voltage crosses the modulator ramp  
COMP  
again. When this occurs the PWM signal will transition low  
again.  
IL1, 7A/DIV  
PWM1, 5V/DIV  
During each PWM time interval the PWM signal can only  
transition high once. Once PWM transitions high it can not  
transition high again until the beginning of the next PWM time  
interval. This prevents the occurrence of double PWM pulses  
occurring during a single period.  
1µs/DIV  
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS  
FOR 3-PHASE CONVERTER  
INPUT-CAPACITOR CURRENT, 10A/DIV  
To further improve the transient response, ISL6324 also  
implements Intersil’s proprietary Adaptive Phase Alignment (APA)  
technique, which turns on all phases together under transient  
events with large step current. With both APP and APA control,  
ISL6324 can achieve excellent transient performance and reduce  
the demand on the output capacitors.  
CHANNEL 3  
INPUT CURRENT  
10A/DIV  
Adaptive Phase Alignment (APA)  
CHANNEL 2  
INPUT CURRENT  
10A/DIV  
To further improve the transient response, the ISL6324 also  
implements Intersil’s proprietary Adaptive Phase Alignment  
(APA) technique, which turns on all of the channels together at  
the same time during large current step transient events. As  
Figure 3 shows, the APA circuitry works by monitoring the  
voltage on the APA pin and comparing it to a filtered copy of  
the voltage on the COMP pin. The voltage on the APA pin is a  
copy of the COMP pin voltage that has been negatively offset.  
If the APA pin exceeds the filtered COMP pin voltage an APA  
event occurs and all of the channels are forced on.  
CHANNEL 1  
INPUT CURRENT  
10A/DIV  
1µs/DIV  
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT  
CAPACITOR RMS CURRENT FOR 3-PHASE  
CONVERTER  
Active Pulse Positioning Modulated PWM Operation  
The ISL6324 uses a proprietary Active Pulse Positioning (APP)  
modulation scheme to control the internal PWM signals that  
command each channel’s driver to turn their upper and lower  
MOSFETs on and off. The time interval in which a PWM signal  
can occur is generated by an internal clock, whose cycle time is  
the inverse of the switching frequency set by the resistor between  
the FS pin and ground. The advantage of Intersil’s proprietary  
Active Pulse Positioning (APP) modulator is that the PWM signal  
has the ability to turn on at any point during this PWM time  
interval, and turn off immediately after the PWM signal has  
transitioned high. This is important because it allows the controller  
to quickly respond to output voltage drops associated with current  
load spikes, while avoiding the ring back affects associated with  
other modulation schemes.  
ISL6324 INTERNAL CIRCUIT  
EXTERNAL CIRCUIT  
APA  
-
+
APA  
100µA  
C
R
APA  
APA  
V
APA,TRIP  
-
TO APA  
CIRCUITRY  
LOW  
PASS  
FILTER  
COMP  
ERROR  
AMPLIFIER  
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION  
The PWM output state is driven by the position of the error  
The APA trip level is the amount of DC offset between the  
COMP pin and the APA pin. This is the voltage excursion that  
the APA and COMP pins must have during a transient event to  
activate the Adaptive Phase Alignment circuitry. This APA trip  
amplifier output signal, V  
, minus the current correction  
COMP  
signal relative to the proprietary modulator ramp waveform as  
illustrated in Figure 3. At the beginning of each PWM time  
interval, this modified V  
signal is compared to the internal  
COMP  
level is set through a resistor, R  
, that connects from the  
APA  
FN6518 Rev 3.00  
April 9, 2015  
Page 13 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
APA pin to the COMP pin. A 100µA current flows across R  
into the APA pin to set the APA trip level as described in  
balance. The internal circuitry, shown in Figure 6 represents  
Channel N of an N-Channel converter. This circuitry is repeated  
for each channel in the converter, but may not be active  
depending on how many channels are operating.  
APA  
Equation 4. An APA trip level of 500mV is recommended for  
most applications. A 0.1µF capacitor, C , should also be  
APA  
placed across the R  
resistor to help with noise immunity.  
APA  
Inductor windings have a characteristic distributed resistance  
or DCR (Direct Current Resistance). For simplicity, the inductor  
DCR is considered as a separate lumped quantity, as shown in  
6  
(EQ. 4)  
V
= R  
100 10  
APA  
APATRIP  
PWM Operation  
Figure 6. The channel current I , flowing through the inductor,  
Ln  
passes through the DCR. Equation 5 shows the S-domain  
equivalent voltage, V , across the inductor.  
L
The timing of each core channel is set by the number of active  
channels. Channel detection on the ISEN3- and ISEN4- pins  
selects 2-channel to 4-channel operation for the ISL6324. The  
switching cycle is defined as the time between PWM pulse  
termination signals of each channel. The cycle time of the  
pulse signal is the inverse of the switching frequency set by the  
resistor between the FS pin and ground. The PWM signals  
command the MOSFET driver to turn on/off the channel  
MOSFETs.  
(EQ. 5)  
V s= I  s L + DCR  
L
L
n
A simple R-C network across the inductor (R , R and C)  
1
2
extracts the DCR voltage, as shown in Figure 6. The voltage  
across the sense capacitor, V , can be shown to be  
C
proportional to the channel current I , shown in Equation 6.  
Ln  
For 4-channel operation, the channel firing order is 4-3-2-1:  
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2  
output follows another 1/4 of a cycle after PWM3, and PWM1  
delays another 1/4 of a cycle after PWM2. For 3-channel  
operation, the channel firing order is 3-2-1.  
s L  
-------------  
+ 1  
(EQ. 6)  
(EQ. 7)  
DCR  
-------------------------------------------------------  
V
s=  
K DCR I  
C
L
n
R R   
1
2
-----------------------  
s   
C + 1  
R
+ R  
2
1
Where:  
R
Connecting ISEN4- to VCC selects 3-channel operation and the  
pulse times are spaced in 1/3 cycle increments. If ISEN3- is  
connected to VCC, 2- channel operation is selected and the  
PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.  
2
--------------------  
K =  
R
+ R  
1
2
I
V
IN  
L
n
Continuous Current Sampling  
UGATE(n)  
LGATE(n)  
L
DCR  
V
OUT  
MOSFET  
DRIVER  
In order to realize proper current-balance, the currents in each  
channel are sampled continuously every switching cycle.  
During this time, the current-sense amplifier uses the ISEN  
inputs to reproduce a signal proportional to the inductor  
INDUCTOR  
-
C
OUT  
V (s)  
L
-
V
(s)  
C
C
current, I . This sensed current, I  
, is simply a scaled  
L
SEN  
version of the inductor current.  
R
1
R
2
ISL6324 INTERNAL CIRCUIT  
I
n
PWM  
SAMPLE  
SWITCHING PERIOD  
+
-
ISENn-  
-
I
L
V
(s)  
C
ISENn+  
VCC  
R
ISEN  
I
SEN  
I
SEN  
TO ACTIVE  
CORE CHANNELS  
RSET  
{
R
SET  
TO NORTH BRIDGE  
C
SET  
TIME  
FIGURE 5. INDUCTOR DCR CURRENT SENSING  
CONFIGURATION  
FIGURE 4. CONTINUOUS CURRENT SAMPLING  
If the R-C network components are selected such that the RC  
time constant matches the inductor L/DCR time constant (see  
The ISL6324 supports Inductor DCR current sensing to  
continuously sample each channel’s current for channel-current  
FN6518 Rev 3.00  
April 9, 2015  
Page 14 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Equation 8), then V is equal to the voltage drop across the  
C
DCR multiplied by the ratio of the resistor divider, K. If a  
+
PWM1  
V
COMP  
TO GATE  
CONTROL  
LOGIC  
+
-
resistor divider is not being used, the value for K is 1.  
MODULATOR  
RAMP  
-
.
WAVEFORM  
R
R  
2
FILTER f(s)  
L
1
-------------  
--------------------  
C  
=
(EQ. 8)  
DCR  
R + R  
1 2  
I
I
4
3
2
I
ER  
The capacitor voltage V , is then replicated across the effective  
I
C
AVG  
N  
internal sense resistor, R  
. This develops a current through  
-
ISEN  
+
R
which is proportional to the inductor current. This  
ISEN  
current, I  
I
, is continuously sensed and is then used by the  
SEN  
I
controller for load-line regulation, channel-current balancing,  
1
and overcurrent detection and limiting. Equation 9 shows that  
NOTE: Channel 3 and 4 are optional.  
the proportion between the channel current, I , and the sensed  
L
current, I  
resistance, R  
ISEN  
, is driven by the value of the effective sense  
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-  
BALANCE ADJUSTMENT  
SEN  
, and the DCR of the inductor.  
The resulting cycle average current, I  
, provides a measure  
AVG  
DCR  
(EQ. 9)  
-----------------  
I
= I  
of the total load current demand on the converter during each  
switching cycle. Channel-current balance is achieved by  
comparing the sampled current of each channel to the cycle  
average current, and making the proper adjustment to each  
channel pulse width based on the error. Intersil’s patented  
current balance method is illustrated in Figure 6, with error  
correction for Channel 1 represented. In the figure, the cycle  
SEN  
L
R
ISEN  
The effective internal R  
resistance is important to the  
ISEN  
current sensing process because it sets the gain of the load  
line regulation loop when droop is enabled as well as the gain  
of the channel-current balance loop and the overcurrent trip  
level. The effective internal R  
resistance is user  
ISEN  
programmable and is set through use of the RSET pin. Placing  
a single resistor, R , from the RSET pin to the VCC pin  
average current, I  
, is compared with the Channel 1 sample,  
AVG  
I , to create an error signal I  
.
1
ER  
The filtered error signal modifies the pulse width commanded  
by V to correct any unbalance and force I toward zero.  
SET  
programs the effective internal R  
resistance according to  
ISEN  
Equation 10.  
COMP ER  
The same method for error signal correction is applied to each  
active channel.  
3
400  
---------  
R
=
R  
(EQ. 10)  
ISEN  
SET  
The North Bridge regulator samples the load current in the  
same manner as the Core regulator does. The R resistor  
VID Interface  
SET  
resistors to the  
The ISL6324 supports hybrid power control of AMD processors  
which operate from either a 6-bit parallel VID interface (PVI) or  
a serial VID interface (SVI). The VID1/SEL pin is used to  
command the ISL6324 into either the PVI mode or the SVI  
mode. Whenever the EN pin is held LOW, both the multiphase  
Core and single-phase North Bridge Regulators are disabled  
and the ISL6324 is continuously sampling voltage on the  
VID1/SEL pin. When the EN pin is toggled HIGH, the status of  
the VID1/SEL pin will latch the ISL6324 into either PVI or SVI  
mode. This latching occurs on the rising edge of the EN  
signal.If the VID1/SEL pin is held LOW during the latch, the  
ISL6324 will be placed into SVI mode. If the VID1/SEL pin is  
held HIGH during the latch, the ISL6324 will be placed into PVI  
mode. For the ISL6324 to properly enter into either mode, the  
level on the VID1/SEL pin must be stable no less that 1µs prior  
to the EN signal transitioning from low to high.  
will program all the effective internal R  
same value.  
ISEN  
Channel-Current Balance  
One important benefit of multiphase operation is the thermal  
advantage gained by distributing the dissipated heat over  
multiple devices and greater area. By doing this the designer  
avoids the complexity of driving parallel MOSFETs and the  
expense of using expensive heat sinks and exotic magnetic  
materials.  
In order to realize the thermal advantage, it is important that  
each channel in a multiphase converter be controlled to carry  
about the same amount of current at any load level. To achieve  
this, the currents through each channel must be sampled every  
switching cycle. The sampled currents, I , from each active  
n
channel are summed together and divided by the number of  
active channels.  
6-bit Parallel VID Interface (PVI)  
With the ISL6324 in PVI mode, the single-phase North Bridge  
regulator is disabled. Only the multiphase controller is active in  
PVI mode to support uniplane VDD only processors. Table 1  
shows the 6-bit parallel VID codes and the corresponding  
reference voltage.  
FN6518 Rev 3.00  
April 9, 2015  
Page 15 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
TABLE 1. 6-BIT PARALLEL VID CODES  
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)  
VID5  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
VID4  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
VID3  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
VID2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VREF  
1.5500  
1.5250  
1.5000  
1.4750  
1.4500  
1.4250  
1.4000  
1.3750  
1.3500  
1.3250  
1.3000  
1.2750  
1.2500  
1.2250  
1.2000  
1.1750  
1.1500  
1.1250  
1.1000  
1.0750  
1.0500  
1.0250  
1.0000  
0.9750  
0.9500  
0.9250  
0.9000  
0.8750  
0.8500  
0.8250  
0.8000  
0.7750  
0.7625  
0.7500  
0.7375  
0.7250  
0.7125  
0.7000  
0.6875  
0.6750  
0.6625  
0.6500  
0.6375  
0.6250  
VID5  
1
VID4  
0
VID3  
1
VID2  
1
VID1  
0
VID0  
0
VREF  
0.6125  
0.6000  
0.5875  
0.5750  
0.5625  
0.5500  
0.5375  
0.5250  
0.5125  
0.5000  
0.4875  
0.4750  
0.4625  
0.4500  
0.4375  
0.4250  
0.4125  
0.4000  
0.3875  
0.3750  
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
Serial VID Interface (SVI)  
The on-board Serial VID interface (SVI) circuitry allows the  
processor to directly drive the core voltage and Northbridge  
voltage reference level within the ISL6324. The SVC and SVD  
states are decoded with direction from the PWROK and VFIXEN  
inputs as described in the following sections. The ISL6324 uses a  
digital to analog converter (DAC) to generate a reference voltage  
based on the decoded SVI value. See Figure 7 for a simple SVI  
interface timing diagram.  
FN6518 Rev 3.00  
April 9, 2015  
Page 16 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
1
2
3
4
5
6
7
8
9
10  
11  
12  
VCC  
SVC  
SVD  
ENABLE  
PWROK  
VDD AND VDDNB  
VDDPWRGD  
V_SVI  
V_SVI  
METAL_VID  
METAL_VID  
VFIXEN  
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP  
PRE-PWROK METAL VID  
VFIX MODE  
Typical motherboard start-up occurs with the VFIXEN input  
low. The controller decodes the SVC and SVD inputs to  
determine the Pre-PWROK metal VID setting. Once the POR  
circuitry is satisfied, the ISL6324 begins decoding the inputs  
per Table 2. Once the EN input exceeds the rising enable  
threshold, the ISL6324 saves the Pre-PWROK metal VID value  
in an on-board holding register and passes this target to the  
internal DAC circuitry.  
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed  
external to the controller through jumpers to either GND or  
VDDIO. These inputs are not expected to change, but the  
ISL6324 is designed to support the potential change of state of  
these inputs. If VFIXEN is high, the IC decodes the SVC and  
SVD states per Table 3.  
Once enabled, the ISL6324 begins to soft-start both VDD and  
VDDNB planes to the programmed VFIX level. The internal  
soft-start circuitry slowly stair steps the reference up to the  
target value and this results in a controlled ramp of the power  
planes. Once soft-start has ended and both output planes are  
within regulation limits, the VDDPWRGD pin transitions high. If  
the EN input falls below the enable falling threshold, then the  
controller ramps both VDD and VDDNB down to near zero.  
TABLE 2. PRE-PWROK METAL VID CODES  
SVC  
SVD  
OUTPUT VOLTAGE (V)  
0
0
1
1
0
1
0
1
1.1  
1.0  
0.9  
0.8  
TABLE 3. VFIXEN VID CODES  
SVC  
SVD  
OUTPUT VOLTAGE (V)  
The Pre-PWROK metal VID code is decoded and latched on  
the rising edge of the enable signal. Once enabled, the  
ISL6324 passes the Pre-PWROK metal VID code on to internal  
DAC circuitry. The internal DAC circuitry begins to ramp both  
the VDD and VDDNB planes to the decoded Pre-PWROK  
metal VID output level. The digital soft-start circuitry actually  
stair steps the internal reference to the target gradually over a  
fix interval. The controlled ramp of both output voltage planes  
reduces in-rush current during the soft-start interval. At the end  
of the soft-start interval, the VDDPWRGD output transitions  
high indicating both output planes are within regulation limits.  
0
0
1
1
0
1
0
1
1.4  
1.2  
1.0  
0.8  
SVI MODE  
Once the controller has successfully soft-started and  
VDDPWRGD transitions high, the Northbridge SVI interface  
can assert PWROK to signal the ISL6324 to prepare for SVI  
commands. The controller actively monitors the SVI interface  
for set VID commands to move the plane voltages to start-up  
VID values. Details of the SVI Bus protocol are provided in the  
AMD Design Guide for Voltage Regulator Controllers  
Accepting Serial VID Codes specification.  
If the EN input falls below the enable falling threshold, the  
ISL6324 ramps the internal reference voltage down to near  
zero. The VDDPWRGD de-asserts with the loss of enable. The  
VDD and VDDNB planes will linearly decrease to near zero.  
FN6518 Rev 3.00  
April 9, 2015  
Page 17 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Once the set VID command is received, the ISL6324 decodes  
the information to determine which plane and the VID target  
required. See Table 4. The internal DAC circuitry steps the  
required output plane voltage to the new VID level. During this  
time one or both of the planes could be targeted. In the event  
the core voltage plane, VDD, is commanded to power off by  
serial VID commands, the VDDPWRGD signal remains  
asserted. The Northbridge voltage plane must remain active  
during this time.  
If the PWROK input is de-asserted, then the controller steps  
both VDD and VDDNB planes back to the stored Pre-PWROK  
metal VID level in the holding register from initial soft-start. No  
attempt is made to read the SVC and SVD inputs during this  
time. If PWROK is reasserted, then the on-board SVI interface  
waits for a set VID command.  
If VDDPWRGD deasserts during normal operation, both  
voltage planes are powered down in a controlled fashion. The  
internal DAC circuitry stair steps both outputs down to near  
zero.  
TABLE 4. SERIAL VID CODES  
VOLTAGE (V) SVID[6:0]  
1.1500 100_0000b  
SVID[6:0]  
000_0000b  
000_0001b  
000_0010b  
000_0011b  
000_0100b  
000_0101b  
000_0110b  
000_0111b  
000_1000b  
000_1001b  
000_1010b  
000_1011b  
000_1100b  
000_1101b  
000_1110b  
000_1111b  
001_0000b  
001_0001b  
001_0010b  
001_0011b  
001_0100b  
001_0101b  
001_0110b  
001_0111b  
001_1000b  
001_1001b  
001_1010b  
001_1011b  
001_1100b  
001_1101b  
001_1110b  
001_1111b  
VOLTAGE (V)  
1.5500  
1.5375  
1.5250  
1.5125  
1.5000  
1.4875  
1.4750  
1.4625  
1.4500  
1.4375  
1.4250  
1.4125  
1.4000  
1.3875  
1.3750  
1.3625  
1.3500  
1.3375  
1.3250  
1.3125  
1.3000  
1.2875  
1.2750  
1.2625  
1.2500  
1.2375  
1.2250  
1.2125  
1.2000  
1.1875  
1.1750  
1.1625  
SVID[6:0]  
010_0000b  
010_0001b  
010_0010b  
010_0011b  
010_0100b  
010_0101b  
010_0110b  
010_0111b  
010_1000b  
010_1001b  
010_1010b  
010_1011b  
010_1100b  
010_1101b  
010_1110b  
010_1111b  
011_0000b  
011_0001b  
011_0010b  
011_0011b  
011_0100b  
011_0101b  
011_0110b  
011_0111b  
011_1000b  
011_1001b  
011_1010b  
011_1011b  
011_1100b  
011_1101b  
011_1110b  
011_1111b  
VOLTAGE (V)  
0.7500  
0.7375  
0.7250  
0.7125  
0.7000  
0.6875  
0.6750  
0.6625  
0.6500  
0.6375  
0.6250  
0.6125  
0.6000  
0.5875  
0.5750  
0.5625  
0.5500  
0.5375  
0.5250  
0.5125  
0.5000  
0.4875*  
0.4750*  
0.4625*  
0.4500*  
0.4375*  
0.4250*  
0.4125*  
0.4000*  
0.3875*  
0.3750*  
0.3625*  
SVID[6:0]  
110_0000b  
110_0001b  
110_0010b  
110_0011b  
110_0100b  
110_0101b  
110_0110b  
110_0111b  
110_1000b  
110_1001b  
110_1010b  
110_1011b  
110_1100b  
110_1101b  
110_1110b  
110_1111b  
111_0000b  
111_0001b  
111_0010b  
111_0011b  
111_0100b  
111_0101b  
111_0110b  
111_0111b  
111_1000b  
111_1001b  
111_1010b  
111_1011b  
111_1100b  
111_1101b  
111_1110b  
111_1111b  
VOLTAGE (V)  
0.3500*  
0.3375*  
0.3250*  
0.3125*  
0.3000*  
0.2875*  
0.2750*  
0.2625*  
0.2500*  
0.2375*  
0.2250*  
0.2125*  
0.2000*  
0.1875*  
0.1750*  
0.1625*  
0.1500*  
0.1375*  
0.1250*  
0.1125*  
0.1000*  
0.0875*  
0.0750*  
0.0625*  
0.0500*  
0.0375*  
0.0250*  
0.0125*  
OFF  
1.1375  
1.1250  
1.1125  
1.1000  
1.0875  
1.0750  
1.0625  
1.0500  
1.0375  
1.0250  
1.0125  
1.0000  
0.9875  
0.9750  
0.9625  
0.9500  
0.9375  
0.9250  
0.9125  
0.9000  
0.8875  
0.8750  
0.8625  
0.8500  
0.8375  
0.8250  
0.8125  
0.8000  
0.7875  
0.7750  
0.7625  
100_0001b  
100_0010b  
100_0011b  
100_0100b  
100_0101b  
100_0110b  
100_0111b  
100_1000b  
100_1001b  
100_1010b  
100_1011b  
100_1100b  
100_1101b  
100_1110b  
100_1111b  
101_0000b  
101_0001b  
101_0010b  
101_0011b  
101_0100b  
101_0101b  
101_0110b  
101_0111b  
101_1000b  
101_1001b  
101_1010b  
101_1011b  
101_1100b  
101_1101b  
101_1110b  
101_1111b  
OFF  
OFF  
OFF  
NOTE: * Indicates a VID not required for AMD Family 10h processors.  
FN6518 Rev 3.00  
April 9, 2015  
Page 18 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
The magnitude of the spike is dictated by the ESR and ESL of  
the output capacitors selected. By positioning the no-load  
voltage level near the upper specification limit, a larger  
negative spike can be sustained without crossing the lower  
limit. By adding a well controlled output impedance, the output  
voltage under load can effectively be level shifted down so that  
a larger positive spike can be sustained without crossing the  
upper specification limit.  
Voltage Regulation  
The integrating compensation network shown in Figure 8  
insures that the steady-state error in the output voltage is  
limited only to the error in the reference voltage, remote-sense  
and error amplifiers. Intersil specifies the guaranteed tolerance  
of the ISL6324 to include the combined tolerances of each of  
these elements.  
The output of the error amplifier, V  
, is used by the  
COMP  
As shown in Figure 8, with the FS resistor tied to ground, the  
modulator to generate the PWM signals. The PWM signals  
control the timing of the Internal MOSFET drivers and regulate  
the converter output so that the voltage at FB is equal to the  
voltage at REF. This will regulate the output voltage to be equal  
to Equation 11. The internal and external circuitry that controls  
voltage regulation is illustrated in Figure 8.  
average current of all active channels, I  
, flows from FB  
AVG  
through a load-line regulation resistor R . The resulting  
FB  
voltage drop across R is proportional to the output current,  
FB  
effectively creating an output voltage droop with a steady-state  
value defined as in Equation 12:  
V
= I  
R  
AVG FB  
(EQ. 11)  
(EQ. 12)  
DROOP  
V
= V  
V  
REF DROOP  
OUT  
The ISL6324 incorporates differential remote-sense  
The regulated output voltage is reduced by the droop voltage  
amplification in the feedback path. The differential sensing  
removes the voltage error encountered when measuring the  
output voltage relative to the controller ground reference point  
resulting in a more accurate means of sensing output voltage.  
V
. The output voltage as a function of load current is  
DROOP  
shown in Equation 13.  
I
400  
1
OUT  
-------------  
--------- --------------  
V
= V  
DCR   
K R  
FB  
OUT  
REF  
N
3
R
SET  
(EQ. 13)  
EXTERNAL CIRCUIT  
FS  
ISL6324 INTERNAL CIRCUIT  
In Equation 13, V  
is the reference voltage, I  
is the total  
OUT  
REF  
TO  
output current of the converter, K is the DC gain of the RC filter  
across the inductor (K is defined in Equation 7), N is the  
number of active channels, and DCR is the Inductor DCR  
value.  
R
DROOP  
FS  
OSCILLATOR  
CONTROL  
COMP  
C
Dynamic VID  
C
I
AVG  
The AMD processor does not step the output voltage  
commands up or down to the target voltage, but instead  
passes only the target voltage to the ISL6324 through either  
the PVI or SVI interface. The ISL6324 manages the resulting  
VID-on-the-Fly transition in a controlled manner, supervising a  
safe output voltage transition without discontinuity or  
disruption. The ISL6324 begins slewing the DAC at 3.25mV/µs  
until the DAC and target voltage are equal. Thus, the total time  
required for a dynamic VID transition is dependent only on the  
size of the DAC change.  
R
C
FB  
-
V
COMP  
+
ERROR  
AMPLIFIER  
+
V
-
R
FB  
DROOP  
+
VID  
DAC  
VSEN  
RGND  
To further improve dynamic VID performance, ISL6324 also  
implements a proprietary DAC smoothing feature. The external  
series RC components connected between DVC and FB limit  
any stair-stepping of the output voltage during a VID-on-the-fly  
transition.  
+
+
V
OUT  
-
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE  
REGULATION  
Compensating Dynamic VID Transitions  
Load-Line (Droop) Regulation  
During a VID transition, the resulting change in voltage on the  
FB pin and the COMP pin causes an AC current to flow  
through the error amplifier compensation components from the  
FB to the COMP pin. This current then flows through the  
By adding a well controlled output impedance, the output  
voltage can effectively be level shifted in a direction which  
works to achieve a cost-effective solution that can help to  
reduce the output-voltage spike that results from fast  
load-current demand changes.  
feedback resistor, R , and can cause the output voltage to  
FB  
overshoot or undershoot at the end of the VID transition. In  
order to ensure the smooth transition of the output voltage  
FN6518 Rev 3.00  
April 9, 2015  
Page 19 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
during a VID change, a VID-on-the-fly compensation network  
is required. This network is composed of a resistor and  
accomplished by ensuring either rising gate turns on its MOSFET  
with minimum and sufficient delay after the other has turned off.  
capacitor in series, R  
the FB pin.  
and C  
, between the DVC and  
DVC  
DVC  
During turn-off of the lower MOSFET, the PHASE voltage is  
monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor  
current). At this time the UGATE is released to rise. An auto-zero  
I
= I  
C
DVC  
R
FB  
comparator is used to correct the r  
drop in the phase  
DS(ON)  
VSEN  
voltage preventing false detection of the -0.3V phase level during  
conduction period. In the case of zero current, the  
I
C
I
DVC  
r
DS(ON)  
UGATE is released after 35ns delay of the LGATE dropping below  
0.5V. When LGATE first begins to transition low, this quick  
transition can disturb the PHASE node and cause a false trip, so  
there is 20ns of blanking time once LGATE falls until PHASE is  
monitored.  
R
C
C
C
C
R
DVC  
DVC  
DVC  
FB  
COMP  
-
Once the PHASE is high, the advanced adaptive  
shoot-through circuitry monitors the PHASE and UGATE  
voltages during a PWM falling edge and the subsequent  
UGATE turn-off. If either the UGATE falls to less than 1.75V  
above the PHASE or the PHASE falls to less than +0.8V, the  
LGATE is released to turn-on.  
+
ERROR  
AMPLIFIER  
VDAC+RGND  
ISL6324 INTERNAL CIRCUIT  
FIGURE 9. DYNAMIC VID COMPENSATION NETWORK  
This VID-on-the-fly compensation network works by sourcing  
AC current into the FB node to offset the effects of the AC  
current flowing from the FB to the COMP pin during a VID  
transition. To create this compensation current the ISL6324  
sets the voltage on the DVC pin to be 2x the voltage on the  
REF pin. Since the error amplifier forces the voltage on the FB  
pin and the REF pin to be equal, the resulting voltage across  
the series RC between DVC and FB is equal to the REF pin  
Initialization  
Prior to initialization, proper conditions must exist on the EN,  
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When  
the conditions are met, the controller begins soft-start. Once the  
output voltage is within the proper window of operation, the  
controller asserts VDDPWRGD.  
ISL6324 INTERNAL CIRCUIT  
EXTERNAL CIRCUIT  
VCC  
voltage. The RC compensation components, R  
and C ,  
DVC  
DVC  
can then be selected to create the desired amount of  
compensation current.  
PVCC1_2  
The amount of compensation current required is dependant on  
the modulator gain of the system, K1, and the error amplifier  
PVCC_NB  
+12V  
RC components, R and C , that are in series between the FB  
C
C
and COMP pins. Use Equations 14, 15, and 16 to calculate the  
RC component values, R and C , for the VID-on-the-fly  
POR  
CIRCUIT  
DVC DVC  
ENABLE  
COMPARATOR  
10.7k  
compensation network. For these equations: V is the input  
IN  
voltage for the power train; V  
is the oscillator ramp  
P-P  
amplitude (1.5V); and R and C are the error amplifier RC  
EN  
+
-
C
C
components between the FB and COMP pins.  
1.00k  
V
(EQ. 14)  
K1  
K1 1  
IN  
0.86V  
---------------  
----------------  
A =  
K1 =  
V
P P  
ISEN3-  
ISEN4-  
R
= A R  
(EQ. 15)  
(EQ. 16)  
DVC  
C
CHANNEL  
DETECT  
SOFT-START  
AND  
FAULT LOGIC  
C
C
-------  
=
C
DVC  
A
Advanced Adaptive Zero Shoot-Through Deadtime  
Control (Patent Pending)  
FIGURE 10. POWER SEQUENCING USING  
THRESHOLD-SENSITIVE ENABLE (EN)  
The integrated drivers incorporate a unique adaptive deadtime  
control technique to minimize deadtime, resulting in high  
efficiency from the reduced freewheeling time of the lower  
MOSFET body-diode conduction, and to prevent the upper and  
lower MOSFETs from conducting simultaneously. This is  
Power-On Reset  
The ISL6324 requires VCC, PVCC1_2, and PVCC_NB inputs  
to exceed their rising POR thresholds before the ISL6324 has  
sufficient bias to guarantee proper operation.  
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ISL6324 Hybrid SVI/PVI with I C  
The bias voltage applied to VCC must reach the internal  
power-on reset (POR) rising threshold. Once this threshold is  
reached, the ISL6324 has enough bias to begin checking the  
driver POR inputs, EN, and channel detect portions of the  
initialization cycle. Hysteresis between the rising and falling  
thresholds assure the ISL6324 will not advertently turn off  
unless the bias voltage drops substantially (see “Electrical  
Specifications” on page 9).  
disabled, then the corresponding PWMn and ISENn+ pins may  
be left unconnected  
Soft-Start Output Voltage Targets  
Once the POR and Phase Detect blocks and enable  
comparator are satisfied, the controller will begin the soft-start  
sequence and will ramp the CORE and NB output voltages up  
to the SVI interface designated target level if the controller is  
set SVI mode. If set to PVI mode, the North Bridge regulator is  
disabled and the core is soft started to the level designated by  
the parallel VID code.  
The bias voltage applied to the PVCC1_2 and PVCC_NB pins  
power the internal MOSFET drivers of each output channel. In  
order for the ISL6324 to begin operation, both PVCC inputs  
must exceed their POR rising threshold to guarantee proper  
operation of the internal drivers. Hysteresis between the rising  
and falling thresholds assure that once enabled, the ISL6324  
will not inadvertently turn off unless the PVCC bias voltage  
drops substantially (see “Electrical Specifications” on page 9).  
Depending on the number of active CORE channels  
SVI MODE  
Prior to soft-starting both CORE and NB outputs, the ISL6324  
must check the state of the SVI interface inputs to determine  
the correct target voltages for both outputs. When the  
controller is enabled, the state of the VFIXEN, SVD and SVC  
inputs are checked and the target output voltages set for both  
CORE and NB outputs are set by the DAC (see “Serial VID  
Interface (SVI)” on page 16). These targets will only change if  
the EN signal is pulled low or after a POR reset of VCC.  
determined by the Phase Detect block, the external driver POR  
checking is supported by the Enable Comparator.  
Enable Comparator  
Soft-Start  
The ISL6324 features a dual function enable input (EN) for  
enabling the controller and power sequencing between the  
controller and external drivers or another voltage rail. The  
enable comparator holds the ISL6324 in shutdown until the  
voltage at EN rises above 0.86V. The enable comparator has  
about 110mV of hysteresis to prevent bounce. It is important  
that the driver ICs reach their rising POR level before the  
ISL6324 becomes enabled. The schematic in Figure 10  
demonstrates sequencing the ISL6324 with the ISL66xx family  
of Intersil MOSFET drivers, which require 12V bias.  
The soft-start sequence is composed of three periods, as  
shown in Figure 11. At the beginning of soft-start, the DAC  
immediately obtains the output voltage targets for both outputs  
by decoding the state of the SVI or PVI inputs. A 100µs fixed  
delay time, TDA, proceeds the output voltage rise. After this  
delay period the ISL6324 will begin ramping both CORE and  
NB output voltages to the programmed DAC level at a fixed  
rate of 3.25mV/µs. The amount of time required to ramp the  
output voltage to the final DAC voltage is referred to as TDB,  
and can be calculated as shown in Equation 17.  
When selecting the value of the resistor divider the driver  
maximum rising POR threshold should be used for calculating  
the proper resistor values. This will prevent improper  
V
DAC  
------------------------------  
TDB =  
(EQ. 17)  
3  
3.25 10  
sequencing events from creating false trips during soft-start.  
After the DAC voltage reaches the final VID setting,  
If the controller is configured for 2-phase CORE operation,  
then the resistor divider can be used for sequencing the  
controller with another voltage rail. The resistor divider to EN  
should be selected using a similar approach as the previous  
driver discussion.  
VDDPWRGD will be set to high.  
.
V
NB  
400mV/DIV  
V
CORE  
400mV/DIV  
The EN pin is also used to force the ISL6324 into either PVI or  
SVI mode. The mode is set upon the rising edge of the EN  
signal. When the voltage on the EN pin rises above 0.86V, the  
mode will be set depending upon the status of the VID1/SEL  
pin.  
TDA  
TDB  
EN  
5V/DIV  
Phase Detection  
VDDPWRGD  
5V/DIV  
The ISEN3- and ISEN4- pins are monitored prior to soft-start to  
determine the number of active CORE channel phases.  
If ISEN4- is tied to VCC, the controller will configure the  
channel firing order and timing for 3-phase operation. If ISEN3-  
and ISEN4- are tied to VCC, the controller will set the channel  
firing order and timing for 2-phase operation (see “PWM  
Operation” on page 14). If Channel 4 and/or Channel 3 are  
100µs/DIV  
FIGURE 11. SOFT-START WAVEFORMS  
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ISL6324 Hybrid SVI/PVI with I C  
Pre-Biased Soft-Start  
The ISL6324 also has the ability to start up into a pre-charged  
output, without causing any unnecessary disturbance. The FB  
pin is monitored during soft-start, and should it be higher than  
the equivalent internal ramping reference voltage, the output  
drives hold both MOSFETs off.  
17.5µA  
-
OCL  
+
I
1
REPEAT FOR EACH  
CORE CHANNEL  
12.5µA  
-
OCP  
Once the internal ramping reference exceeds the FB pin  
potential, the output drives are enabled, allowing the output to  
ramp from the pre-charged level to the final level dictated by the  
DAC setting. Should the output be pre-charged to a level  
exceeding the DAC setting, the output drives are enabled at the  
end of the soft-start period, leading to an abrupt correction in the  
output voltage down to the DAC-set level.  
+
I
12.5µA  
NB  
-
OCP  
+
I
AVG  
CORE ONLY  
NB ONLY  
SOFT-START, FAULT  
AND CONTROL LOGIC  
Both CORE and NB output support start-up into a pre-charged  
output.  
DUPLICATED FOR  
NB AND CORE  
+
1.8V  
OVP  
-
OUTPUT PRECHARGED  
ABOVE DAC LEVEL  
+
DAC + 250mV  
DAC - 300mV  
OV  
-
OUTPUT PRECHARGED  
BELOW DAC LEVEL  
-
VSEN  
V
CORE  
400mV/DIV  
UV  
+
VDDPWRGD  
ISL6324 INTERNAL CIRCUITRY  
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY  
EN  
5V/DIV  
Fault Monitoring and Protection  
The ISL6324 actively monitors both CORE and NB output  
voltages and currents to detect fault conditions. Fault monitors  
trigger protective measures to prevent damage to either load.  
One common power good indicator is provided for linking to  
external system monitors. The schematic in Figure 13 outlines  
the interaction between the fault monitors and the power good  
signal.  
100µs/DIV  
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6324-BASED  
MULTIPHASE CONVERTER  
Power-Good Signal  
The power-good pin (VDDPWRGD) is an open-drain logic  
output that signals whether or not the ISL6324 is regulating  
both NB and CORE output voltages within the proper levels,  
and whether any fault conditions exist. This pin should be tied  
to a +5V source through a resistor.  
During shutdown and soft-start, VDDPWRGD pulls low and  
releases high after a successful soft-start and both output  
voltages are operating between the undervoltage and  
overvoltage limits. VDDPWRGD transitions low when an  
undervoltage, overvoltage, or overcurrent condition is detected  
on either output or when the controller is disabled by a POR  
reset or EN. In the event of an overvoltage or overcurrent  
condition, the controller latches off and VDDPWRGD will not  
return high. Pending a POR reset of the ISL6324 and  
successful soft-start, the VDDPWRGD will return high.  
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ISL6324 Hybrid SVI/PVI with I C  
converter to begin overcurrent protection procedures. The  
Core regulator and the North Bridge regulator have the same  
type of overcurrent protection.  
Overvoltage Protection  
The ISL6324 constantly monitors the sensed output voltage on  
the VSEN pin to detect if an overvoltage event occurs. When the  
output voltage rises above the OVP trip level and exceeds the  
VDDPWRGD OV limit actions are taken by the ISL6324 to  
protect the microprocessor load.  
The overcurrent trip threshold is dictated by the DCR of the  
inductors, the number of active channels, the DC gain of the  
inductor RC filter and the R  
resistor. The overcurrent trip  
SET  
threshold is shown in Equation 18.  
At the inception of an overvoltage event, both on-board lower  
gate pins are commanded low as are the active PWM outputs  
to the external drivers, the VDDPWRGD signal is driven low,  
and the ISL6324 latches off normal PWM action. This turns on  
the all of the lower MOSFETs and pulls the output voltage  
below a level that might cause damage to the load. The lower  
MOSFETs remain driven ON until VDIFF falls below 400mV.  
The ISL6324 will continue to protect the load in this fashion as  
long as the overvoltage condition recurs. Once an overvoltage  
condition ends the ISL6324 latches off, and must be reset by  
toggling POR, before a soft-start can be re-initiated.  
V
N V  
V
OUT OUT  
N
DCR  
1
K
3
IN  
------------- --- ---------  
---------------------------------------- ---------------  
I
= 100A   
R  
OCP  
SET  
400  
2 L f  
V
IN  
S
(EQ. 18)  
Where:  
K =  
R
2
See “Continuous Current Sampling” on  
page 14.  
--------------------  
+ R  
R
1
2
f
= Switching Frequency  
S
Equation 18 is valid for both the Core regulator and the North  
Bridge regulator. This equation includes the DC load current as  
well as the total ripple current contributed by all the phases.  
For the North Bridge regulator, N is 1.  
Pre-POR Overvoltage Protection  
Prior to PVCC and VCC exceeding their POR levels, the  
ISL6324 is designed to protect either load from any  
overvoltage events that may occur. This is accomplished by  
means of an internal 10kresistor tied from PHASE to LGATE,  
which turns on the lower MOSFET to control the output voltage  
until the overvoltage event ceases or the input power supply  
cuts off. For complete protection, the low side MOSFET should  
have a gate threshold well below the maximum voltage rating  
of the load/microprocessor.  
During soft-start, the overcurrent trip point is boosted by a  
factor of 1.4. Instead of comparing the average measured  
current to 100µA, the average current is compared to 140µA.  
Immediately after soft-start is over, the comparison level  
changes to 100µA. This is done to allow for start-up into an  
active load while still supplying output capacitor in-rush  
current.  
In the event that during normal operation the PVCC or VCC  
voltage falls back below the POR threshold, the pre-POR  
overvoltage protection circuitry reactivates to protect from any  
more pre-POR overvoltage events.  
CORE REGULATOR OVERCURRENT  
At the beginning of overcurrent shutdown, the controller sets all  
of the UGATE and LGATE signals low, puts PWM3 and PWM4  
(if active) in a high-impedance state, and forces VDDPWRGD  
low. This turns off all of the upper and lower MOSFETs. The  
system remains in this state for fixed period of 12ms. If the  
controller is still enabled at the end of this wait period, it will  
attempt a soft-start, as shown in Figure 14. If the fault remains,  
the trip-retry cycles will continue until either the fault is cleared or  
for a total of seven attempts. If the fault is not cleared on the final  
attempt, the controller disables UGATE and LGATE signals for  
both Core and North Bridge and latches off requiring a POR of  
VCC to reset the ISL6324.  
Undervoltage Detection  
The undervoltage threshold is set at VDAC - 300mV typical.  
When the output voltage (VSEN-RGND) is below the  
undervoltage threshold, VDDPWRGD gets pulled low. No other  
action is taken by the controller. VDDPWRGD will return high if  
the output voltage rises above VDAC - 250mV typical.  
Open Sense Line Protection  
In the case that either of the remote sense lines, VSEN or  
GND, become open, the ISL6324 is designed to detect this  
and shut down the controller. This event is detected by  
monitoring small currents that are fed out the VSEN and  
RGND pins. In the event of an open sense line fault, the  
controller will continue to remain off until the fault goes away, at  
which point the controller will re-initiate a soft-start sequence.  
It is important to note that during soft-start, the overcurrent trip  
point is increased by a factor of 1.4. If the fault draws enough  
current to trip overcurrent during normal run mode, it may not  
draw enough current during the soft-start ramp period to trip  
overcurrent while the output is ramping up. If a fault of this type  
is affecting the output, then the regulator will complete soft-  
start and the trip-retry counter will be reset to zero. Once the  
regulator has completed soft-start, the overcurrent trip point will  
return to it’s nominal setting and an overcurrent shutdown will  
be initiated. This will result in a continuous hiccup mode.  
Overcurrent Protection  
The ISL6324 takes advantage of the proportionality between  
the load current and the average current, I  
overcurrent condition. See “Continuous Current Sampling” on  
page 14 and “Channel-Current Balance” on page 15 for more  
detail on how the average current is measured. Once the  
average current exceeds 100µA, a comparator triggers the  
, to detect an  
AVG  
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ISL6324 Hybrid SVI/PVI with I C  
Note that the energy delivered during trip-retry cycling is much  
less than during full-load operation, so there is no thermal  
hazard.  
from the pin to the ground pad under the part is all that is  
required. The PVCC_NB pin (pin 42) should be tied to either  
+5V or to +12V with a small decoupling capacitor to ground. All  
other pins associated with the North Bridge regulator may be  
left unconnected.  
2
OUTPUT CURRENT, 50A/DIV  
I C Bus Interface  
2
The ISL6324 includes an I C bus interface which allows for  
user programmability of three of the controller’s operating  
parameters. The operating parameters that can be adjusted  
through the I C are:  
0A  
2
1. Voltage Margining Offset: The DAC voltage can be offset  
in 25mV increments.  
OUTPUT VOLTAGE,  
500mV/DIV  
2. VDDPWRGD Trip Level: The PGOOD trip level for either  
the Core regulator or the North Bridge regulator can be  
increased.  
0V  
3. Overvoltage Trip Level: The OVP trip level of either the  
3ms/DIV  
Core or North Bridge regulator can be increased.  
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE  
To adjust these three parameters, data transmission from the  
main microprocessor to the ISL6324 and vice versa must take  
NORTH BRIDGE REGULATOR OVERCURRENT  
2
The overcurrent shutdown sequence for the North Bridge  
regulator is identical to the Core regulator with the exception that  
it is a single phase regulator and will only disable the MOSFET  
drivers for the North Bridge. Once 7 retry attempts have been  
executed unsuccessfully, the controller will disable UGATE and  
LGATE signals for both Core and North Bridge and will latch off  
requiring a POR of VCC to reset the ISL6324.  
place through the two wire I C bus interface. The two wires of the  
2
I C bus consist of the SDA line, over which all data is sent, and  
the SCL line, which is a clock signal used to synchronize  
sending/receiving of the data.  
Both SDA and SCL are bidirectional lines, externally connected to  
a positive supply voltage via a pull-up resistor. Pull-up resistor  
values should be chosen to limit the input current to less then  
3mAWhen the bus is free, both lines are HIGH. The output  
stages of ISL6324 have an open drain/open collector in order to  
Note that the energy delivered during trip-retry cycling is much  
less than during full-load operation, so there is no thermal  
hazard.  
2
perform the wired-AND function. Data on the I C bus can be  
transferred up to 100Kbps in the standard-mode or up to 400Kbps  
in the fast-mode. The level of logic “0” and logic “1” is dependent  
Individual Channel Overcurrent Limiting  
The ISL6324 has the ability to limit the current in each  
individual channel of the Core regulator without shutting down  
the entire regulator. This is accomplished by continuously  
comparing the sensed currents of each channel with a  
constant 140µA OCL reference current. If a channel’s  
individual sensed current exceeds this OCL limit, the UGATE  
signal of that channel is immediately forced low, and the  
LGATE signal is forced high. This turns off the upper  
MOSFET(s), turns on the lower MOSFET(s), and stops the rise  
of current in that channel, forcing the current in the channel to  
decrease. That channel’s UGATE signal will not be able to  
return high until the sensed channel current falls back below  
the 140µA reference.  
on associated value of V as per electrical specification table.  
DD  
One clock pulse is generated for each data bit transferred. The  
ISL6324 is a “SLAVE only” device, so the SCL line must always  
be controlled by an external master.  
2
It is important to note that the I C bus of the ISL6324 only  
works once the voltage on the VCC pin has risen above the  
2
POR rising threshold. The I C will continue to remain active  
until the voltage on the VCC pin falls back below the falling  
POR threshold level.  
Data Validity  
The data on the SDA line must be stable during the HIGH  
period of the SCL, unless generating a START or STOP  
condition. The HIGH or LOW state of the data line can only  
change when the clock signal on the SCL line is LOW. Refer to  
Figure 15.  
Exclusive Operation in Parallel Mode  
The ISL6324 was designed such that the processor would be  
the determining factor of whether the ISL6324 operated in PVI  
mode or in SVI mode. If, however, the ISL6324 is to be used in  
a system that will be used exclusively in parallel mode and the  
North Bridge regulator will not be populated at all, there are  
some pin connections that must be made in order for the  
ISL6324 to function properly. The ISEN_NB+ (pin 2) and  
ISEN_NB- (pin 47) pins must be tied to ground. A small trace  
FN6518 Rev 3.00  
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ISL6324 Hybrid SVI/PVI with I C  
.
2
ISL6324 I C Slave Address  
2
2
All devices on the I C bus must have a 7-bit I C address in  
order to be recognized. The address for the ISL6324 is  
1000_110.  
SDA  
SCL  
2
Communicating Over the I C Bus  
DATA LINE CHANGE  
2
Two transactions are supported on the I Cbus:  
STABLE  
OF DATA  
DATA VALID ALLOWED  
1. Write register  
FIGURE 15. DATA VALIDITY  
2. Read register from current address.  
2
All transactions start with a control byte sent from the I C  
START and STOP Conditions  
master device. The control byte begins with a Start condition,  
followed by 7 bits of slave address. The last bit sent by the  
master is the R/W bit and is 0 for a write or 1 for a read. If any  
Figure 16 shows a START (S) condition is a HIGH to LOW  
transition of the SDA line while SCL is HIGH.  
2
The STOP (P) condition is a LOW to HIGH transition on the  
SDA line while SCL is HIGH. A STOP condition must be sent  
before each START condition (see Figure 16).  
slaves on the I C bus recognize their address, they will  
Acknowledge by pulling the serial data line low for the last  
clock cycle in the control byte. If no slaves exist at that address  
or are not ready to communicate, the data line will be 1,  
indicating a Not Acknowledge condition.  
SDA  
SCL  
Once the control byte is sent, and the ISL6324 acknowledges it,  
the 2nd byte sent by the master must be a register address byte.  
This register address byte tells the ISL6324 which one of the two  
internal registers it wants to write to or read from. The address of  
the first internal register, RGS1, is 0000_0000. This register sets  
the North Bridge Offset, Overvoltage trip point and Power Good  
trip level. The address of the second internal register, RGS2, is  
0000_0001. This register sets the Core Offset, Overvoltage trip  
point and Power Good trip level. Once the ISL6324 receives a  
correct register address byte, it responds with an acknowledge.  
S
P
START  
CONDITION  
STOP  
CONDITION  
FIGURE 16. START AND STOP WAVEFORMS  
Byte Format  
Every byte put on the SDA line must be eight bits long. The  
number of bytes that can be transmitted per transfer is  
unrestricted. Each byte has to be followed by an acknowledge  
bit. Data is transferred with the most significant bit first (MSB)  
and the least significant bit last (LSB).  
Writing to the Internal Registers  
In order to change any of the three operating parameters via  
the I C bus, the internal registers must be written to. The two  
2
registers inside the ISL6324 can be written individually with  
two separate write transactions or sequentially with one write  
transaction by sending two data bytes. See “Reading from the  
Internal Registers” on page 26.  
Acknowledge  
Each address and data transmission uses 9-clock pulses. The  
ninth pulse is the acknowledge bit (A). After the start condition,  
the master sends 7 slave address bits and a R/W bit during the  
next 8-clock pulses. During the ninth clock pulse, the device  
that recognizes its own address holds the data line low to  
acknowledge. The acknowledge bit is also used by both the  
master and the slave to acknowledge receipt of register  
addresses and data as described in Figure 17.  
To write to a single register in the ISL6324, the master sends a  
control byte with the R/W bit set to 0, indicating a write. If it  
receives an Acknowledge from the ISL6324, it sends a register  
address byte representing the internal register it wants to write  
to (0000_0000 for RGS1 or 0000_0001 for RGS2). The  
ISL6324 will respond with an Acknowledge. The master then  
sends a byte representing the data byte to be written into the  
desired register. The ISL6324 will respond with an  
Acknowledge. The master then issues a Stop condition,  
indicating to the ISL6324 that the current transaction is  
complete. Once this transaction completes, the ISL6324 will  
immediately update and change the operating parameters on-  
the-fly.  
SCL  
8
2
1
9
SDA  
MSB  
START  
ACKNOWLEDGE  
FROM SLAVE  
2
FIGURE 17. ACKNOWLEDGE ON THE I C BUS  
It is also possible to write to both registers sequentially. To do  
this the master must write to register RGS1 first. This  
transaction begins with the master sending a control byte with  
the R/W bit set to 0. If it receives an Acknowledge from the  
ISL6324, it sends the register address byte 0000_0000,  
FN6518 Rev 3.00  
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ISL6324 Hybrid SVI/PVI with I C  
representing the internal register RGS1. The ISL6324 will  
respond with an Acknowledge. After sending the data byte to  
RGS1 and receiving an Acknowledge from the ISL6324,  
instead of sending a Stop condition, the master sends the data  
byte to be stored in register RGS2. The ISL6324 will respond  
with an Acknowledge. The master then issues a Stop  
condition, indicating to the ISL6324 that the current transaction  
is complete. Once this transaction completes the ISL6324 will  
immediately update and change the operating parameters on-  
the-fly.  
It is also possible for both registers to be read consecutively. To  
do this the master must read from register RGS1 first. This  
transaction begins with the master sending a control byte with  
the R/W bit set to 0. If it receives an Acknowledge from the  
ISL6324, it sends the register address byte 0000_0000,  
representing the internal register RGS1. The ISL6324 will  
respond with an Acknowledge. The master must then respond  
with a Stop condition. After the Stop condition the master  
follows with a new Start condition, and then sends a new  
control byte with the R/W bit set to 1, indicating a read. The  
ISL6324 will then respond by sending the master an  
Acknowledge, followed by the data byte stored in register  
RGS1. The master must then send an Acknowledge, and after  
doing so, the ISL6324 will respond by sending the data byte  
stored in register RGS2. The master must then send a Not  
Acknowledge followed by a Stop command, which will  
complete the read transaction.  
Reading from the Internal Registers  
The ISL6324 has the ability to read from both registers  
separately or read from them consecutively. Prior to reading  
from an internal register, the master must first select the  
desired register by writing to it and sending the register’s  
address byte. This process begins by the master sending a  
control byte with the R/W bit set to 0, indicating a write. Once it  
receives an Acknowledge from the ISL6324, it sends a register  
address byte representing the internal register it wants to read  
from (0000_0000 for RGS1 or 0000_0001 for RGS2). The  
ISL6324 will respond with an Acknowledge. The master must  
then respond with a Stop condition. After the Stop condition,  
the master follows with a new Start condition, and then sends a  
new control byte with the R/W bit set to 1, indicating a read.  
The ISL6324 will then respond by sending the master an  
Acknowledge, followed by the data byte stored in that register.  
The master must then send a Not Acknowledge followed by a  
Stop command, which will complete the read transaction.  
Resetting the Internal Registers  
2
The ISL6324’s two internal I C registers always initialize to  
0000_0000 when the controller first receives power. Once the  
voltage on the VCC pin rises above the POR rising threshold  
2
level, these registers can be changed at any time via the I C  
bus. If the voltage on the VCC pin falls below the POR falling  
threshold, the internal registers are automatically reset to  
0000_0000.  
It is possible to reset the internal registers without powering  
down the controller and without requiring the controller to stop  
regulating and soft-start again. Simply write to the internal  
2
registers over the I C bus to be 0000_0000.  
2
I C Read and Write Protocol  
WRITE TO A SINGLE REGISTER  
S
SLAVE_ADDR + W  
A
REG_ADDR  
A
REG_DATA  
A
A
P
WRITE TO BOTH REGISTERS  
SLAVE_ADDR + W  
READ FROM SINGLE REGISTER  
SLAVE_ADDR + W  
READ FROM BOTH REGISTERS  
S
A
0000_0000  
REG_ADDR  
0000_0000  
A
A
A
REG_RGS1_DATA  
REG_RGS2_DATA  
A
P
S
A
P
P
S
S
SLAVE_ADDR + R  
SLAVE_ADDR + R  
A
A
REG_DATA  
N
A
P
S
SLAVE_ADDR + W  
DRIVEN BY MASTER  
DRIVEN BY ISL6324  
A
REG_RGS1_DATA  
REG_RGS2_DATA  
N
P
S = START CONDITION  
P = STOP CONDITION  
A = ACKNOWLEDGE  
N = NO ACKNOWLEDGE  
FN6518 Rev 3.00  
April 9, 2015  
Page 26 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
TABLE 6. BITS [5:0] REGISTER RGSn  
(VOLTAGE MARGINING OFFSET) (Continued)  
Register Bit Definitions  
The bits for RGS1 and RGS2 are utilized in the same manner  
by the ISL6324. Bit-7 enables the overvoltage protection trip  
point to be increased. Bit-6 enables the Power Good trip point  
to be increased. These bits will be interpreted by the ISL6324  
according to Table 5. Bits 5 through 0 determine the amount of  
offset for the particular regulator. See Table 6 for the bit codes  
and the corresponding offset voltages from the nominal DAC.  
BIT5  
VO5  
1
BIT4  
VO4  
1
BIT3  
VO3  
1
BIT2  
VO2  
0
BIT1  
VO1  
0
BIT0  
VO0  
0
V
OFFSET  
(mV)  
-200  
-175  
-150  
-125  
-100  
-75  
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
TABLE 5. BIT [7] and [6] of REGISTER RGSn  
1
1
1
1
0
0
BIT 7  
OVP TRIP LEVEL  
1
1
1
1
0
1
0
1.8V or V  
1.8V or V  
+ 250mV, whichever is greater  
+ 500mV, whichever is greater  
PGOOD TRIP LEVEL  
DAC  
DAC  
1
1
1
1
1
0
-50  
1
BIT 6  
0
1
1
1
1
1
1
-25  
VDAC +250mV/-300mV  
VDAC +300mV/-350mV  
0
0
0
0
0
0
0
1
0
0
0
0
0
1
25  
NOTE: All Pgood trip points have 50mV hysteresis  
0
0
0
0
1
0
50  
0
0
0
0
1
1
75  
TABLE 6. BITS [5:0] REGISTER RGSn  
(VOLTAGE MARGINING OFFSET)  
0
0
0
1
0
0
100  
125  
150  
175  
200  
225  
250  
275  
300  
325  
350  
375  
400  
425  
450  
475  
500  
525  
550  
575  
600  
625  
650  
675  
700  
725  
750  
775  
0
0
0
1
0
1
BIT5  
VO5  
1
BIT4  
VO4  
0
BIT3  
VO3  
0
BIT2  
VO2  
0
BIT1  
VO1  
0
BIT0  
VO0  
0
V
OFFSET  
(mV)  
0
0
0
1
1
0
0
0
0
1
1
1
-800  
-775  
-750  
-725  
-700  
-675  
-650  
-625  
-600  
-575  
-550  
-525  
-500  
-475  
-450  
-425  
-400  
-375  
-350  
-325  
-300  
-275  
-250  
-225  
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
1
1
1
1
FN6518 Rev 3.00  
April 9, 2015  
Page 27 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
The total maximum power dissipated in each lower MOSFET is  
approximated by the summation of P and P  
General Design Guide  
.
LOW,2  
LOW,1  
UPPER MOSFET POWER CALCULATION  
In addition to r losses, a large portion of the upper  
This design guide is intended to provide a high-level explanation  
of the steps necessary to create a multiphase power converter. It  
is assumed that the reader is familiar with many of the basic skills  
and techniques referenced in the following sections. In addition to  
this guide, Intersil provides complete reference designs that  
include schematics, bills of materials and example board layouts  
for all common microprocessor applications.  
DS(ON)  
MOSFET losses are due to currents conducted across the input  
voltage (V ) during switching. Since a substantially higher  
IN  
portion of the upper-MOSFET losses are dependent on  
switching frequency, the power calculation is more complex.  
Upper MOSFET losses can be divided into separate  
Power Stages  
components involving the upper-MOSFET switching times, the  
The first step in designing a multiphase converter is to determine  
the number of phases. This determination depends heavily on  
the cost analysis which in turn depends on system constraints  
that differ from one design to the next. Principally, the designer  
will be concerned with whether components can be mounted on  
both sides of the circuit board, whether through-hole  
components are permitted, the total board space available for  
power supply circuitry, and the maximum amount of load  
current. Generally speaking, the most economical solutions are  
those in which each phase handles between 25A and 30A. All  
surface-mount designs will tend toward the lower end of this  
current range. If through-hole MOSFETs and inductors can be  
used, higher per-phase currents are possible. In cases where  
board space is the limiting constraint, current can be pushed as  
high as 40A per phase, but these designs require heat sinks and  
forced air to cool the MOSFETs, inductors and heat dissipating  
surfaces.  
lower-MOSFET body-diode reverse recovery charge, Q , and  
rr  
the upper MOSFET r  
DS(ON)  
conduction loss.  
When the upper MOSFET turns off, the lower MOSFET does  
not conduct any portion of the inductor current until the voltage  
at the phase node falls below ground. Once the lower  
MOSFET begins conducting, the current in the upper MOSFET  
falls to zero as the current in the lower MOSFET ramps up to  
assume the full inductor current. In Equation 21, the required  
time for this commutation is t and the approximated  
1
associated power loss is P  
UP(1)  
.
t
1
I
I
M
P-P  
2
(EQ. 21)  
P
V  
f  
----   
----- + ----------  
UP1  
IN  
S
2
N
At turn-on, the upper MOSFET begins to conduct and this  
transition occurs over a time t . In Equation 22, the  
2
approximate power loss is P  
.
UP(2)  
I
t
2
2
MOSFETS  
I  
P-P  
2
M
(EQ. 22)  
P
V  
f  
S
----------   ----   
----- –  
UP2  
IN  
N
The choice of MOSFETs depends on the current each MOSFET  
will be required to conduct, the switching frequency, the  
capability of the MOSFETs to dissipate heat, and the availability  
and nature of heat sinking and air flow.  
A third component involves the lower MOSFET  
reverse-recovery charge, Q . Since the inductor current has  
fully commutated to the upper MOSFET before the  
rr  
lower-MOSFET body diode can recover all of Q , it is  
conducted through the upper MOSFET across VIN. The power  
rr  
LOWER MOSFET POWER CALCULATION  
The calculation for power loss in the lower MOSFET is simple,  
since virtually all of the loss in the lower MOSFET is due to  
current conducted through the channel resistance (r  
dissipated as a result is P  
as shown in Equation 23.  
UP(3)  
(EQ. 23)  
P
= V Q f  
IN rr S  
UP3  
). In  
DS(ON)  
Equation 19, I is the maximum continuous output current, I  
M
P-  
Finally, the resistive part of the upper MOSFET is given in  
Equation 24 as P  
is the peak-to-peak inductor current (see Equation 2), and d  
P
.
UP(4)  
is the duty cycle (V  
/V ).  
OUT IN  
2
2
I
P-P  
2
I
2
M
(EQ. 24)  
I
 1 d  
(EQ. 19)  
P
r  
DSON  
d +  
I
----------  
12  
-----  
LP P  
UP4  
M
P
= r  
DSON  
 1 d+ ----------------------------------------------  
N
-----  
LOW1  
12  
N
The total power dissipated by the upper MOSFET at full load  
can now be approximated as the summation of the results from  
Equations 21, 22, 23 and 24. Since the power equations  
depend on MOSFET parameters, choosing the correct  
MOSFETs can be an iterative process involving repetitive  
solutions to the loss equations for different MOSFETs and  
different switching frequencies.  
An additional term can be added to the lower-MOSFET loss  
equation to account for additional loss accrued during the dead  
time when inductor current is flowing through the lower-  
MOSFET body diode. This term is dependent on the diode  
forward voltage at I , V  
, the switching frequency, f , and  
M
D(ON)  
S
the length of dead times, t and t , at the beginning and the  
d1 d2  
end of the lower-MOSFET conduction interval respectively.  
.
Internal Bootstrap Device  
All three integrated drivers feature an internal bootstrap  
Schottky diode. Simply adding an external capacitor across the  
BOOT and PHASE pins completes the bootstrap circuit. The  
bootstrap function is also designed to prevent the bootstrap  
I  
I
I
I
M
M
P
= V  
f  
S
P-P  
2
P-P  
2
t  
+
t  
-----------  
------ –  
------ + -----------  
LOW2  
DON  
d1  
d2  
N  
N
(EQ. 20)  
FN6518 Rev 3.00  
April 9, 2015  
Page 28 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
capacitor from overcharging due to the large negative swing at  
the PHASE node. This reduces voltage stress on the boot to  
phase pins.  
room temperature. See “Layout Considerations” on page 36 for  
thermal transfer improvement suggestions.  
When designing the ISL6324 into an application, it is  
recommended that the following calculations is used to ensure  
safe operation at the desired frequency for the selected  
The bootstrap capacitor must have a maximum voltage rating  
above PVCC + 4V and its capacitance value can be chosen  
from Equation 25:  
MOSFETs. The total gate drive power losses, P  
, due to  
Qg_TOT  
the gate charge of MOSFETs and the integrated driver’s  
internal circuitry and their corresponding average driver current  
can be estimated with Equations 26 and 27, respectively.  
Q
GATE  
-------------------------------------  
C
BOOT_CAP  
V  
BOOT_CAP  
(EQ. 25)  
P
= P  
+ P  
+ I VCC  
Qg_Q2 Q  
(EQ. 26)  
Q
PVCC  
Qg_TOT  
Qg_Q1  
G1  
-----------------------------------  
Q
=
N  
Q1  
GATE  
V
GS1  
3
--  
P
=
Q  
PVCC f  
N  
N  
Q1 PHASE  
Qg_Q1  
G1  
SW  
2
where Q is the amount of gate charge per upper MOSFET  
G1  
at V  
gate-source voltage and N is the number of control  
P
= Q  
PVCC f  
N  
N  
PHASE  
GS1  
Q1  
Qg_Q2  
G2  
SW  
Q2  
MOSFETs. The V  
BOOT_CAP  
droop in the rail of the upper gate drive.  
term is defined as the allowable  
3
2
--  
I
=
Q  
N  
+ Q  
N  
N  
f  
+ I  
(EQ. 27)  
DR  
G1  
G2  
Q2  
PHASE SW Q  
Q1  
1.6  
In Equations 26 and 27, P  
power loss and P  
Qg_Q2  
is the total upper gate drive  
is the total lower gate drive power loss;  
Qg_Q1  
1.4  
1.2  
1.0  
0.8  
0.6  
the gate charge (Q and Q ) is defined at the particular gate  
G1 G2  
to source drive voltage PVCC in the corresponding MOSFET  
data sheet; I is the driver total quiescent current with no load at  
Q
both drive outputs; N and N are the number of upper and  
Q1 Q2  
lower MOSFETs per phase, respectively; N  
PHASE  
is the number  
of active phases. The I *VCC product is the quiescent power of  
Q
Q
= 100nC  
GATE  
the controller without capacitive load and is typically 75mW at  
300kHz.  
0.4  
50nC  
0.2  
0.0  
20nC  
PVCC  
BOOT  
D
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0  
V (V)  
C
GD  
BOOT_CAP  
R
HI1  
G
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE  
VOLTAGE  
UGATE  
C
DS  
R
R
LO1  
R
GI1  
C
G1  
Gate Drive Voltage Versatility  
GS  
Q1  
The ISL6324 provides the user flexibility in choosing the gate  
drive voltage for efficiency optimization. The controller ties the  
upper and lower drive rails together. Simply applying a voltage  
from 5V up to 12V on PVCC sets both gate drive rail voltages  
simultaneously.  
S
PHASE  
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH  
PVCC  
Package Power Dissipation  
D
When choosing MOSFETs it is important to consider the  
amount of power being dissipated in the integrated drivers  
located in the controller. Since there are a total of three drivers  
in the controller package, the total power dissipated by all three  
drivers must be less than the maximum allowable power  
dissipation for the QFN package.  
C
GD  
R
HI2  
G
LGATE  
C
DS  
R
R
LO2  
R
GI2  
C
G2  
GS  
Q2  
S
Calculating the power dissipation in the drivers for a desired  
application is critical to ensure safe operation. Exceeding the  
maximum allowable power dissipation level will push the IC  
beyond the maximum recommended operating junction  
temperature of +125°C. The maximum allowable IC power  
dissipation for the 7x7 QFN package is approximately 3.5W at  
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH  
FN6518 Rev 3.00  
April 9, 2015  
Page 29 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
The total gate drive power losses are dissipated among the  
resistive components along the transition path and in the  
bootstrap diode. The portion of the total power dissipated in the  
controller itself is the power dissipated in the upper drive path  
1. Choose a capacitor value for the North Bridge RC filter. A  
0.1µF capacitor is a recommended starting point.  
2. Calculate the value for resistor R using Equation 30:  
1
L
NB  
C  
NB  
(EQ. 30)  
-------------------------------------  
R
=
resistance (P  
) the lower drive path resistance (P )  
DR_UP  
DR_UP  
1
DCR  
NB  
NB  
and in the boot strap diode (P  
). The rest of the power will  
BOOT  
be dissipated by the external gate resistors (R and R ) and  
3. Calculate the value for the R  
resistor using Equation 31:  
G1 G2  
SET  
the internal gate resistors (R  
Figures 19 and 20 show the typical upper and lower gate  
drives turn-on transition path. The total power dissipation in the  
and R ) of the MOSFETs.  
GI2  
GI1  
DCR  
K  
V
V  
V
NB NB  
400  
3
NB  
IN  
--------- -----------------------------  
---------------------------- -----------  
R
=
I  
+
SET  
OCP  
100A  
2 L  
f  
V
IN  
NB  
NB  
S
(EQ. 31)  
Where:  
K = 1  
controller itself, P , can be roughly estimated as Equation 28:  
DR  
P
= P  
+ P  
+ P  
+ I VCC  
(Derived from Equation 18).  
DR  
DR_UP  
DR_LOW  
BOOT  
Q
4. Using Equation 32 (also derived from Equation 18),  
calculate the value of K for the Core regulator.  
P
Qg_Q1  
3
---------------------  
P
=
BOOT  
3
400  
N
100A  
---------  
----------------------------- -----------------------------------------------------------------------------------------------------------  
K =  
R  
SET  
DCR  
V
N V  
V
CORE CORE  
R
R
P
CORE  
IN  
HI1  
LO1  
Qg_Q1  
3
-------------------------------------------- --------------------  
I
+
-------------------------------------- --------------------------------------- ---------------------  
P
=
+
OCP  
2 L  
f  
V
IN  
DR_UP  
CORE  
R
+ R  
R
+ R  
EXT1  
CORE  
S
HI1  
EXT1  
LO1  
(EQ. 32)  
R
R
P
Qg_Q2  
HI2  
LO2  
-------------------------------------- --------------------------------------- ---------------------  
P
R
=
+
DR_LOW  
R
+ R  
R
+ R  
EXT2  
2
5. Choose a capacitor value for the Core RC filters. A 0.1µF  
capacitor is a recommended starting point.  
HI2  
EXT2  
LO2  
R
R
GI1  
GI2  
6. Calculate the values for R and R for Core. Equations 33  
-------------  
-------------  
1
2
= R  
+
R
= R  
G2  
+
EXT1  
G1  
EXT2  
N
N
(EQ. 28)  
Q2  
and 34 will allow for their computation.  
Q1  
R
2
Core  
(EQ. 33)  
(EQ. 34)  
Inductor DCR Current Sensing Component  
Selection and R Value Calculation  
----------------------------------------------  
K =  
R
+ R  
1
2
SET  
resistor setting the value of the effective  
Core  
Core  
With the single R  
SET  
R
R  
2
1
L
Core  
Core  
Core  
internal sense resistors for both the North Bridge and Core  
regulators, it is important to set the R value and the  
--------------------------  
----------------------------------------------  
=
C  
Core  
DCR  
Core  
R
+ R  
2
1
SET  
Core  
Core  
inductor RC filter gain, K, properly. See “Continuous Current  
Sampling” on page 14 and “Channel-Current Balance” on  
CASE 2  
I
page 15 for more details on the application of the R  
and the RC filter gain.  
resistor  
Core  
SET  
MAX  
(EQ. 35)  
--------------------------  
I
DCR  
DCR  
Core  
NB  
NB  
N
MAX  
There are 3 separate cases to consider when calculating these  
component values. If the system under design will never utilize  
the North Bridge regulator and the ISL6324 will always be in  
parallel mode, then follow the instructions for Case 3 and only  
calculate values for Core regulator components.  
In Case 2, the DC voltage across the North Bridge inductor at  
full load is greater than the DC voltage across a single phase  
of the Core regulator while at full load. Here, the DC voltage  
across the North Bridge inductor must be scaled down to  
match the DC voltage across the Core inductors, which will be  
For all three cases, use the expected VID voltage that would  
impressed across the ISEN pins without any gain. So, the R  
2
be used at TDC for Core and North Bridge for the V  
and  
resistor for the Core inductor RC filters is left unpopulated and  
CORE  
V
variables, respectively.  
K = 1.  
NB  
CASE 1  
1. Choose a capacitor value for the Core RC filter. A 0.1µF  
capacitor is a recommended starting point.  
I
Core  
MAX  
(EQ. 29)  
--------------------------  
DCR  
Core  
I
DCR  
NB  
MAX  
NB  
2. Calculate the value for resistor R :  
1
N
L
Core  
(EQ. 36)  
-----------------------------------------------  
R
=
In Case 1, the DC voltage across the North Bridge inductor at  
full load is less than the DC voltage across a single phase of  
the Core regulator while at full load. Here, the DC voltage  
across the Core inductors must be scaled down to match the  
DC voltage across the North Bridge inductor, which will be  
impressed across the ISEN_NB pins without any gain. So, the  
1
DCR  
C  
Core  
Core  
Core  
3. Calculate the value for the R  
SET  
resistor using Equation 37:  
DCR  
K  
V
N V  
V
CORE CORE  
400  
CORE  
IN  
--------- --------------------------------------  
-------------------------------------------- --------------------  
R
=
I  
+
SET  
OCP  
3
N 100A  
2 L  
f  
V
IN  
CORE  
CORE  
S
Where:  
K = 1  
(EQ. 37)  
R resistor for the North Bridge inductor RC filter is left  
2
unpopulated and K = 1.  
(Derived from Equation 18).  
FN6518 Rev 3.00  
April 9, 2015  
Page 30 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
4. Using Equation 38 (also derived from Equation 18),  
calculate the value of K for the North bridge regulator.  
then the component values must be recalculated utilizing  
Case 2.  
V
V  
V
3
400  
1
100A  
1
3
400  
IN  
NB NB  
---------  
--------------------- -------------------------------------------------------------------------  
K =  
R  
--------------------- ---------  
---------------------------- -----------  
I
= 100A   
R  
+
SET  
DCR  
V
V  
V
NB  
OCP  
SET  
DCR  
2 L  
f  
V
IN  
NB  
IN  
NB  
NB  
NB  
NB  
S
---------------------------- -----------  
I
+
OCP  
2 L  
f  
V
IN  
NB  
NB  
S
(EQ. 45)  
(EQ. 38)  
Note: The values of R  
must be greater than 20kand less  
SET  
5. Choose a capacitor value for the North Bridge RC filter. A  
0.1µF capacitor is a recommended starting point.  
than 80k. For all of the 3 cases above, if the calculated value  
of R is less than 20k, then either the OCP trip point needs  
SET  
to be increased or the inductor must be changed to an inductor  
with higher DCR. If the R resistor is greater than 80k,  
6. Calculate the values for R and R for North Bridge.  
1
2
Equations 39 and 40 will allow for their computation.  
SET  
that is less than 80kmust be chosen  
R
then a value of R  
2
SET  
NB  
(EQ. 39)  
------------------------------------  
K =  
and a resistor divider across both North Bridge and Core  
inductors must be set up with proper gain. This gain will  
represent the variable “K” in all equations. It is also very  
R
+ R  
1
2
NB  
NB  
R
R  
2
1
L
NB  
NB  
NB  
(EQ. 40)  
---------------------  
------------------------------------  
C  
=
important that the R  
resistor be tied between the RSET pin  
SET  
NB  
DCR  
NB  
R
+ R  
1
2
NB  
NB  
and the VCC pin of the ISL6324.  
Inductor DCR Current Sensing Component Fine  
Tuning  
CASE 3  
I
Core  
MAX  
(EQ. 41)  
--------------------------  
DCR  
Core  
I
DCR  
=
I
V
IN  
NB  
MAX  
NB  
L
N
n
UGATE(n)  
LGATE(n)  
L
In Case 3, the DC voltage across the North Bridge inductor at  
full load is equal to the DC voltage across a single phase of the  
Core regulator while at full load. Here, the full scale DC  
inductor voltages for both North Bridge and Core will be  
DCR  
V
OUT  
MOSFET  
DRIVER  
INDUCTOR  
-
C
OUT  
V (s)  
L
-
V
(s)  
C
C
impressed across the ISEN pins without any gain. So, the R  
2
resistors for the Core and North Bridge inductor RC filters are  
R
1
left unpopulated and K = 1 for both regulators.  
R
2
For this Case, it is recommended that the overcurrent trip point  
for the North Bridge regulator be equal to the overcurrent trip  
point for the Core regulator divided by the number of core  
phases.  
ISL6324 INTERNAL CIRCUIT  
I
n
1. Choose a capacitor value for the North Bridge RC filter. A  
0.1µF capacitor is a recommended starting point.  
SAMPLE  
+
-
2. Calculate the value for the North Bridge resistor R :  
1
ISENn-  
-
V
(s)  
C
L
NB  
(EQ. 42)  
ISENn+  
VCC  
-------------------------------------  
R
=
R
ISEN  
1
DCR  
C  
NB  
NB  
NB  
I
SEN  
3. Choose a capacitor value for the Core RC filter. A 0.1µF  
capacitor is a recommended starting point.  
To Active  
Core Channels  
RSET  
{
R
SET  
To North Bridge  
4. Calculate the value for the Core resistor R :  
1
L
Core  
(EQ. 43)  
C
SET  
-----------------------------------------------  
R
=
1
DCR  
C  
Core  
Core  
Core  
FIGURE 21. DCR SENSING CONFIGURATION  
5. Calculate the value for the R  
SET  
resistor using Equation 44:  
Due to errors in the inductance and/or DCR it may be  
necessary to adjust the value of R and R to match the time  
1
2
DCR  
K  
V
N V  
V
CORE CORE  
400  
3
CORE  
IN  
--------- --------------------------------------  
-------------------------------------------- -------------------  
R
=
I  
+
constants correctly. The effects of time constant mismatch can  
be seen in the form of droop overshoot or undershoot during  
the initial load transient spike, as shown in Figure 22. Follow  
the steps below to ensure the RC and inductor L/DCR time  
constants are matched accurately.  
SET  
OCP  
N 100A  
2 L  
f  
V
IN  
CORE  
CORE  
S
(EQ. 44)  
Where:  
K = 1  
6. Calculate the OCP trip point for the North Bridge regulator  
using Equation 45. If the OCP trip point is higher than  
desired, then the component values must be recalculated  
utilizing Case 1. If the OCP trip point is lower than desired,  
FN6518 Rev 3.00  
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ISL6324 Hybrid SVI/PVI with I C  
1. If the regulator is not utilizing droop, modify the circuit by  
placing the frequency set resistor between FS and Ground  
for the duration of this procedure.  
these poles is determined by the system function, the gain of  
the current signal, and the value of the compensation  
components, R and C .  
C
C
2. Capture a transient event with the oscilloscope set to about  
L/DCR/2 (sec/div). For example, with L = 1µH and DCR =  
1m, set the oscilloscope to 500µs/div.  
C
(OPTIONAL)  
2
3. Record V1 and V2 as shown in Figure 22. Select new  
C
C
R
C
values, R  
and R  
) for the time constant  
COMP  
FB  
1(NEW)  
2(NEW  
resistors based on the original values, R  
and  
1(OLD)  
R
using Equations 46 and 47.  
2(OLD)  
V  
ISL6324  
1
(EQ. 46)  
(EQ. 47)  
---------  
R1NEW= R1OLD  
R
FB  
V  
2
VSEN  
V  
1
---------  
R2NEW= R2OLD  
V  
2
4. Replace R and R with the new values and check to see  
1
2
FIGURE 23. COMPENSATION CONFIGURATION FOR  
LOAD-LINE REGULATED ISL6324 CIRCUIT  
that the error is corrected. Repeat the procedure if  
necessary.  
Since the system poles and zero are affected by the values of  
the components that are meant to compensate them, the  
solution to the system equation becomes fairly complicated.  
Fortunately, there is a simple approximation that comes very  
close to an optimal solution. Treating the system as though it  
were a voltage-mode regulator, by compensating the L-C poles  
and the ESR zero of the voltage mode approximation, yields a  
solution that is always stable with very close to ideal transient  
performance.  
V  
2
V  
1
V
OUT  
Select a target bandwidth for the compensated system, f . The  
0
I
TRAN  
target bandwidth must be large enough to assure adequate  
transient performance, but smaller than 1/3 of the per-channel  
switching frequency. The values of the compensation  
I  
components depend on the relationships of f to the L-C pole  
0
frequency and the ESR zero frequency. For each of the  
following three, there is a separate set of equations for the  
compensation components.  
FIGURE 22. TIME CONSTANT MISMATCH BEHAVIOR  
Loadline Regulation Resistor  
The loadline regulation resistor, labeled R in Figure 8, sets  
FB  
the desired loadline required for the application. Equation 48  
In Equation 49, L is the per-channel filter inductance divided by  
the number of active channels; C is the sum total of all output  
capacitors; ESR is the equivalent series resistance of the bulk  
can be used to calculate R  
.
FB  
V
output filter capacitance; and V  
sawtooth signal amplitude as described in the “Electrical  
Specifications” table on page 9.  
is the peak-to-peak  
DROOP  
MAX  
P-P  
R
= ---------------------------------------------------------------------  
(EQ. 48)  
FB  
I
OUT  
400  
--------- ------------------------- --------------  
K  
DCR  
MAX  
3
N
R
SET  
Once selected, the compensation values in Equation 49  
assure a stable converter with reasonable transient  
performance. In most cases, transient performance can be  
Where K is defined in Equation 7.  
If no loadline regulation is required, FS resistor should be tied  
improved by making adjustments to R . Slowly increase the  
C
between the FS pin and VCC. To choose the value for R in  
FB  
value of R while observing the transient performance on an  
C
this situation, please refer to “Compensation Without Loadline  
Regulation” on page 33.  
oscilloscope until no further improvement is noted. Normally,  
C
will not need adjustment. Keep the value of C from  
C
C
Equation 49 unless some performance issue is noted.  
Compensation With Loadline Regulation  
The load-line regulated converter behaves in a similar manner  
to a peak current mode controller because the two poles at the  
output filter L-C resonant frequency split with the introduction  
of current information into the control loop. The final location of  
The optional capacitor C , is sometimes needed to bypass  
2
noise away from the PWM comparator (see Figure 23). Keep a  
position available for C , and be prepared to install a high  
2
FN6518 Rev 3.00  
April 9, 2015  
Page 32 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
frequency capacitor of between 22pF and 150pF in case any  
be lower than 10f can cause problems with too much phase shift  
0
leading edge jitter problem is noted.  
below the system bandwidth as shown in Equation 50.  
.
.
C ESR  
L C C ESR  
1
-------------------------------------------  
FB  
R
C
= R  
------------------------------- > f  
0
1
1
2    L C  
Case 1:  
2    f V  
L C  
0
P-P  
----------------------------------------------------------  
FB  
R
C
= R  
L C C ESR  
C
= -------------------------------------------  
0.66 V  
IN  
R
FB  
0.66 V  
IN  
= -----------------------------------------------------  
C
1
2    V  
R f  
0
0.75 V  
P-P  
FB  
IN  
C
= -----------------------------------------------------------------------------------------------------  
2
2
2   f f  
  L C  R V  
0
HF  
FB P-P  
(EQ. 50)  
1
-------------------------------  
2    L C  
f < -------------------------------------  
0
2    C ESR  
Case 2:  
2
   
2  
f f  
L C R  
FB  
2
2
V
0
HF  
V
 2   f L C  
0
P-P  
P-P  
R
C
= -----------------------------------------------------------------------------------------  
-----------------------------------------------------------------  
FB  
R
C
= R  
(EQ. 49)  
C
C
C
C
 2    f  
L C1  
0.66 V  
0.75  
V
HF  
IN  
IN  
0.66 V  
IN  
= --------------------------------------------------------------------------------------  
2   f V  
0.75 V  2    f  
L C1  
2
2
IN  
HF  
R  
L C  
0
P-P  
FB  
= -----------------------------------------------------------------------------------------------------  
2
2   f f  
  L C  R V  
0
HF  
FB P-P  
1
Case 3:  
f
> -------------------------------------  
In the solutions to the compensation equations, there is a  
single degree of freedom. For the solutions presented in  
0
2    C ESR  
2    f V  
L  
0
P-P  
Equation 51, R is selected arbitrarily. The remaining  
---------------------------------------------  
FB  
R
C
= R  
FB  
C
C
0.66 V ESR  
IN  
compensation components are then selected according to  
Equation 51.  
0.66 V ESR   
C
IN  
= -----------------------------------------------------------------  
2    V R f  
0
L
Where, L is the per-channel filter inductance divided by the  
number of active channels; C is the sum total of all output  
capacitors; ESR is the equivalent-series resistance of the bulk  
P-P  
FB  
Compensation Without Loadline Regulation  
The non load-line regulated converter is accurately modeled as  
a voltage-mode regulator with two poles at the L-C resonant  
frequency and a zero at the ESR frequency. A type-III  
controller, as shown in Figure 24, provides the necessary  
compensation.  
output-filter capacitance; and V  
is the peak-to-peak  
P-P  
sawtooth signal amplitude as described in “Electrical  
Specifications” on page 9.  
Output Filter Design  
C
2
1
------------------------------- > f  
Case 1:  
Case 2:  
Case 3:  
0
2    L C  
2    f V  
L C  
C
0
P-P  
C
R
C
----------------------------------------------------------  
R
C
= R  
COMP  
FB  
C
C
FB  
0.66 V  
IN  
0.66 V  
IN  
= -----------------------------------------------------  
2    V  
R f  
0
P-P  
FB  
C
1
ISL6324  
1
1
-------------------------------  
2    L C  
f < -------------------------------------  
R
0
R
FB  
1
2    C ESR  
2
2
V
 2   f L C  
0
VSEN  
PP  
----------------------------------------------------------------  
FB  
R
C
= R  
(EQ. 51)  
C
C
0.66 V  
IN  
0.66 V  
IN  
= --------------------------------------------------------------------------------------  
2   f V  
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE  
REGULATION  
2
2
R  
L C  
0
P-P  
FB  
The first step is to choose the desired bandwidth, f , of the  
0
1
f > -------------------------------------  
compensated system. Choose a frequency high enough to  
assure adequate transient performance but not higher than 1/3 of  
the switching frequency. The type-III compensator has an extra  
high-frequency pole, f . This pole can be used for added noise  
rejection or to assure adequate attenuation at the error amplifier  
high-order pole and zero frequencies. A good general rule is to  
0
2    C ESR  
2    f V  
L  
0
P-P  
---------------------------------------------  
R
C
= R  
FB  
C
C
0.66 V ESR  
IN  
HF  
0.66 V ESR   
C
IN  
= -----------------------------------------------------------------  
2    V R f  
0
L
P-P  
FB  
choose f = 10f , but it can be higher if desired. Choosing f to  
HF HF  
0
FN6518 Rev 3.00  
April 9, 2015  
Page 33 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
The output inductors and the output capacitor bank together to  
form a low-pass filter responsible for smoothing the pulsating  
voltage at the phase nodes. The output filter also must provide  
the transient energy until the regulator can respond. Because it  
has a low bandwidth compared to the switching frequency, the  
output filter limits the system transient response. The output  
capacitors must supply or sink load current while the current in  
the output inductors increases or decreases to meet the  
demand.  
Since the capacitors are supplying a decreasing portion of the  
load current while the regulator recovers from the transient, the  
capacitor voltage becomes slightly depleted. The output  
inductors must be capable of assuming the entire load current  
before the output voltage decreases more than V  
. This  
MAX  
places an upper limit on inductance.  
Equation 54 gives the upper limit on L for the cases when the  
trailing edge of the current transient causes a greater output-  
voltage deviation than the leading edge. Equation 55  
addresses the leading edge. Normally, the trailing edge  
dictates the selection of L because duty cycles are usually less  
than 50%. Nevertheless, both inequalities should be  
evaluated, and L should be selected based on the lower of the  
two results. In each equation, L is the per-channel inductance,  
C is the total output capacitance, and N is the number of active  
channels.  
In high-speed converters, the output capacitor bank is usually  
the most costly (and often the largest) part of the circuit. Output  
filter design begins with minimizing the cost of this part of the  
circuit. The critical load parameters in choosing the output  
capacitors are the maximum size of the load step, I, the load-  
current slew rate, di/dt, and the maximum allowable output-  
voltage deviation under transient loading, V  
. Capacitors  
MAX  
are characterized according to their capacitance, ESR, and ESL  
(equivalent series inductance).  
2 N C V  
O
(EQ. 54)  
---------------------------------  
L   
L   
V  
I ESR  
MAX  
2
I  
At the beginning of the load transient, the output capacitors  
supply all of the transient current. The output voltage will  
initially deviate by an amount approximated by the voltage drop  
across the ESL. As the load current increases, the voltage  
drop across the ESR increases linearly until the load current  
reaches its final value. The capacitors selected must have  
sufficiently low ESL and ESR so that the total output voltage  
deviation is less than the allowable maximum. Neglecting the  
contribution of inductor current and regulator response, the  
output voltage initially deviates by an amount as shown in  
Equation 52:  
N C  
1.25  
(EQ. 55)  
   
I ESR  V V  
MAX IN O  
----------------------------  
V  
2
I  
Switching Frequency  
There are a number of variables to consider when choosing the  
switching frequency, as there are considerable effects on the  
upper MOSFET loss calculation. These effects are outlined in  
“MOSFETs” on page 28, and they establish the upper limit for the  
switching frequency. The lower limit is established by the  
requirement for fast transient response and small output-voltage  
ripple as outlined in “Output Filter Design” on page 33. Choose  
the lowest switching frequency that allows the regulator to meet  
the transient-response requirements.  
di  
----  
(EQ. 52)  
V ESL + ESR  I  
dt  
The filter capacitor must have sufficiently low ESL and ESR so  
that V < V  
Switching frequency is determined by the selection of the  
.
frequency-setting resistor, R . Figure 25 and Equation 56 are  
MAX  
T
provided to assist in selecting the correct value for R .  
T
Most capacitor solutions rely on a mixture of high frequency  
capacitors with relatively low capacitance in combination with  
bulk capacitors having high capacitance but limited high-  
frequency performance. Minimizing the ESL of the high-  
frequency capacitors allows them to support the output voltage  
as the current increases. Minimizing the ESR of the bulk  
capacitors allows them to supply the increased current with  
less output voltage deviation.  
10.61 1.035 logf   
(EQ. 56)  
S
R
= 10  
T
1k  
The ESR of the bulk capacitors also creates the majority of the  
output-voltage ripple. As the bulk capacitors sink and source  
the inductor AC ripple current (see “Interleaving” on page 12  
and Equation 3), a voltage develops across the bulk capacitor  
100  
ESR equal to I  
(ESR). Thus, once the output capacitors  
C(P-P)  
are selected, the maximum allowable ripple voltage, V  
P-  
, determines the lower limit on the inductance.  
P(MAX)  
10  
10k  
100k  
1M  
10M  
V
V
N V  
IN  
OUT  
OUT  
SWITCHING FREQUENCY (Hz)  
(EQ. 53)  
L
-------------------------------------------------------------------  
ESR   
f
V V  
IN P-P(MAX)  
FIGURE 25. R vs SWITCHING FREQUENCY  
T
S
FN6518 Rev 3.00  
April 9, 2015  
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2
ISL6324 Hybrid SVI/PVI with I C  
.
Input Capacitor Selection  
0.3  
0.2  
0.1  
0
I
I
= 0  
I
I
= 0.5 I  
O
The input capacitors are responsible for sourcing the AC  
component of the input current flowing into the upper MOSFETs.  
Their RMS current capacity must be sufficient to handle the AC  
component of the current drawn by the upper MOSFETs which  
is related to duty cycle and the number of active phases.  
0.3  
L(P-P)  
L(P-P)  
= 0.25 I  
= 0.75 I  
O
L(P-P)  
O
L(P-P)  
I
I
= 0  
= 0.25 I  
I
I
= 0.5 I  
O
L(P-P)  
L(P-P)  
L(P-P)  
L(P-P)  
= 0.75 I  
O
O
0.2  
0.1  
0
0
0.2  
0.4  
0.6  
0.8  
1.0  
DUTY CYCLE (V  
V
)
O
IN/  
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS  
CURRENT FOR 3-PHASE CONVERTER  
0.3  
0.2  
0.1  
0
0.2  
0.4  
0.6  
0.8  
1.0  
DUTY CYCLE (V  
V
)
O/ IN  
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT  
vs DUTY CYCLE FOR 4-PHASE CONVERTER  
For a four-phase design, use Figure 26 to determine the input-  
capacitor RMS current requirement set by the duty cycle,  
maximum sustained output current (I ), and the ratio of the  
O
peak-to-peak inductor current (I  
) to I . Select a bulk  
L(P-P)  
O
capacitor with a ripple current rating which will minimize the  
total number of input capacitors required to support the RMS  
current calculated.  
I
I
I
= 0  
L(P-P)  
L(P-P)  
L(P-P)  
= 0.5 I  
O
= 0.75 I  
O
The voltage rating of the capacitors should also be at least  
1.25x greater than the maximum input voltage. Figures 27 and  
28 provide the same input RMS current information for  
3-phase and 2-phase designs respectively. Use the same  
approach for selecting the bulk capacitor type and number.  
Low capacitance, high-frequency ceramic capacitors are  
needed in addition to the input bulk capacitors to suppress  
leading and falling edge voltage spikes. The spikes result from  
the high current slew rate produced by the upper MOSFET turn  
on and off. Place low ESL ceramic capacitors as close as  
possible to each upper MOSFET drain to minimize board  
parasitics and maximize suppression.  
0
0
0.2  
0.4  
0.6  
0.8  
1.0  
DUTY CYCLE (V  
V
)
IN/  
O
FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS  
CURRENT FOR 2-PHASE CONVERTER  
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FN6518 Rev 3.00  
April 9, 2015  
Page 35 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
circuit close to their respective controller pins, since they belong to  
a high-impedance circuit loop, sensitive to EMI pick-up.  
Layout Considerations  
MOSFETs switch very fast and efficiently. The speed with which  
the current transitions from one device to another causes voltage  
spikes across the interconnecting impedances and parasitic  
circuit elements. These voltage spikes can degrade efficiency,  
radiate noise into the circuit and lead to device overvoltage stress.  
Careful component selection, layout, and placement minimizes  
these voltage spikes. Consider, as an example, the turnoff  
transition of the upper PWM MOSFET. Prior to turnoff, the upper  
MOSFET was carrying channel current. During the turn-off,  
current stops flowing in the upper MOSFET and is picked up by  
the lower MOSFET. Any inductance in the switched current path  
generates a large voltage spike during the switching interval.  
Careful component selection, tight layout of the critical  
components, and short, wide circuit traces minimize the  
magnitude of voltage spikes.  
A multi-layer printed circuit board is recommended. Figure 28  
shows the connections of the critical components for the  
converter. Note that capacitors C and C  
could each  
IN OUT  
represent numerous physical capacitors. Dedicate one solid layer,  
usually the one underneath the component side of the board, for a  
ground plane and make all critical component ground connections  
with vias to this layer. Dedicate another solid layer as a power  
plane and break this plane into smaller islands of common voltage  
levels. Keep the metal runs from the PHASE terminal to output  
inductors short. The power plane should support the input power  
and output power nodes. Use copper filled polygons on the top  
and bottom circuit layers for the phase nodes. Use the remaining  
printed circuit layers for small signal wiring.  
Routing UGATE, LGATE, and PHASE Traces  
Great attention should be paid to routing the UGATE, LGATE,  
and PHASE traces since they drive the power train MOSFETs  
using short, high current pulses. It is important to size them as  
large and as short as possible to reduce their overall impedance  
and inductance. They should be sized to carry at least one  
ampere of current (0.02” to 0.05”). Going between layers with  
vias should also be avoided, but if so, use two vias for  
interconnection when possible.  
There are two sets of critical components in a DC/DC converter  
using a ISL6324 controller. The power components are the most  
critical because they switch large amounts of energy. Next are  
small signal components that connect to sensitive nodes or  
supply critical bypassing current and signal coupling.  
The power components should be placed first, which include the  
MOSFETs, input and output capacitors, and the inductors. It is  
important to have a symmetrical layout for each power train,  
preferably with the controller located equidistant from each.  
Symmetrical layout allows heat to be dissipated equally across  
all power trains. Equidistant placement of the controller to the  
CORE and NB power trains it controls through the integrated  
drivers helps keep the gate drive traces equally short, resulting  
in equal trace impedances and similar drive capability of all sets  
of MOSFETs.  
Extra care should be given to the LGATE traces in particular  
since keeping their impedance and inductance low helps to  
significantly reduce the possibility of shoot-through. It is also  
important to route each channels UGATE and PHASE traces in  
as close proximity as possible to reduce their inductances.  
Current Sense Component Placement and Trace  
Routing  
One of the most critical aspects of the ISL6324 regulator layout  
is the placement of the inductor DCR current sense  
components and traces. The R-C current sense components  
must be placed as close to their respective ISEN+ and ISEN-  
pins on the ISL6324 as possible.  
When placing the MOSFETs try to keep the source of the upper  
FETs and the drain of the lower FETs as close as thermally  
possible. Input high-frequency capacitors, C , should be placed  
HF  
close to the drain of the upper FETs and the source of the lower  
FETs. Input bulk capacitors, CBULK, case size typically limits  
following the same rule as the high-frequency input capacitors.  
Place the input bulk capacitors as close to the drain of the upper  
FETs as possible and minimize the distance to the source of the  
lower FETs.  
The sense traces that connect the R-C sense components to  
each side of the output inductors should be routed on the  
bottom of the board, away from the noisy switching  
components located on the top of the board. These traces  
should be routed side by side, and they should be very thin  
traces. It’s important to route these traces as far away from any  
other noisy traces or planes as possible. These traces should  
pick up as little noise as possible.  
Locate the output inductors and output capacitors between the  
MOSFETs and the load. The high-frequency output decoupling  
capacitors (ceramic) should be placed as close as practicable to  
the decoupling target, making use of the shortest connection  
paths to any internal planes, such as vias to GND next or on the  
capacitor solder pad.  
Thermal Management  
For maximum thermal performance in high current, high switching  
frequency applications, connecting the thermal GND pad of the  
ISL6324 to the ground plane with multiple vias is recommended.  
This heat spreading allows the part to achieve its full thermal  
potential. It is also recommended that the controller be placed in a  
direct path of airflow if possible to help thermally manage the part.  
The critical small components include the bypass capacitors  
(C  
) for VCC and PVCC, and many of the components  
FILTER  
surrounding the controller including the feedback network and  
current sense components. Locate the VCC/PVCC bypass  
capacitors as close to the ISL6324 as possible. It is especially  
important to locate the components associated with the feedback  
FN6518 Rev 3.00  
April 9, 2015  
Page 36 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
R
FB  
C
2
+12V  
+12V  
C
C
R
C
R
C
3_2  
IN  
FB  
C
VSEN  
BOOT  
C
BOOT  
COMP  
ISEN3+  
ISEN3-  
PWM3  
C
IN  
C
BOOT1  
R
BOOT1  
3
3_1  
UGATE1  
PHASE1  
UGATE1  
PHASE1  
LGATE1  
R
C
APA  
R
1_1  
APA  
C
1
LGATE1  
PGND  
PWM1  
APA  
DVC  
R
1_2  
ISEN1-  
ISEN1+  
+12V  
ISL6614  
+12V  
V_CORE  
+5V  
+12V  
PVCC1_2  
VCC  
C
FILTER  
C
C
FILTER  
IN  
BOOT2  
PVCC  
VCC  
C
IN  
C
BOOT  
C
BOOT  
C
FILTER  
BOOT2  
C
BULK  
C
HF  
FS  
UGATE2  
PHASE2  
GND  
UGATE2  
R
FS  
CPU  
LOAD  
PHASE2  
LGATE2  
PWM2  
R
SET  
C
R
R
4
4_1  
C
2_1  
2
LGATE2  
RSET  
R
4_2  
R
2_2  
VFIXEN  
SEL  
ISEN2-  
ISEN2+  
SVD  
SVC  
VID4  
RGND  
NC  
NC  
VID5  
PWROK  
VDDPWRGD  
ISEN4+  
ISEN4-  
GND  
SCL  
SDA  
PWM4  
+12V  
ISL6324  
+12V  
KEY  
HEAVY TRACE ON CIRCUIT PLANE LAYER  
ISLAND ON POWER PLANE LAYER  
ISLAND ON CIRCUIT PLANE LAYER  
VIA CONNECTION TO GROUND PLANE  
PVCC_NB  
R
EN1  
EN2  
C
C
FILTER  
IN  
EN  
OFF  
ON  
C
BOOT_NB  
BOOT_NB  
R
UGATE_NB  
V_NB  
PHASE_NB  
LGATE_NB  
C
BULK  
C
R
HF  
1_NB  
C
1_NB  
RED COMPONENTS:  
LOCATE CLOSE TO IC TO  
MINIMIZE CONNECTION PATH  
R
2_NB  
NB  
LOAD  
ISEN_NB-  
ISEN_NB+  
BLUE COMPONENTS:  
LOCATE NEAR LOAD  
(MINIMIZE CONNECTION PATH)  
COMP_NB  
FB_NB  
R
C_NB  
C
C_NB  
MAGENTA COMPONENTS:  
LOCATE CLOSE TO SWITCHING TRANSISTORS  
(MINIMIZE CONNECTION PATH)  
R
FB_NB  
FIGURE 29. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS  
FN6518 Rev 3.00  
April 9, 2015  
Page 37 of 38  
2
ISL6324 Hybrid SVI/PVI with I C  
Package Outline Drawing  
L48.7x7  
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
Rev 5, 4/10  
4X  
5.5  
7.00  
A
44X  
6
0.50  
B
PIN #1 INDEX AREA  
37  
48  
6
1
36  
PIN 1  
INDEX AREA  
4. 30 ± 0 . 15  
12  
25  
(4X)  
0.15  
13  
24  
0.10 M C A B  
48X 0 . 40± 0 . 1  
TOP VIEW  
4
0.23 +0.07 / -0.05  
BOTTOM VIEW  
SEE DETAIL "X"  
C
C
0.10  
0 . 90 ± 0 . 1  
BASE PLANE  
( 6 . 80 TYP )  
4 . 30 )  
SEATING PLANE  
0.08 C  
(
SIDE VIEW  
( 44X 0 . 5 )  
0 . 2 REF  
5
C
( 48X 0 . 23 )  
( 48X 0 . 60 )  
0 . 00 MIN.  
0 . 05 MAX.  
TYPICAL RECOMMENDED LAND PATTERN  
DETAIL "X"  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3. Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Dimension applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 indentifier may be  
either a mold or mark feature.  
FN6518 Rev 3.00  
April 9, 2015  
Page 38 of 38  

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