ISL6520IBZ-T [INTERSIL]
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; 单同步降压脉宽调制（ PWM ）控制器
| 型号： | ISL6520IBZ-T |
| 厂家： | 
Intersil |
| 描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 文件： | 总11页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6520
®
Data Sheet
October 4, 2005
FN9009.4
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
Features
• Operates from +5V Input
The ISL6520 makes simple work out of implementing a
complete control and protection scheme for a DC/DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6520 integrates the
control, output adjustment, monitoring and protection
functions into a single 8-pin package.
• 0.8V to V Output Range
IN
- 0.8V Internal Reference
- ±1.5% Over Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
The ISL6520 provides simple, single feedback loop, voltage-
mode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of ±1.5% over temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Over-Current Protection
- Uses Upper MOSFET’s r
DS(on)
The error amplifier features a 15MHz gain-bandwidth
product and 8V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
• Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Protection from over-current conditions is provided by
monitoring the r
of the upper MOSFET to inhibit PWM
DS(ON)
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
Applications
• Power Supplies for Microprocessors
- PCs
PART
PART
TEMP.
PKG.
NUMBER MARKING RANGE (°C)
PACKAGE
8 Ld SOIC
DWG. #
ISL6520CB 6520CB
0 to 70
0 to 70
M8.15
- Embedded Controllers
ISL6520CBZ 6520CBZ
(Note)
8 Ld SOIC (Pb-free) M8.15
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
ISL6520IB
6520IB
-40 to 85 8 Ld SOIC
M8.15
ISL6520IBZ 6520IBZ
(Note)
-40 to 85 8 Ld SOIC (Pb-free) M8.15
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
ISL6520CR ISL6520CR
0 to 70
16 Ld 4x4mm QFN L16.4x4
ISL6520IR
ISL6520IR
-40 to 85 16 Ld 4x4mm QFN L16.4x4
Evaluation Board
ISL6520EVAL1
• Personal Computer Peripherals
* Add “-T” suffix for tape and reel.
• Industrial Power Supplies
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• 5V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6520
Pinouts
SOIC
QFN
TOP VIEW
TOP VIEW
BOOT
UGATE
GND
1
2
3
4
8
7
6
5
PHASE
COMP/SD
FB
16 15 14 13
GND
BOOT
UGATE
GND
1
2
3
4
12 NC
11 COMP/OCSET
10 NC
LGATE
VCC
NC
9
FB
5
6
7
8
Block Diagram
VCC
POR AND
SOFTSTART
BOOT
+
SAMPLE
AND
-
OC
UGATE
HOLD
COMPARATOR
PHASE
PWM
+
ERROR
AMP
COMPARATOR
0.8V
GATE
CONTROL
LOGIC
+
-
+
-
-
PWM
VCC
FB
LGATE
COMP/OCSET
20µA
OSCILLATOR
FIXED 300kHz
GND
Typical Application
V
CC
C
C
BULK
DCPL
C
HF
D
BOOT
VCC
R
OCSET
BOOT
5
1
ISL6520
C
BOOT
UGATE
PHASE
COMP/OCSET
2
8
7
L
OUT
+V
O
R
F
C
I
LGATE
4
C
6
3
OUT
C
F
GND
FB
R
OFFSET
R
S
FN9009.4
2
October 4, 2005
ISL6520
Absolute Maximum Ratings
Thermal Information
Thermal Resistance
o
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
θ
( C/W)
95. . N/A
45. . 7
θ
( C/W)
CC
Absolute Boot Voltage, V
JA
JC
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
SOIC Package (Note 1) . . . . . . . . . . . . . .
Upper Driver Supply Voltage, V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
- V
. . . . . . . . . . . +6.0V
BOOT
PHASE
QFN Package (Note 2, 3). . . . . . . . . . . . . .
Maximum Junction Temperature
o
o
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
o
Maximum Storage Temperature Range. . . . . . . . -65 C to 150 C
Maximum Lead Temperature
Recommended Operating Conditions
o
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
(SOIC - Lead Tips Only)
o
o
o
o
Ambient Temperature Range - ISL6520C . . . . . . . . . . . 0 C to 70 C
Ambient Temperature Range - ISL6520I . . . . . . . . . . -40 C to 85 C
o
o
Junction Temperature Range. . . . . . . . . . . . . . . . . . -40 C to 125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
UGATE and LGATE Open
2.6
3.2
3.8
mA
VCC
POWER-ON RESET
Rising VCC POR Threshold
VCC POR Threshold Hysteresis
OSCILLATOR
POR
4.19
-
4.30
0.25
4.5
-
V
V
Frequency
f
ISL6520C, V
= 5V
250
230
-
300
300
1.5
340
340
-
kHz
kHz
OSC
CC
= 5V
ISL6520I, V
CC
Ramp Amplitude
∆V
V
P-P
OSC
REFERENCE
Reference Voltage Tolerance
ISL6520C
ISL6520I
-1.5
-2.5
-
-
+1.5
+2.5
-
%
%
V
Nominal Reference Voltage
ERROR AMPLIFIER
DC Gain
V
0.800
REF
Guaranteed By Design
-
-
-
88
15
8
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
MHz
V/µs
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION / DISABLE
OCSET Current Source
I
-
-
-
-
-1
1
-
-
-
-
A
A
A
A
UGATE-SRC
I
UGATE-SNK
I
-1
2
LGATE-SRC
I
LGATE-SNK
I
ISL6520C
ISL6520I
17
14
-
20
20
22
24
-
µA
µA
V
OCSET
Disable Threshold
V
0.8
DISABLE
FN9009.4
3
October 4, 2005
ISL6520
An over-current trip cycles the soft-start function.
Functional Pin Description
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error amplifier.
Use this pin, in combination with the FB pin, to compensate the
voltage-control feedback loop of the converter.
VCC
This is the main bias supply for the ISL6520, as well as the
lower MOSFET’s gate. Connect a well-decoupled 5V supply
to this pin.
Pulling OCSET to a level below 0.8V will disable the
controller. Disabling the ISL6520 causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
FB
This pin is the inverting input of the internal error amplifier. Use
this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the converter.
LGATE
GND
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
Do not insert any circuitry between this pin and the gate of the
lower MOSFET, as it may interfere with the internal adaptive
shoot-through protection circuitry and render it ineffective.
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection. This pin is also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
Functional Description
Initialization
The ISL6520 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Over-Current Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
Over Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
BOOT
r
, to monitor the current. This method enhances the
DS(ON)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor
OCSET
Application diagram).
COMP/OCSET
This is a multiplexed pin. During a short period of time following
power-on reset (POR), this pin is used to determine the over-
current threshold of the converter. Connect a resistor (R
from this pin to the drain of the upper MOSFET (V ).
(R
) programs the over-current trip level (see Typical
)
OCSET
CC
), and the
Immediately following POR, the ISL6520 initiates the Over-
Current Protection sampling and hold operation. First, the
internal error amplifier is disabled. This allows an internal
R
, an internal 20µA current source (I
OCSET
OCSET
upper MOSFET on-resistance (r
) set the converter over-
DS(ON)
20µA current sink to develop a voltage across R
. The
OCSET
current (OC) trip point according to the following equation:
ISL6520 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Over-Current Set Point.
I
xR
OCSET
OCSET
I
= -------------------------------------------------
PEAK
r
DS(ON)
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Over-Current Set
Point, the over-current function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6520 to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
Internal circuitry of the ISL6520 will not recognize a voltage
drop across R larger than 0.5V. Any voltage drop
OCSET
that is greater than 0.5V will set the
across R
OCSET
overcurrent trip point to:
0.5V
I
= ----------------------
PEAK
r
DS(ON)
FN9009.4
4
October 4, 2005
ISL6520
Start interval and causes an over-current trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
increasing width that charge the output capacitor(s). When the
internally generated Soft Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
OUTPUT INDUCTOR
CURRENT
5A/DIV.
V
OUT
500mV/DIV.
COMP/OCSET
1V/DIV.
TIME (5ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
TIME (2ms/DIV.)
The over-current function will trip at a peak inductor current
PEAK)
FIGURE 2. START UP SEQUENCE
(I
determined by:
I
x R
OCSET
OCSET
I
= ----------------------------------------------------
Application Guidelines
PEAK
r
DS(ON)
Layout Considerations
where I
is the internal OCSET current source (20µA
OCSET
typical). The OC trip point varies mainly due to the
MOSFET’s r variations. To avoid over-current tripping
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
DS(ON)
in the normal operating load range, find the R
from the equation above with:
resistor
OCSET
1. The maximum r
temperature.
2. The minimum I
at the highest junction
DS(ON)
from the specification table.
OCSET
(∆I)
I
> I
+ ----------
3. Determine I
for
,
PEAK
PEAK
OUT(MAX)
V
IN
2
where ∆I is the output inductor ripple current.
ISL6520
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
UGATE
PHASE
Q
Q
1
L
O
V
OUT
Soft Start
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (non-
inverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the oversurrent setpoint by disabling the error
C
IN
2
LGATE
C
O
RETURN
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
amplifier and drawing 20µA through R
. Once the over-
OCSET
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
current level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
FN9009.4
5
October 4, 2005
ISL6520
ST
Please note that the capacitors C and C may each
IN
2. Place 1 Zero Below Filter’s Double Pole (~75% F ).
LC
O
ND
represent numerous physical capacitors. Locate the ISL6520
within 3 inches of the MOSFETs, Q and Q . The circuit traces
3. Place 2
Zero at Filter’s Double Pole.
ST
1
2
4. Place 1 Pole at the ESR Zero.
for the MOSFETs’ gate and source connections from the
ISL6520 must be sized to handle up to 1A peak current.
ND
5. Place 2
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R
close
V
IN
DRIVER
DRIVER
OSCET
OSC
to the COMP/OCSET pin because the internal current source is
only 20µA. Provide local V decoupling between VCC and
PWM
L
O
COMPARATOR
V
OUT
CC
GND pins. Locate the capacitor, C
the BOOT and PHASE pins. All components used for feedback
compensation should be located as close to the IC a practical.
as close as practical to
-
PHASE
BOOT
+
∆V
C
O
OSC
ESR
(PARASITIC)
Z
FB
+V
IN
BOOT
V
E/A
D
1
Z
Q
1
-
IN
+5V
L
O
C
+
BOOT
V
OUT
REFERENCE
ERROR
AMP
PHASE
VCC
ISL6520
C
O
+5V
DETAILED COMPENSATION COMPONENTS
Q
2
COMP/OCSET
GND
Z
FB
V
OUT
C
2
C
VCC
Z
IN
C
C
R
R
3
1
3
2
R
1
COMP
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
FB
-
+
ISL6520
Feedback Compensation
REFERENCE
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
(V
) is regulated to the Reference voltage level. The
OUT
error amplifier (Error Amp) output (V ) is compared with
E/A
the oscillator (OSC) triangular wave to provide a pulse-
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
width modulated (PWM) wave with an amplitude of V at
IN
OUT E/A
Gain and the output filter (L and C ), with a double pole
the PHASE node. The PWM wave is smoothed by the output
O
O
filter (L and C ).
break frequency at F and a zero at F . The DC Gain of
LC ESR
O
O
the modulator is simply the input voltage (V ) divided by the
IN
Modulator Break Frequency Equations
peak-to-peak oscillator voltage ∆V
OSC
.
1
1
F
= ------------------------------------------
F
= -------------------------------------------
Compensation Break Frequency Equations
LC
ESR
2π x ESR x C
2π x
L
x C
O
O
O
1
2
1
F
= -----------------------------------
F
= --------------------------------------------------------
Z1
Z2
P1
P2
2π x R x C
C
x C
2
1
The compensation network consists of the error amplifier
(internal to the ISL6520) and the impedance networks Z
and Z . The goal of the compensation network is to provide
FB
a closed loop transfer function with the highest 0dB crossing
1
---------------------
C + C
2π x R
x
2
IN
1
2
1
1
3
F
= ------------------------------------------------------
F
= -----------------------------------
2π x (R + R ) x C
2π x R x C
3
1
3
3
frequency (f
) and adequate phase margin. Phase margin
0dB
is the difference between the closed loop phase at f
and
0dB
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R , R ,
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
1
2
R , C , C , and C ) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
3
1
2
3
1. Pick Gain (R /R ) for desired converter bandwidth.
2
1
FN9009.4
6
October 4, 2005
ISL6520
Check the compensation gain at F with the capabilities of
P2
Use only specialized low-ESR capacitors intended for
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F
F
P1
F
F
Z2
Z1
P2
80
60
40
20
0
Output Inductor Selection
OPEN LOOP
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
ERROR AMP GAIN
20LOG
(R /R )
2
1
20LOG
(V /DV
)
OSC
IN
MODULATOR
GAIN
COMPENSATION
GAIN
-20
-40
-60
V
- V
Fs x L
V
OUT
IN
OUT
CLOSED LOOP
∆V
= ∆I x ESR
∆I =
x
OUT
GAIN
V
IN
F
LC
F
ESR
100K
FREQUENCY (Hz)
10
100
1K
10K
1M
10M
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6520 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L x I
L x I
V
TRAN
OUT
TRAN
t
=
t
=
FALL
RISE
V
- V
IN
OUT
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
where: I
is the transient load current step, t
is the
is the
TRAN
RISE
response time to the application of load, and t
FALL
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
FN9009.4
7
October 4, 2005
ISL6520
minimum and maximum output levels for the worst case
response time.
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Input Capacitor Selection
1
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk
2
Io x V x t
IN SW
x F
S
P
P
= Io x r
x D +
UPPER
DS(ON)
2
2
= Io x r
x (1 - D)
LOWER
DS(ON)
capacitors to supply the current needed each time Q turns
1
Where: D is the duty cycle = V
/ V ,
IN
OUT
on. Place the small ceramic capacitors physically close to
t
is the switching interval, and
is the switching frequency.
SW
the MOSFETs and between the drain of Q and the source
1
F
S
of Q .
2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
Given the reduced available gate bias voltage (5V),
logic-level or sub-logic-level transistors should be used for
both N-MOSFETs. Caution should be exercised with
devices exhibiting very low V
characteristics. The
GS(ON)
shoot-through protection present aboard the ISL6520 may
be circumvented by these MOSFETs if they have large
parasitic impedences and/or capacitances that would
inhibit the gate of the MOSFET from being discharged
below its threshold level before the complementary
MOSFET is turned on.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
+5V
D
BOOT
+5V
+ V
-
D
VCC
BOOT
C
ISL6520
BOOT
Q1
UGATE
PHASE
MOSFET Selection/Considerations
The ISL6520 requires two N-Channel power MOSFETs.
NOTE:
≈ V -V
D
V
G-S
CC
These should be selected based upon r
supply requirements, and thermal management
requirements.
, gate
DS(ON)
Q2
LGATE
-
+
NOTE:
G-S
In high-current applications, the MOSFET power
V
≈ V
CC
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6520 and don't heat the
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V . The boot capacitor,
CC
C
, develops a floating supply voltage referenced to
BOOT
the PHASE pin. The supply is refreshed to a voltage of V
CC
less the boot diode drop (V ) each time the lower
D
MOSFET, Q , turns on.
2
MOSFETs. However, large gate-charge increases the
switching interval, t
which increases the upper MOSFET
SW
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
FN9009.4
8
October 4, 2005
ISL6520
ISL6520 DC/DC Converter Application Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete Bill-
of-Materials and circuit board description, can be found in
Application Note AN9932.
+5V
+
0.1µF
C
2 x 1µF
IN
2 x 330µF
VCC
5
ISL6520
D
1
6.19kΩ
MONITOR
AND
PROTECTION
1
BOOT
UGATE
PHASE
2
8
COMP/OCSET
7
0.1µF
Q
1
REF
L
1
10.0kΩ
+
470pF
FB
-
V
OUT
4
8200pF
LGATE
+
-
+
6
Q
C
2
OUT
3 x 330µF
0.1µF
OSC
3
GND
1.00kΩ
U
1
3.16kΩ
60.4Ω
18000pF
Component Selection Notes:
C
C
- Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
L - 3.1µH Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent.
1
Q , Q - Intersil MOSFET; HUF76143.
1 2
IN
- Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
OUT
D1 - 30mA Schottky Diode, MA732 or Equivalent
FIGURE 8. 5V to 3.3V 15A DC/DC CONVERTER
FN9009.4
9
October 4, 2005
ISL6520
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9009.4
10
October 4, 2005
ISL6520
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
1.95
1.95
0.28
0.35
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.65 BSC
-
k
0.25
0.50
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9009.4
11
October 4, 2005
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