ISL6521CBZ-T_技术文档

ISL6521

®

Data Sheet

February 8, 2005

FN9148.2

PWM Buck DC-DC and Triple Linear

Power Controller

Features

• Provides 4 Regulated Voltages

- Switching Regulator 20A Capable

- Three Linear Regulators

- Capable of 120mA

- Capable of up to 3A with an External Transistor

• Externally Resistor-Adjustable Outputs

The ISL6521 provides the power control and protection for

four output voltages in low-voltage, high-performance

applications. The IC integrates a voltage-mode PWM

controller and three linear controllers, as well as monitoring

and protection functions into a 16-lead SOIC package. The

PWM controller is intended to regulate the low voltage

supply that requires the greatest amount of current (usually

the core voltage for the FPGA, ASIC, or processor) with a

synchronous rectified buck converter. The linears are

intended to regulate other system voltages, such as I/O

(input/output) and memory circuits. Both the switching

regulator and linear voltage reference provide ±2% of static

regulation over line, load, and temperature ranges. All

outputs are user-adjustable by means of an external resistor

divider. All linear controllers can supply up to 120mA with no

external pass devices. Employing bipolar NPNs for the pass

transistors, the linear regulators can achieve output currents

of 3A or higher with proper device selection.

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- All Outputs: ±2% Over Temperature

• Overcurrent Fault Monitors

- Switching Regulator Does Not Require Extra Current

Sensing Element, Uses MOSFET’s r

DS(ON)

• Small Converter Size

- 300kHz Constant Frequency Operation

- Small External Component Count

The ISL6521 monitors all the output voltages. The PWM

controller’s adjustable overcurrent function monitors the

output current by using the voltage drop across the upper

• Commercial and Industrial Temperature Range Support

• Pb-free Available (RoHS Compliant)

MOSFET’s r

. The linear regulator outputs are

DS(ON)

monitored via the FB pins for undervoltage events.

Ordering Information

Applications

PKG.

™

•

PowerPC

FPGA and

-based boards

PART NUMBER TEMP. RANGE (°C) PACKAGE

DWG. #

• General purpose, low voltage power supplies

ISL6521CBZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.15

Related Literature

ISL6521CBZ-T

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

• Technical Support Document AG0001, “Power

Management Application Guide for Xilinx FPGAs”

ISL6521IBZ

(Note)

-40 to 85

16 Ld SOIC

(Pb-free)

• Technical Support Document AG0002, “Power

Management Application Guide for Altera FPGAs”

ISL6521IBZ-T

(Note)

-40 to 85

16 Ld SOIC

(Pb-free)

• Technical Support Document AG0005, “Power

Management Application Guide for Actel FPGAs”

ISL6521EVAL1

Evaluation Board

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

ISL6521 (SOIC)

Pinout

TOP VIEW

DRIVE2

FB2

1

2

3

4

5

6

7

8

16 FB3

15 DRIVE3

14 FB4

13 DRIVE4

12 OCSET

11 VCC

FB

COMP

GND

PHASE

BOOT

UGATE

10 LGATE

9

PGND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6521

Typical Applications

High Output Current PWM Converter With Simple Triple Linears Regulators

L

IN

+5V

+

C

IN

V

OUT2

VCC

2.5V

BOOT

120mA

DRIVE2

FB2

C

BOOT

+

OCSET

C

OUT2

Rs2

Rs3

Rp2

UGATE

PHASE

Q1

Q2

V

OUT1

1.5V

L

OUT1

V

OUT3

1.8V

120mA

DRIVE3

FB3

+

ISL6521

LGATE

PGND

C

OUT1

CR1

C

OUT3

OUT4

Rp3

FB

V

OUT4

Rs1

3.3V

COMP

120mA

DRIVE4

FB4

C

Rs4

Rp1

Rp4

GND

High Output Current PWM Converter and Auxiliary 3.3V Linear Regulator

L

IN

+5V

+

C

IN

V

OUT2

VCC

2.5V

BOOT

120mA

DRIVE2

FB2

C

BOOT

+

OCSET

C

OUT2

Rs2

Rs3

Rp2

UGATE

PHASE

Q1

Q2

V

OUT1

1.5V

L

OUT1

V

OUT3

1.8V

120mA

DRIVE3

FB3

+

ISL6521

LGATE

PGND

C

OUT1

CR1

OUT3

Rp3

FB

+5V

Rs1

COMP

V

DRIVE4

FB4

OUT4

Q3

3.3V

3A

Rs4

+

Rp1

Rp4

GND

C

OUT4

3

ISL6521

Absolute Maximum Ratings

Thermal Information

UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V

VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V

Thermal Resistance (Typical, Note 1)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

θ

JA

(°C/W)

74

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Operating Conditions

Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

Ambient Temperature Range

ISL6521CBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

ISL6521IBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . -40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Operating Conditions: VCC = 5V, T = 0°C to 70°C, Unless Otherwise Noted. Typical specifications are at

A

T

= 25°C.

A

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply Current

POWER-ON RESET

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

UGATE, LGATE, and DRIVEx Open

-

5

-

mA

CC

Rising VCC Threshold

4.25

3.74

-

4.51

4.0

V

Falling VCC Threshold

OSCILLATOR AND SOFT-START

Free Running Frequency

F

ISL6521CBZ

275

250

-

300

1.5

325

350

-

kHz

OSC

ISL6521IBZ (-40°C to 85°C)

Ramp Amplitude

∆V

V

P-P

OSC

SS

Soft-Start Interval

T

6.25

6.83

7.40

ms

REFERENCE VOLTAGE

Reference Voltage (All Regulators)

All Outputs Voltage Regulation

V

0.780 0.800 0.820

V

REF

ISL6521CBZ

-2.0

-2.5

-

+2.0

+2.5

%

ISL6521IBZ (-40°C to 85°C)

LINEAR REGULATORS (OUT2, OUT3, AND OUT4)

Output Drive Current (All Linears)

VCC > 4.5V

100

-

120

70

-

mA

%

Undervoltage Level (V /V

)

V

UV

FB REF

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain

-

15

-

80

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

COMP = 10pF

6

PWM CONTROLLER GATE DRIVERS

UGATE Source

I

VCC = 5V, V

= 2.5V

-

-1

1

-

A

UGATE

LGATE

UGATE Sink

I

V

= 2.5V

UGATE-PHASE

LGATE Source

I

VCC = 5V, V

= 2.5V

-1

2

LGATE

LGATE Sink

I

V

= 2.5V

LGATE

PROTECTION

OCSET Current Source

I

ISL6521CBZ

ISL6521IBZ (-40°C to 85°C)

34

40

46

48

µA

OCSET

31.5

4

ISL6521

DRIVE2, 3, 4 (Pins 1, 15, 13)

Functional Pin Descriptions

VCC (Pin 11)

Provide a well decoupled 5V bias supply for the IC to this

pin. This pin also provides the gate bias charge for the lower

MOSFET controlled by the PWM section of the IC, as well as

the drive current for the linear regulators. The voltage at this

pin is monitored for Power-On Reset (POR) purposes.

Connect these pins to the point of load or to the base

terminals of external bipolar NPN transistors. These pins are

each capable of providing 120mA of load current or drive

current for the pass transistors.

FB2, 3, 4 (Pins 2, 16, 14)

Connect the output of the corresponding linear regulators to

these pins through properly sized resistor dividers. The

voltage at these pins is regulated to 0.8V. These pins are

also monitored for undervoltage events.

GND (Pin 5)

Signal ground for the controller. All voltage levels are

measured with respect to this pin.

Quickly pulling and holding any of these pins above 1.25V

(using diode-coupled logic devices) shuts off the respective

regulators. Releasing these pins from the pull-up voltage

initiates a soft-start sequence on the respective regulator.

PGND (Pin 9)

This is the power ground connection. Tie the source of the

lower MOSFET of the synchronous PWM converter to this

pin.

Description

Operation

BOOT (Pin 7)

Floating bootstrap supply pin for the upper gate drive. The

bootstrap capacitor provides the necessary charge to turn

and hold the upper MOSFET on. Connect a suitable

capacitor (0.47µF recommended) from this pin to PHASE.

The ISL6521 monitors and precisely controls one

synchronous PWM converter and three configurable linear

regulators from a +5V bias input. The PWM controller is

designed to regulate the core voltage of an embedded

processor or simple down conversion for high current

applications. The PWM controller drives two MOSFETs (Q1

and Q2) in a synchronous-rectified buck converter

OCSET (Pin 12)

Connect a resistor from this pin to the drain of the upper

PWM MOSFET. This resistor, an internal 40µA current

source (typical), and the upper MOSFET’s on-resistance set

the converter overcurrent trip point. An overcurrent trip

cycles the soft-start function.

configuration and regulates the output voltage to a level

programmed by a resistor divider. The linear controllers are

designed to regulate three additional system voltages.

Typically, these include any I/O, memory, or clock voltages

that might be required. All three linear controllers support

up to 120mA of load current without external pass devices

or higher currents with external NPN bipolar transistors.

The voltage at this pin is monitored for power-on reset

(POR) purposes and pulling this pin below 1.25V with an

open drain/collector device will shut down the switching

controller.

Initialization

PHASE (Pin 6)

The ISL6521 automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

monitors the input bias supply voltage. The POR monitors

the bias voltage at the VCC pin. The POR function initiates

soft-start operation after the bias supply voltage exceeds its

POR threshold.

Connect this pin to the source of the PWM converter upper

MOSFET. This pin is used to monitor the voltage drop across

the upper MOSFET for overcurrent protection.

UGATE (Pin 8)

Connect UGATE pin to the PWM converter’s upper

MOSFET gate. This pin provides the gate drive for the upper

MOSFET.

Soft-Start

The POR function initiates the soft-start sequence. The

PWM error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s).

Similarly, all linear regulators’ reference inputs are clamped

to a voltage proportional to the soft-start voltage. The ramp-

up of the internal soft-start function provides a controlled

output voltage rise.

LGATE (Pin 10)

This pin provides the gate drive for the synchronous rectifier

lower MOSFET. Connect LGATE to the gate of the lower

MOSFET.

COMP and FB (Pins 4, 3)

COMP and FB are the available external pins of the PWM

converter error amplifier. The FB pin is the inverting input of the

error amplifier. Similarly, the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-mode

control feedback loop of the synchronous PWM converter.

Figure 1 shows the soft-start sequence for a typical

application. At T0 the +5V bias voltage starts to ramp up

crossing the 4.5V POR threshold at time T1. On the PWM

section, the oscillator’s triangular waveform is compared to

5

ISL6521

the clamped error amplifier output voltage. As the internal

soft-start voltage increases, the pulse-width on the PHASE

pin increases to reach its steady-state duty cycle at time T2.

Also at time T2, the error amplifier references of the linear

controllers, ramp to their final value bringing all outputs

within regulation limits.

three soft-start periods, the fourth cycle initiates a ramp-up of

this linear output at time T3. One soft-start period after T3,

the linear output is within regulation limits. UV glitches less

than 1µs (typically) in duration are ignored.

V

(3.3V)

(1.8V)

OUT4

V

OUT3

+5V

V

(1.5V)

OUT1

V

(2.5V)

OUT2

(0.5V/DIV.)

V

(3.3V)

0V

OUT4

0V

V

(2.5V)

(1.8V)

(1V/DIV)

OUT2

SOFT-START

FUNCTION

OUT3

V

(1.5V)

OUT1

UV MONITORING

V

INACTIVE

ACTIVE

OUT1

0V

(0.5V/DIV)

V

OUT2

T0

T1

T2

TIME

T0

T1

T2

T3T4

FIGURE 1. SOFT-START INTERVAL

TIME

FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION

RESPONSE

Overcurrent Protection

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFET’s

Overcurrent protection is performed on the synchronous

switching regulator on a cycle-by-cycle basis. OC monitoring

is active as long as the regulator is operational. Since the

overcurrent protection on the linear regulators is performed

through undervoltage monitoring at the feedback pins (FB2,

FB3, and FB4), this feature is activated approximately 25%

into the soft-start interval (see Figure 2).

on-resistance, r

to monitor the current for protection

DS(ON)

against a shorted output. All linear controllers monitor their

respective FB pins for undervoltage events to protect against

excessive currents.

A sustained overload (undervoltage on linears or overcurrent

on the PWM) on any output results in an independent

shutdown of the respective output, followed by subsequent

individual re-start attempts performed at an interval equivalent

to 3 soft-start intervals. Figure 2 describes the protection

feature. At time T0, an overcurrent event sensed across the

A resistor (R

) programs the overcurrent trip level for

OCSET

the PWM converter. As shown in Figure 3, the internal

40µA current sink (I ) develops a voltage across

OCSET

R

(V ) that is referenced to V . The DRIVE

OCSET SET

IN

signal enables the overcurrent comparator (OCC). When

the voltage across the upper MOSFET (V ) exceeds

switching regulator’s upper MOSFET (r

sensing)

output. As a result, its

DS(ON)

triggers a shutdown of the V

OUT1

V

, the overcurrent comparator trips to set the

SET

internal soft-start initiates a number of soft-start cycles. After a

three-cycle wait, the fourth soft-start initiates a ramp-up

attempt of the failed output, at time T2, bringing the output in

regulation at time T4.

overcurrent latch. Both V

and V

are referenced

DS(ON)

OCSET

SET

to V and a small capacitor across R

helps V

OCSET

IN

track the variations of V due to MOSFET switching. The

IN

overcurrent function will trip at a peak inductor current

(I

determined by:

PEAK)

To exemplify a UV event on one of the linears, at time T1,

I

× R

the clock regulator (V

) is also subjected to an

OCSET

OUT2

I

= ---------------------------------------------------

PEAK

r

overcurrent event, resulting in a UV condition. Similarly, after

DS(ON)

6

ISL6521

The OC trip point varies with MOSFET’s r

Output voltage selection on the linear regulators is set by

DS(ON)

temperature variations. To avoid overcurrent tripping in the

means of external resistor dividers as shown in Figure 4.

The two resistors used to set the voltage on each of the

three linear regulators have to meet the following criteria:

their value while in a parallel connection has to be less than

5kΩ, or otherwise said, the following relationship has to be

met:

normal operating load range, determine the R

resistor from the equation above with:

OCSET

1. The maximum r

2. The minimum I

at the highest junction temperature.

from the specification table.

DS(ON)

OCSET

3. Determine I

for I

> I

+ (∆I)/2, where

PEAK

OUT(MAX)

R

× R

+ R

P

S

P

∆I is the output inductor ripple current.

---------------------

< 5kΩ

S

OVERCURRENT TRIP:

V

= +5V

IN

V

> V

> I

DS

SET

To ensure the parallel combination of the feedback resistors

i

¥ r

¥ R

D

DS(ON) OCSET

OCSET

equals a certain chosen value, R , use the following

FB

R

OCSET

equations:

OCSET

V

I

i

OUT

OCSET

D

V

+

---------------

SET

R

=

× R

S

FB

40µA

FB

VCC

UGATE

+

R

× V

FB

S

DRIVE

, where

R

= --------------------------------

V

DS(ON)

P

V

– V

OUT

FB

OC

+

PHASE

-

V

- the desired output voltage,

OUT

OCC

V

= V – V

PHASE

IN

DS

- feedback (reference) voltage, 0.8V.

FB

GATE

CONTROL

PWM

V

= V – V

OCSET

IN

SET

Application Guidelines

Soft-Start Interval

FIGURE 3. OVERCURRENT DETECTION

The soft-start function controls the output voltages rate of rise

to limit the current surge at start-up. The soft-start function is

integrated on the chip and the soft-start interval is fixed.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

Output Voltage Selection

PWM Controller Feedback Compensation

The output voltage of the PWM converter can be resistor-

The PWM controller uses voltage-mode control for output

regulation. This section highlights the design consideration

for a PWM voltage-mode controller. Apply the methods and

considerations only to the PWM controller.

programmed to any level between V and 0.8V. However,

IN

since the value of R is affecting the values of the rest of

S1

the compensation components, it is advisable its value is

kept between 2kΩ and 5kΩ.

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

+5V

IN

(V

) is regulated to the reference voltage level, 0.8V. The

OUT

error amplifier (Error Amp) output (V ) is compared with

DRIVE3

FB3

E/A

Q3

the oscillator (OSC) triangular wave to provide a pulse-width

V

OUT3

C

modulated (PWM) wave with an amplitude of V at the

IN

R

S3

PHASE node. The PWM wave is smoothed by the output

+

R

OUT3

P3

ISL6521

filter (L and C ).

O O

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

V

OUT4

DRIVE4

FB4

OUT E/A

Gain, given by V /V

, and shaped by the output filter,

LC

IN OSC

C

OUT4

with a double pole break frequency at F and a zero at

R

S4

F

.

ESR

R

P4

Modulator Break Frequency Equations

R









S

P

1

V

= 0.8 × 1 + -------



F

= ---------------------------------------

F

= -----------------------------------------

OUT

LC

ESR



2π × ESR × C

2π ×

L × C

O

O O

FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF

THE FOUR REGULATORS (OUTPUTS 3 AND 4

PICTURED)

The compensation network consists of the error amplifier

(internal to the ISL6521) and the impedance networks Z

IN

7

ISL6521

Figure 6 shows an asymptotic plot of the DC-DC converter’s

V

IN

gain vs. frequency. The actual Modulator Gain has a high

gain peak dependent on the quality factor (Q) of the output

filter, which is not shown in Figure 5. Using the above

guidelines should yield a Compensation Gain similar to the

curve plotted. The open loop error amplifier gain bounds the

DRIVER1

OSC

PWM

L

O

COMP

V

OUT

SYNC

-

DRIVER

PHASE

+

∆V

C

OSC

O

compensation gain. Check the compensation gain at F

P2

ESR

(PARASITIC)

with the capabilities of the error amplifier. The Closed Loop

Gain is constructed on the log-log graph of Figure 6 by

adding the Modulator Gain (in dB) to the Compensation Gain

(in dB). This is equivalent to multiplying the modulator

transfer function to the compensation transfer function and

plotting the gain.

Z

FB

Z

IN

V

E/A

+

0.8V

ERROR

AMP

The compensation gain uses external impedance networks

DETAILED COMPENSATION COMPONENTS

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

Z

FB

V

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

OUT

C2

Z

IN

C1

C3

R3

R2

R

S1

COMP

FB

OPEN LOOP

F

P1

F

Z1

Z2

P2

-

+

ERROR AMP GAIN

100

80

R

P1

V













ISL6521

IN

------------

20log

0.8V

V

PP

60

40

COMPENSATION

GAIN

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

20

0









R2

------------

20log



and Z . The goal of the compensation network is to provide

FB

R



S1

-20

-40

-60

a closed loop transfer function with high 0dB crossing

CLOSED LOOP

GAIN

MODULATOR

GAIN

frequency (f

) and adequate phase margin. Phase margin

F

ESR

0dB

LC

is the difference between the closed loop phase at f

and

0dB

10

100

1K

10K

100K

1M

10M

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 5. Use these guidelines for

locating the poles and zeros of the compensation network:

FREQUENCY (Hz)

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

Individual Output Disable

The PWM and linear controllers can independently be

shutdown.

2. Place 1 Zero Below Filter’s Double Pole (~75% F

ND

)

LC

3. Place 2

Zero at Filter’s Double Pole

ST

4. Place 1 Pole at the ESR Zero

ND

To disable the switching regulator, use an open-drain or

open-collector device capable of pulling the OCSET pin (with

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

the attached R

pull-up) below 1.25V. To minimize the

OCSET

possibility of OC trips at levels different than predicted, a

capacitor with a value of an order of magnitude

C

Compensation Break Frequency Equations

OCSET

larger than the output capacitance of the pull-down device,

has to be used in parallel with R (1nF recommended).

1

F

= ------------------------------------------------------

F

= -----------------------------------

OCSET

Z1

P1

2π × R2 × C1

C1 × C2



----------------------

×





Upon turn-off of the pull-down device, the switching regulator

undergoes a soft-start cycle.

2π × R

2



C1 + C2

1

F

= ----------------------------------------------------------

F

= -----------------------------------

Z2

P2

2π × (R + R3) × C3

2π × R3 × C3

To disable a particular linear controller, pull and hold the

respective FB pin above a typical threshold of 1.25V. One

way to achieve this task is by using a logic gate coupled

S1

8

ISL6521

through a small-signal diode. The diode should be placed as

between the MOSFETs and the load. Locate the PWM

controller close to the MOSFETs.

close to the FB pin as possible to minimize stray capacitance

to this pin. Upon turn-off of the pull-up device, the respective

output undergoes a soft-start cycle, bringing the output

within regulation limits. On regulators implementing this

feature, the parallel combination of the feedback resistors

has to be sufficiently high to allow ease of driving from the

external device. Considering the other restriction applying to

the upper range of this resistor combination (see ‘Output

Voltage Selection’ paragraph), it is recommended the values

of the feedback resistors on the linear regulator output meet

the following constraint:

The critical small signal components include the bypass

capacitor for VCC and the feedback resistors. Locate these

components close to their connecting pins on the control IC.

A multi-layer printed circuit board is recommended. Figure 7

shows the connections of the critical components in the

converter. Note that the capacitors C and C

each can

IN

OUT

represent numerous physical capacitors. Dedicate one

solid layer for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break

this plane into smaller islands of common voltage levels.

The power plane should support the input power and

output power nodes. Use copper filled polygons on the top

and bottom circuit layers for the PHASE nodes, but do not

unnecessarily oversize these particular islands. Since the

PHASE nodes are subjected to very high dv/dt voltages,

the stray capacitor formed between these islands and the

surrounding circuitry will tend to couple switching noise.

Use the remaining printed circuit layers for small signal

wiring. The wiring traces from the control IC to the

MOSFET gate and source should be sized to carry 2A peak

currents.

R

× R

P

S

---------------------

2kΩ <

< 5kΩ

+ R

S

P

Important Note When Using External Pass Devices

If the collector voltage to a linear regulator pass transistor

(Q3, Q4, or Q5 shown in Figure 7) is lost, the respective

regulator has to be shut down by pulling high its FB pin. This

measure is necessary in order to avoid possible damage to

the ISL6521 as a result of overheating. Overheating can

occur in such situations due to sheer power dissipation

inside the chip’s linear drivers.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

L

IN

+5V

IN

+

+12V

C

IN

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-

off transition of the upper PWM MOSFET. Prior to turn-off,

the upper MOSFET was carrying the full load current.

During the turn-off, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET or

Schottky diode. Any inductance in the switched current

path generates a large voltage spike during the switching

interval. Careful component selection, tight layout of the

critical components, and short, wide circuit traces minimize

the magnitude of voltage spikes.

C

VCC

VCC GND

OCSET

C

OCSET

R

OCSET

Q1

OUT

UGATE

PHASE

V

OUT2

L

V

OUT1

+

C

+

OUT2

DRIVE2

C

OUT1

CR1

Q3

LGATE

Q2

OUT3

+

V

OUT4

ISL6521

+

C

OUT3

DRIVE4

PGND

DRIVE3

C

OUT4

Q5

Q4

There are two sets of critical components in a DC-DC

converter using an ISL6521 controller. The switching power

components are the most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

+3.3V

KEY

IN

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

The power components and the controller IC should be

placed first. Locate the input capacitors, especially the high-

frequency ceramic decoupling capacitors, close to the power

switches. Locate the output inductor and output capacitors

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

9

ISL6521

Component Selection Guidelines

Output Capacitor Selection

V

– V

V

OUT

IN

F

OUT

∆V

= ∆I × ESR

------------------------------- ---------------

∆I =

×

OUT

× L

V

S

IN

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic load regulation requirements.

Additionally, the PWM converters require an output capacitor

to filter the current ripple. The load transient for some

embedded processors requires high quality capacitors to

supply the high slew rate (di/dt) current demands.

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values increase

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6521 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

interval required to slew the inductor current from an initial

current value to the post-transient current level. During this

interval the difference between the inductor current and the

transient current level must be supplied by the output

capacitor(s). Minimizing the response time can minimize the

output capacitance required.

PWM Output Capacitors

High performance embedded processors can produce

transient load rates above 1A/ns. High frequency capacitors

initially supply the transient current and slow the load rate-of-

change seen by the bulk capacitors. The bulk filter capacitor

values are generally determined by the ESR (effective series

resistance) and voltage rating requirements rather than

actual capacitance requirements.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

L

V

× I

TRAN

L

× I

TRAN

O

t

= -------------------------------

t

= ------------------------------

RISE

FALL

– V

V

IN

OUT

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient’s edge. An aluminum electrolytic capacitor’s ESR

value is related to the case size with lower ESR available in

larger case sizes. However, the equivalent series inductance

(ESL) of these capacitors increases with case size and can

reduce the usefulness of the capacitor to high slew-rate

transient loading. Unfortunately, ESL is not a specified

parameter. Work with your capacitor supplier and measure

the capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

where: I

is the transient load current step, t

is the

TRAN

response time to the application of load, and t

RISE

FALL

response time to the removal of load. Be sure to check both

of these equations at the minimum and maximum output

levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitors are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the

maximum input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 of the summation of the DC load current.

Linear Output Capacitors

The output capacitors for the linear regulators provide

dynamic load current. The linear controllers use dominant

pole compensation integrated into the error amplifier and are

insensitive to output capacitor selection. Output capacitors

should be selected for transient load regulation.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors can be

placed very close to the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

PWM Output Inductor Selection

The PWM converter requires an output inductor. The output

inductor is selected to meet the output voltage ripple

requirements and sets the converter’s response time to a

load transient. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current. The ripple voltage and current are approximated by

the following equations:

For a through-hole design, several electrolytic capacitors

may be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge-current at

power-up.

10

ISL6521

Transistors Selection/Considerations

+5V OR LESS

+

+5V

The ISL6521 can employ up to 5 external transistors. Two

N-channel MOSFETs are used in the synchronous-rectified

buck topology of PWM converter. The linear controllers can

each drive an NPN bipolar transistor as a pass element. All

VCC

BOOT

C

BOOT

ISL6521

Q1

UGATE

PHASE

these transistors should be selected based upon r

,

DS(ON)

current gain, saturation voltages, gate/base supply

NOTE:

≈ V -0.5V

V

GS

CC

requirements, and thermal management considerations.

VCC

CR1

LGATE

PGND

Q2

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the equations

below). The conduction losses are the main component of

power dissipation for the lower MOSFETs. Only the upper

MOSFET has significant switching losses, since the lower

device turns on and off into near zero voltage.

-

+

NOTE:

V

≈ V

CC

GS

GND

FIGURE 8. MOSFET GATE BIAS

Rectifier CR1 is a clamp that catches the negative inductor

swing during the dead time between the turn off of the lower

MOSFET and the turn on of the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to

omit the diode and let the body diode of the lower MOSFET

clamp the negative inductor swing, providing the body diode

is fast enough to avoid excessive negative voltage swings at

the PHASE pin. The diode's rated reverse breakdown

voltage must be greater than the maximum input voltage.

The equations below assume linear voltage-current

transitions and do not model power loss due to the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are dissipated by the ISL6521 and don't heat

the MOSFETs. However, large gate-charge increases the

switching time, t

which increases the upper MOSFET

SW

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

Linear Controller Transistor Selection

The main criteria for selection of transistors for the linear

regulators is package selection for efficient removal of heat.

The power dissipated in a linear regulator is:

P

= I × (V – V

OUT

)

LINEAR

O

IN

2

I

× r

× V

I

× V × t

× F

SW S

O

DS(ON)

OUT

O

IN

P

= ------------------------------------------------------------ + ----------------------------------------------------

UPPER

LOWER

V

2

Select a package and heatsink that maintains the junction

temperature below the rating with a the maximum expected

ambient temperature.

IN

2

I

× r

× (V – V

OUT

)

O

DS(ON)

IN

= --------------------------------------------------------------------------------

V

IN

If bipolar NPN transistors have to be used with the linear

controllers, insure the current gain at the given operating

Given the reduced available gate bias voltage (5V) logic-

level or sub-logic-level transistors have to be used for both

N-MOSFETs. Caution should be exercised with devices

V

is sufficiently large to provide the desired maximum

CE

output load current when the base is fed with the minimum

driver output current.

exhibiting very low V

characteristics, as the low gate

GS(ON)

threshold could be conducive to some shoot-through (due to

the Miller effect), in spite of the counteracting circuitry

present aboard the ISL6521.

11

ISL6521

ISL6521 DC-DC Converter Application Circuit

Figure 9 shows a power management application circuit for

powering an embedded processor. The circuit provides the

Intersil’s portfolio of multiple output controllers continues to

expand with new selections to better fit our customer’s

needs. Refer to our website for updated information:

www.intersil.com

processor core voltage (V

), the I/O voltage (V ), the

CORE I/O

clock voltage (V

), and memory voltage (V )

CLOCK

MEMORY

from a single +5V supply. A component selection table

provides the recommended component values at various

load current steps.

+5V

C2

+

C1

1µF

D1

C7

VCC

0.1µF

MA732

ISL6521

BOOT

R5

OCSET

DRIVE2

FB2

V

Q3

I/O

2.5V

C3

0.47µF

UGATE

PHASE

Q1

Q2

R6

V

CORE

1.5V

L

OUT

+

12.7kΩ

R7

C8

C11

5.9kΩ

10µF

+

LGATE

PGND

C4

C10

10µF

DRIVE3

FB3

V

CLOCK

3.3V

2.0kΩ

FB

R8

C5

R1

18.2kΩ

R9

COMP

C9

C12

10µF

5.9kΩ

C14

R12

100µF

R2

C6

+5V

R3

2.26kΩ

DRIVE4

FB4

Q4

V

MEMORY

R11

+

R10

C

13

14

GND

FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR AN EMBEDDED PROCESSOR

Component Selection Table

I

L

Q1

Q2

Q3

C1

C4

CC_INT

OUT

5A

7.5µH

Pulse P1172.103

IRF7910

FZT649

(1A or less)

1 x 1000µF

10MBZ1000M 10x12.5

1 x 1200µF

6.3MBZ1200M 8x16

10A

15A

20A

4.8µH

IRF7460

IRF7821

IRF7476

IRF7832

2SD1802

2 x 1000µF

2 x 1800µF

Sumida CDEP134

(3A or less)

10MBZ1000M 10x12.5

6.3MBZ1800M 10x16

1.6µH

Sumida CDEP134

2SD1802

(3A or less)

2 x 1800µF

10MBZ1800M 10x20

2 x 3300µF

6.3MBZ3300M 10x23

0.5µH

Pulse PG0006.601

2 x

IRF7821

2 x

IRF7832

2SD1802

(3A or less)

3 x 1500µF

10MBZ1500M 10x16

3 x 3300µF

6.3MBZ3300M10x23

12

ISL6521

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

SYMBOL

MIN

MAX

0.069

0.010

0.019

0.010

0.394

0.157

MIN

1.35

0.10

0.35

0.19

9.80

3.80

MAX

1.75

NOTES

AREA

E

A

A1

B

C

D

E

e

0.053

0.004

0.014

0.007

0.386

0.150

-

-B-

0.25

-

0.49

9

1

2

3

L

0.25

-

10.00

4.00

3

SEATING PLANE

A

4

-A-

o

D

h x 45

0.050 BSC

1.27 BSC

-

H

h

0.228

0.010

0.016

0.244

0.020

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

-C-

α

µ

5

e

A1

L

6

C

B

0.10(0.004)

N

α

16

7

M

S

B

o

0.25(0.010)

C

A

0

8

0

8

-

Rev. 1 02/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

13


型号：	ISL6521CBZ-T
厂家：	Intersil
描述：	PWM Buck DC-DC and Triple Linear Power Controller PWM降压型DC -DC和三线性电源控制器开关光电二极管控制器
文件：	总13页 (文件大小：602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6521CBZ-T [INTERSIL]

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