ISL6530EVAL2_技术文档

ISL6530

®

Data Sheet

November 15, 2004

FN9052.2

Dual 5V Synchronous Buck Pulse-Width

Modulator (PWM) Controller for DDRAM

Features

• Provides V

channel DDRAM memory systems

, V

, and V voltages for one- and two-

TT

DDQ REF

Memory V

and V Termination

DDQ

TT

The ISL6530 provides complete control and protection for

dual DC-DC converters optimized for high-performance

DDRAM memory applications. It is designed to drive low

cost N-channel MOSFETs in synchronous-rectified buck

• Excellent voltage regulation

- V

= 2.5V ±2% over full operating range

DDQ

= (V

÷2) ±1% over full operating range

± 30mV

REF

DDQ

- V = V

TT REF

topology to efficiently generate 2.5V V

for powering

DDQ

for DDRAM differential signalling,

• Supports ‘S3’ sleep mode

- V is held at V ÷2 via low power window regulator

DDRAM memory, V

REF

and V for signal termination. The ISL6530 integrates all of

TT

TT DDQ

to minimize wake-up time

the control, output adjustment, monitoring and protection

functions into a single package.

• Fast transient response

- Full 0% to 100% duty ratio

The V

DDQ

output of the converter is maintained at 2.5V

through an integrated precision voltage reference. The V

output is precisely regulated to 1/2 the memory power

supply, with a maximum tolerance of ±1% over temperature

REF

• Operates from +5V input

• Overcurrent fault monitor on VDD

- Does not require extra current sensing element

and line voltage variations. V accurately tracks V

.

TT REF

- Uses MOSFET’s r

DS(ON)

During V2_SD sleep mode, the V output is maintained by

TT

a low power window regulator.

• Drives inexpensive N-Channel MOSFETs

The ISL6530 provides simple, single feedback loop, voltage-

mode control with fast transient response. It includes two

phase-locked 300kHz triangle-wave oscillators which are

• Small converter size

- 300kHz fixed frequency oscillator

o

• 24 Lead, SOIC or 32 Lead, 5mm×5mm QFN

• Pb-Free Available (RoHS Compliant)

displaced 90 to minimize interference between the two

PWM regulators. The regulators feature error amplifiers with

a 15MHz gain-bandwidth product and 6V/µs slew rate which

enables high converter bandwidth for fast transient

performance. The resulting PWM duty ratio ranges from 0%

to 100%.

Applications

• V

, V , and VREF regulation for DDRAM memory

DDQ TT

systems

The ISL6530 protects against over-current conditions by

inhibiting PWM operation. The ISL6530 monitors the current

- Main Memory in AMD® Athlon™ and K8™, Pentium®

III, Pentium IV, Transmeta, PowerPC™, AlphaPC™, and

UltraSparc® based computer systems

in the V

regulator by using the r

of the upper

DDQ

DS(ON)

- Video memory in graphics systems

MOSFET which eliminates the need for a current sensing

resistor.

• High-power tracking DC-DC regulators

Ordering Information

TEMP

RANGE( C)

PKG.

DWG. #

o

PART NUMBER

PACKAGE

ISL6530CB*

0 to 70

24 Lead SOIC

M24.3

ISL6530CBZ*

(See Note)

0 to 70

24 Lead SOIC

(Pb-free)

M24.3

ISL6530CR*

0 to 70

32 Lead 5x5 QFN L32.5x5

ISL6530CRZ*

(See Note)

32 Lead 5x5 QFN L32.5x5

(Pb-free)

ISL6530EVAL1, 2

Evaluation Board

* Add “-T” suffix for tape and reel option.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding

compounds/die attach materials and 100% matte tin plate termination finish, which are

RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6530

Pinouts

24 LEAD (SOIC)

32 LEAD (QFN)

TOP VIEW

24

23

22

21

20

19

18

17

16

15

14

13

1

2

PGND1

LGATE1

PVCC1

OCSET/SD

V2_SD

PGOOD

COMP2

SENSE2

FB2

UGATE1

BOOT1

PHASE1

VREF

3

32 31 30 29 28 27 26 25

4

PHASE 1

PVCC1

OCSET/SD

V2_SD

PGOOD

COMP2

SENSE2

FB2

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

FB1

5

VREF

FB1

6

COMP1

SENSE1

VREF_IN

GNDA

7

8

COMP1

SENSE1

VREF_IN

GNDA

9

10

11

VCC

PHASE2

BOOT2

LGATE2

PGND2

UGATE2 12

GNDA

VCC

9

10 11 12 13 14 15 16

FN9052.2

2

November 15, 2004

ISL6530

Block Diagram

OCSET/SD

VCC

PGOOD

POWER-ON

RESET (POR)

+

-

SOFT-

START

BOOT1

40µA

OVER-

CURRENT

UGATE1

PHASE1

PWM

ERROR

AMP

COMPARATOR

GATE

CONTROL

LOGIC

INHIBIT

PWM

+

-

FB1

PVCC1

COMP1

0.8V

REFERENCE

LGATE1

SENSE1

VREF_IN

OSCILLATOR

PGND1

BOOT2

+

-

VREF

o

90 Phase

Shift

ERROR

AMP

UGATE2

+

-

FB2

PWM

GATE

CONTROL

LOGIC

-

+

COMP2

PHASE2

INHIBIT

PWM

COMPARATOR

VCC

WINDOW

SENSE2

V2_SD

REGULATOR

LGATE2

PGND2

GND

FN9052.2

November 15, 2004

3

ISL6530

Typical Application

+5V

PGOOD

R

OCSET

D

BOOT1

VCC

PGOOD

BOOT1

OCSET/SD

Q

RESET

1

UGATE1

C

BOOT1

GNDA

V

DDQ

PHASE1

L

OUT1

+5V

C

OUT1

PVCC1

Q

V2_SD

SLEEP

2

LGATE1

VREF_IN

PGND1

V

REF

(.5xV

ISL6530

)

DDQ

VREF

D

BOOT2

COMP1

BOOT2

Q

3

UGATE2

C

BOOT2

PHASE2

LGATE2

V

TT

L

FB1

OUT2

4

C

OUT2

R

FB1

SENSE1

COMP2

PGND2

SENSE2

FB2

R

FB2

FIGURE 1. TYPICAL APPLICATION FOR ISL6530

FN9052.2

November 15, 2004

4

ISL6530

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Thermal Resistance

θ

( C/W)

θ

( C/W)

CC

JA

JC

Boot Voltage, V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

- V

. . . . . . . . . . . . . . . . . . . . . . +7.0V

+0.3V

BOOTn

PHASEn

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Note 2). . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

65

33

N/A

4

CC

o

Operating Conditions

(SOIC - Lead tips only)

For Recommended soldering conditions see Tech Brief TB389.

Supply Voltage, V

CC

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 125 C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

the

JA

JC,

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions with Vcc = 5V, Unless Otherwise Noted

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

OCSET/SD = V

;

CC

-

5

-

mA

CC

UGATE1, UGATE2, LGATE1, and LGATE2

Open

Shutdown Supply

OCSET/SD = 0V

-

3

-

mA

POWER-ON RESET

Rising V

Threshold

V

= 4.5V

4.25

3.75

-

4.5

4.0

V

CC

OCSET/SD

Falling V

CC

OSCILLATOR

Free Running Frequency

REFERENCES

V

= 5

275

300

325

kHz

CC

%SENSE1

Reference Voltage

(V2 Error Amp Reference)

V

SENSE1 = 2.5V

49.5

50

-

50.5

VREF

V1 Error Amp Reference Voltage

Tolerance

-

2

-

%

V1 Error Amp Reference

ERROR AMPLIFIERS

DC Gain

V

= 5

CC

0.8

V

REF

-

82

15

6

-

dB

Gain-Bandwidth Product

Slew Rate

GBW

SR

MHz

V/µs

COMP = 10pF

WINDOW REGULATOR

Load Current

-

±10

±7

-

mA

%

Output Voltage Error

V2_SD = VCC; ±10mA load on V2

GATE DRIVERS

Upper Gate Source (UGATE1 and 2)

Upper Gate Sink (UGATE1 and 2)

Lower Gate Source (LGATE1 and 2)

Lower Gate Sink (LGATE1 and 2)

PROTECTION

I

V

= 5V, V

= 2.5V

-

-1

1

-

A

UGATE

CC

UGATE-PHASE

= 5V, V

UGATE

= 2.5V

I

UGATE

I

-1

2

LGATE

CC

LGATE

= 2.5V

I

LGATE

OCSET/SD Current Source

OCSET/SD Disable Voltage

I

V

= 4.5VDC

34

-

40

46

-

µA

OCSET

V

0.8

V

RESET

FN9052.2

5

November 15, 2004

ISL6530

Functional Pin Description

24 LEAD (SOIC)

32 LEAD (QFN)

TOP VIEW

24

23

22

21

20

19

18

17

16

15

14

13

1

2

PGND1

LGATE1

PVCC1

OCSET/SD

V2_SD

PGOOD

COMP2

SENSE2

FB2

UGATE1

BOOT1

PHASE1

VREF

3

32 31 30 29 28 27 26 25

4

PHASE 1

PVCC1

OCSET/SD

V2_SD

PGOOD

COMP2

SENSE2

FB2

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

FB1

5

VREF

FB1

6

COMP1

SENSE1

VREF_IN

GNDA

7

8

COMP1

SENSE1

VREF_IN

GNDA

9

10

11

VCC

PHASE2

BOOT2

LGATE2

PGND2

UGATE2 12

GNDA

VCC

9

10 11 12 13 14 15 16

(r

) set the V

converter over-current (OC) trip

DDQ

BOOT1 and BOOT2

DS(ON)

point according to the following equation:

These pins provide bias voltage to the upper MOSFET

drivers. A single capacitor bootstrap circuit may be used to

create a BOOT voltage suitable to drive a standard N-

Channel MOSFET.

I

• R

OCSET

OCS

I

= -------------------------------------------

PEAK

r

DS(ON)

An overcurrent trip cycles the soft-start function.

UGATE1 and UGATE2

Pulling the OCSET/SD pin to ground resets the ISL6530 and

all external MOSFETS are turned off allowing the two output

voltage power rails to float.

Connect UGATE1 and UGATE2 to the corresponding upper

MOSFET gate. These pins provide the gate drive for the

upper MOSFETs. UGATE2 is also monitored by the adaptive

shoot through protection to determine when the upper FET

PGOOD

of the V regulator has turned off.

TT

A high level on this open-drain output indicates that both the

V

and V regulators are within normal operating

DDQ

TT

LGATE1 and LGATE2

voltage ranges.

Connect LGATE1 and LGATE2 to the corresponding lower

MOSFET gate. These pins provide the gate drive for the

lower MOSFETs. These pins are monitored by the adaptive

shoot through protection to determine when the lower FET

has turned off.

GNDA

Signal ground for the IC. Tie this pin to the ground plane

through the lowest impedence connection available.

VCC

PGND1 and PGND2

The 5V bias supply for the chip is connected to this pin. This

pin is also the positive supply for the lower gate driver,

LGATE2. Connect a well decoupled 5V supply to this pin.

These are the power ground connections for the gate drivers

of the PWM controllers. Tie these pins to the ground plane

through the lowest impedence connection available.

V2_SD

OCSET/SD

A high level on the V2_SD input places the V2 controller into

“sleep” mode. In sleep mode, both UGATE2 and LGATE2

are driven low, effectively floating the V supply.

TT

A resistor (R

) connected from this pin to the drain of

the upper MOSFET of the V regulator sets the

OCSET

DDQ

, an internal 40µA current

overcurrent trip point. R

OCSET

source (I

), and the upper MOSFET on-resistance

OCS

FN9052.2

6

November 15, 2004

ISL6530

While the V supply “floats”, it is held to about 50% of

TT

300kHz clocks. The clocks are phase locked and displaced

90 to minimize noise coupling between the controllers.

o

V

via a low current window regulator which drives V

DDQ

TT

via the SENSE2 pin. The window regulator can overcome up

The first regulator includes a precision 0.8V reference and is

to at least ±10mA of leakage on V

.

TT

intended to provide the proper V

to a DDRAM memory

controller implements overcurrent

DDQ

While V2_SD is high, PGOOD is low.

system. The V

DDQ

protection utilizing the r

Following a fault condition, the V

via a digital softstart circuit.

of the upper MOSFET.

DS(ON)

PHASE1 and PHASE2

regulator is softstarted

DDQ

Connect PHASE1 and PHASE2 to the corresponding upper

MOSFET source. This pin is used as part of the upper

MOSFET bootstrapped drives. PHASE1 is used to monitor

the voltage drop across the upper MOSFET of the V

regulator for over-current protection. The PHASE1 pin is

Included in the ISL6530 is a precision V

reference

REF

is a buffered representation of .5xV

output. V

. V

REF

DDQ REF

DDQ

is derived via a precision internal resistor divider connected

to the SENSE1 terminal.

monitored by the adaptive shoot through protection circuitry

to determine when the upper FET of the V

turned off.

supply has

DDQ

The second PWM regulator is designed to provide V

TT

termination for the DDRAM signal lines. The reference to the

V

regulator is V . Thus the V regulator provides a

REF TT

TT

termination voltage equal to .5xV

FB1, COMP1, FB2, and COMP2

. The drain of the upper

DDQ

COMP1, COMP2, FB1, and FB2 are the available external

pins of the error amplifiers. The FB1 and FB2 pins are the

inverting inputs of each error amplifier and the COMP1 and

COMP2 pins are the associated outputs. An appropriate AC

network across these pins is used to compensate the

voltage-controlled feedback loop of each converter.

MOSFET of the V supply is connected to the regulated

TT

V

voltage. The V controller is designed to enable both

TT

DDQ

sinking and sourcing current on the V rail.

TT

Two benefits result from the ISL6530 dual controller

topology. First, as VREF is always .5xV

, the V supply

DDQ

TT

will track the V

DDQ

the overcurrent protection incorporated into the V

will simultaneously protect the V supply.

TT

supply during softstart cycles. Second,

supply

VREF and VREF_IN

DDQ

VREF produces a voltage equal to one half of the voltage on

SENSE1. This low current output is connected to the VREF

input of the DDRAM devices being powered. This same

Initialization

voltage is used as the reference input of the V error

The ISL6530 automatically initializes upon application of

input power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltage at the VCC pin. The

POR function initiates soft-start operation after the 5V bias

supply voltage exceeds its POR threshold.

TT

amplifier. Thus V is controlled to 50% of V

TT

.

DDQ

VREF_IN is used as an option to overdrive the internal

resistor divider network that sets the voltage for both

VREF_OUT and the reference voltage for the V supply. A

TT

100pF capacitor between VREF_IN and ground is

recommended for proper operation.

Soft-Start

The POR function initiates the digital soft start sequence. The

PWM error amplifier reference input for the VDDQ regulator is

clamped to a level proportional to the soft-start voltage. As the

soft-start voltage slews up, the PWM comparator generates

PHASE pulses of increasing width that charge the output

capacitor(s). This method provides a rapid and controlled

output voltage rise. The soft start sequence typically takes

about 7ms.

PVCC1

This is the positive supply for the lower gate driver, LGATE1.

PVCC1 is connected to a well decoupled 5V.

SENSE1 and SENSE2

Both SENSE1 and SENSE2 are connected directly to the

regulated outputs of the V

respectively. SENSE1 is used as an input to create the

voltage at VREF_OUT and the reference voltage for the V

supply. SENSE2 is used as the regulation point for the

window regulator that is enabled in V2_SD mode.

and V supplies,

DDQ

TT

1

2

TT

--

With the V regulator reference held at

TT

it will

⋅ V

DDQ

automatically track the ramp of the V

softstart, thus

DDQ

enabling a soft-start for V

.

TT

Figure 2 shows the soft-start sequence for a typical application.

At t0, the +5V VCC bias voltage starts to ramp. Once the

voltage on VCC crosses the POR threshold at time t1, both

outputs begin their soft-start sequence. The triangle waveforms

from the PWM oscillators are compared to the rising error

amplifier output voltage. As the error amplifier voltage

increases, the pulse-widths on the UGATE pins increase to

reach their steady-state duty cycle at time t2.

Functional Description

Overview

The ISL6530 contains control and drive circuitry for two

synchronous buck PWM voltage regulators. Both regulators

utilize 5V bootstrapped output topology to allow use of low

cost N-channel MOSFETs. The regulators are driven by

FN9052.2

7

November 15, 2004

ISL6530

When the V2_SD input of the ISL6530 is driven high, the

regulator is placed into a “sleep” state. In the sleep

V

TT

state the main V regulator is disabled, with both the

TT

VCC (5V)

upper and lower MOSFETs being turned off. The V bus

TT

(1V/DIV)

is maintained at close to .5xVdd via a low current window

regulator which drives V via the SENSE2 pin.

TT

Maintaining V at .5xV

TT

consumes negligible power

DDQ

and enables rapid wake-up from sleep mode without the

V

(2.5V)

DDQ

need of softstarting the V regulator. During this power

TT

down mode, PGOOD is held LOW.

V

(1.25V)

TT

Output Voltage Selection

0V

The output voltage of the V

regulator can be

DDQ

programmed to any level between V (i.e. +5V) and the

T2

T0

T1

IN

TIME

internal reference, 0.8V. An external resistor divider is used

to scale the output voltage relative to the reference voltage

and feed it back to the inverting input of the error amplifier,

see Figure 3. However, since the value of R1 affects the

values of the rest of the compensation components, it is

advisable to keep its value less than 5kΩ. R4 can be

calculated based on the following equation:

FIGURE 2. SOFT-START INTERVAL

Shoot-Through Protection

A shoot-through condition occurs when both the upper

MOSFET and lower MOSFET are turned on simultaneously,

effectively shorting the input voltage to ground. To protect

the regulators from a shoot-through condition, the ISL6530

incorporates specialized circuitry which insures that

complementary MOSFETs are not ON simultaneously.

R1 × 0.8V

R4 = -------------------------------------

V

– 0.8V

OUT1

If the output voltage desired is 0.8V, simply route VOUT1

back to the FB pin through R1, but do not populate R4.

The adaptive shoot-through protection utilized by the V

DDQ

regulator looks at the lower gate drive pin, LGATE1, and the

phase node, PHASE1, to determine whether a MOSFET is

ON or OFF. If PHASE1 is below 0.8V, the upper gate is

defined as being OFF. Similarly, if LGATE1 is below 0.8V, the

lower MOSFET is defined as being OFF. This method of

+5V

D1

VCC

BOOT1

shoot-through protection allows the V

source current only.

regulator to

DDQ

Due to the necessity of sinking current, the V regulator

TT

employs a modified protection scheme from that of the

C4

Q1

UGATE1

L

OUT

V

regulator. If the voltage from UGATE2 or from

DDQ

PHASE1

LGATE1

ISL6530

LGATE2 to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the other MOSFET is

turned ON.

Q2

+

C

OUT1

FB1

Since the voltage of the lower MOSFET gates and the upper

C1

R1

C3

MOSFET gate of the V supply are being measured to

COMP1

TT

R3

determine the state of the MOSFET, the designer is

encouraged to consider the repercussions of introducing

external components between the gate drivers and their

respective MOSFET gates before actually implementing

such measures. Doing so may interfere with the shoot-

through protection.

C2

R2

R4

FIGURE 3. OUTPUT VOLTAGE SELECTION OF V

DDQ

Power Down Mode

V

Reference Overdrive

TT

DDRAM systems include a sleep state in which the V

DDQ

The ISL6530 allows the designer to bypass the internal 50%

tracking of V that is used as the reference for V . The

voltage to the memories is maintained, but signaling is

suspended. During this mode the V termination voltage is

DDQ TT

TT

ISL6530 was designed to divide down the V voltage by

no longer needed. The only load placed on the V bus is

TT

the leakage of the associated signal pins of the DDRAM and

DDQ

50% through two internal matched resistances. These

resistances are typically 200kΩ.

memory controller ICs.

FN9052.2

November 15, 2004

8

ISL6530

One method that may be employed to bypass the internal

reference generation is to supply an external reference

programs the overcurrent trip level (see Figure 1). An internal

V

40µA (typical) current sink develops a voltage across R

TT

OCSET

that is referenced to V . When the voltage across the upper

directly to the V

pin. When doing this the SENSE1 pin

REF_IN

must remain unconnected. Caution must be exercised when

IN

MOSFET of V

voltage across R

(also referenced to V ) exceeds the

DDQ

IN

, the overcurrent function initiates a

using this method as the V regulator does not employ a

TT

OCSET

soft-start of its own.

soft-start sequence.

Figure 5 illustrates the protection feature responding to an

over current event on V . At time T0, an over current

A second method would be to overdrive the internal

resistors. Figure 4 shows how to implement this method. The

external resistors used to overdrive the internal resistors

should be less than 2kΩ and have a tolerance of 1% or

better. This method still supplies a buffer between the

DDQ

condition is sensed across the upper MOSFET of the V

DDQ

regulator. As a result, both regulators are quickly shutdown

and the internal soft-start function begins producing soft-

start ramps. The delay interval seen by the output is

equivalent to three soft-start cycles. The fourth internal soft-

start cycle initiates a normal soft-start ramp of the output, at

time T1. Both outputs are brought back into regulation by

time t2, as long as the overcurrent event has cleared.

resistor network and any loading on the V

pin. If there is

REF

pin, then no buffering is necessary

no loading on the V

REF

and the reference voltage created by the resistor network

can be tied directly to V

.

REF

V

DDQ

ISL6530

Had the cause of the overcurrent still been present after the

delay interval, the overcurrent condition would be sensed

and both regulators would be shut down again for another

delay interval of three soft-start cycles. The resulting hiccup

mode style of protection would continue to repeat

indefinitely.

SENSE1

VREF_IN

R

A

VREF

+

-

B

V

(2.5V)

DDQ

TO ERROR

AMPLIFIER

V

(1.25V)

TT

FIGURE 4. V REFERENCE OVERDRIVE

TT

Converter Shutdown

Pulling and holding the OCSET/SD pin below 0.8V will

shutdown both regulators. During this state, PGOOD will be

held LOW. Upon release of the OCSET/SD pin, the IC enters

into a soft start cycle which brings both outputs back into

regulation.

0V

INTERNAL SOFT-START FUNCTION

DELAY INTERVAL

Voltage Monitoring

The ISL6530 offers a PGOOD signal that will communicate

whether the regulation of both V

and V are within

DDQ

TT

±15% of regulation, the V2_SD pin is held low and the bias

voltage of the IC is above the POR level. If all the criteria

above are true, the PGOOD pin will be at a high impedence

level. When one or more of the criteria listed above are false,

the PGOOD pin will be held low.

T0

T1

T2

TIME

FIGURE 5. OVERCURRENT PROTECTION RESPONSE

Overcurrent Protection

The overcurrent function will trip at a peak inductor current

The overcurrent function protects the converter from a shorted

(I

determined by:

PEAK)

output by using the upper MOSFET on-resistance, r

, of

DS(ON)

V

to monitor the current. This method enhances the

I

x R

OCSET OCSET

DDQ

I

= ----------------------------------------------------

PEAK

converter’s efficiency and reduces cost by eliminating a

current sensing resistor.

r

DS(ON)

where I

OCSET

is the internal OCSET current source (40µA

The over-current function cycles the soft-start function in a

typical). The OC trip point varies mainly due to the MOSFET

hiccup mode to provide fault protection. A resistor (R

)

OCSET

FN9052.2

9

November 15, 2004

ISL6530

r

variations. To avoid over-current tripping in the

DS(ON)

+5V

normal operating load range, find the R

the equation above with:

resistor from

OCSET

ISL6530

1. The maximum r

2. The minimum I

at the highest junction temperature.

DS(ON)

UGATE1

PHASE1

V

DDQ

from the specification table.

OCSET

LGATE1

(∆I)

2

I

> I

+ ----------

,

OUT(MAX)

3. Determine I

PEAK

for

PEAK

DDR

SDRAM

where ∆I is the output inductor ripple current.

UGATE2

PHASE2

+

-

For an equation for the ripple current see the section under

component guidelines titled Output Inductor Selection.

V

TT

R

T

LGATE2

V

REF

A small ceramic capacitor should be placed in parallel with

R

to smooth the voltage across

R

in the

OCSET

presence of switching noise on the input voltage.

FIGURE 6. V CURRENT SINKING LOOP

TT

Current Sinking

Application Guidelines

The ISL6530 V regulator incorporates a MOSFET shoot-

TT

Layout Considerations

through protection method which allows the converter to sink

current as well as source current. Care should be exercised

when designing a converter with the ISL6530 when it is

known that the converter may sink current.

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

300kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit board design minimizes the voltage

spikes in the converters.

When the converter is sinking current, it is behaving as a

boost converter that is regulating its input voltage. This

means that the converter is boosting current into the input

rail of the regulator. If there is nowhere for this current to go,

such as to other distributed loads on the rail or through a

voltage limiting protection device, the capacitance on this rail

will absorb the current. This situation will allow the voltage

level of the input rail to increase. If the voltage level of the rail

is boosted to a level that exceeds the maximum voltage

rating of any components attached to the input rail, then

those components may experience an irreversible failure or

experience stress that may shorten their lifespan. Ensuring

that there is a path for the current to flow other than the

capacitance on the rail will prevent this failure mode.

As an example, consider the turn-off transition of the PWM

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the lower MOSFET. Any

parasitic inductance in the switched current path generates a

large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide traces minimizes the magnitude of voltage

spikes.

To insure that the current does not boost up the input rail

There are two sets of critical components in a DC-DC

converter using the ISL6530. The switching components are

the most critical because they switch large amounts of

energy, and therefore tend to generate large amounts of

noise. Next are the small signal components which connect

to sensitive nodes or supply critical bypass current and

signal coupling.

voltage of the V regulator, it is recommended that the

TT

input rail of the V regulator be the output of the V

TT

DDQ

regulator. The current being sunk by the V regulator will

TT

be fed into the V

DDQ

rail and then drawn into the DDR

SDRAM memory module and back into the V regulator.

TT

Figure 6 shows the recommended configuration and the

resulting current loop.

A multi-layer printed circuit board is recommended. Figure 7

shows the connections of the critical components in the

converter. Note that capacitors C and C

could each

IN OUT

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

FN9052.2

10

November 15, 2004

ISL6530

nodes. Use copper filled polygons on the top and bottom

The switching components should be placed close to the

ISL6530 first. Minimize the length of the connections

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from

the GATE pins to the MOSFET gates should be kept short

and wide enough to easily handle the 1A of drive current.

between the input capacitors, C , and the power switches

IN

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain as

possible. Position the output inductor and output capacitors

between the upper MOSFET and lower diode and the load.

+5V V

IN

ISL6530

VCC

The critical small signal components include any bypass

capacitors, feedback components, and compensation

C

BP

C

D1

IN

GND

components. Position the bypass capacitor, C , close to the

BP

VCC pin with a via directly to the ground plane. Place the

PWM converter compensation components close to the FB

and COMP pins. The feedback resistors for both regulators

should also be located as close as possible to the relevant

FB pin with vias tied straight to the ground plane as required.

BOOT1

C

BOOT1

Q1

Q2

UGATE1

PHASE1

L

OUT1

V

PHASE1

DDQ

Feedback Compensation

Figure 8 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

C

LGATE1

PGND1

COMP1

OUT1

(V

) is regulated to the Reference voltage level. The

OUT

error amplifier (Error Amp) output (V ) is compared with

E/A

C

2A

the oscillator (OSC) triangular wave to provide a pulse-

C

1A

R

2A

R

width modulated (PWM) wave with an amplitude of V at

1A

IN

FB1

the PHASE node. The PWM wave is smoothed by the output

C

R

3A

R4

filter (L and C ).

O

SENSE1

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

+5V V

OUT E/A

Gain and the output filter (L and C ), with a double pole

IN

D2

O

V

DDQ

Q3

break frequency at F and a zero at F

. The DC Gain of

LC ESR

BOOT2

the modulator is simply the input voltage (V ) divided by the

IN

C

BOOT2

peak-to-peak oscillator voltage ∆V

OSC

UGATE2

PHASE2

L

OUT2

Modulator Break Frequency Equations

V

PHASE2

TT

1

F

= -----------------------------------------

F

= ------------------------------------------

LC

ESR

2π x ESR x C

Q4

2π x

L

x C

O O

O

C

LGATE2

PGND2

OUT2

The compensation network consists of the error amplifier

(internal to the ISL6530) and the impedance networks Z

IN

COMP1

C

and Z . The goal of the compensation network is to provide

2B

FB

C

1B

a closed loop transfer function with the highest 0dB crossing

R

2B

R

1B

frequency (f

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f and

FB1

0dB

C

R

3B

0dB

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R , R ,

SENSE2

1

2

R , C , C , and C ) in Figure 7. Use these guidelines for

3

1

2

3

locating the poles and zeros of the compensation network:

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

1. Pick gain (R /R ) for desired converter bandwidth.

2

1

2. Place first zero below filter’s double pole (~75% F ).

LC

VIA CONNECTION TO GROUND PLANE

3. Place second zero at filter’s double pole.

4. Place first pole at the ESR zero.

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin - repeat if necessary.

FN9052.2

November 15, 2004

11

ISL6530

.

V

IN

DRIVER

OPEN LOOP

ERROR AMP GAIN

F

P1

F

OSC

Z1

Z2

P2

PWM

100

80

L

O

COMPARATOR

V

OUT

V













IN

---------------

20log

-

PHASE

V

+

DV

OSC

C

O

OSC

60

ESR

(PARASITIC)

40

COMPENSATION

GAIN

Z

FB

20

V

E/A

Z

-

IN

0

+

R2







-------

20log



R1

REFERENCE

ERROR

AMP

-20

-40

-60

MODULATOR

GAIN

LOOP GAIN

10M

F

ESR

LC

DETAILED COMPENSATION COMPONENTS

Z

FB

10

100

1K

10K

100K

1M

V

OUT

C

1

Z

FREQUENCY (Hz)

IN

C

R

3

2

3

2

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

R

1

COMP

Component Selection Guidelines

FB

Output Capacitor Selection

-

+

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

ISL6530

REFERENCE

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Compensation Break Frequency Equations

Modern digital ICs can produce high transient load slew

rates. High-frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

1

F

= ----------------------------------

F

= --------------------------------------------------------

Z1

Z2

P1

P2

2π × R × C

C

x C

2













1

2

---------------------

2π x R

x

2

C

+ C

2

1

F

= ------------------------------------------------------

2π x (R + R ) x C

= -----------------------------------

2π x R x C

3

1

3

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

Figure 9 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual modulator gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 9. Using the above guidelines should give a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

compensation gain at F with the capabilities of the error

P2

amplifier. The closed loop gain is constructed on the graph of

Figure 9 by adding the modulator gain (in dB) to the

compensation gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

FN9052.2

12

November 15, 2004

ISL6530

conservative guideline. The RMS current rating requirement

Output Inductor Selection

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

The maximum RMS current required by the regulator may be

closely approximated through the following equation:

2

 

V_OUT

-------------

V_IN

V

_IN– V_OUTV_OUT

2

1





 

------ ---------------------------- -------------

I_RMS

=

× I_OUT

+

×



12

L × f_s

V_IN

MAX

V

- V

IN OUT

V

OUT

∆V

OUT

= ∆I x ESR

∆I =

x

f x L

V

IN

s

For a through-hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge currentrating. These capacitors

must be capable of handling the surge-current at power-up.

Some capacitor series available from reputable manufacturers

are surge current tested.

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6530 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection/Considerations

The ISL6530 requires two N-Channel power MOSFETs for

each PWM regulator. These should be selected based upon

r

, gate supply requirements, and thermal management

DS(ON)

requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed between

the two MOSFETs according to duty factor. The switching

losses seen when sourcing current will be different from the

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

L x I

TRAN

- V

t

=

t

=

FALL

RISE

switching losses seen when sinking current. The V

DDQ

V

OUT

IN OUT

regulator will only source current while the V regulator can

TT

sink and source. When sourcing current, the upper MOSFET

realizes most of the switching losses. The lower switch realizes

most of the switching losses when the converter is sinking

current (see the equations below). These equations assume

linear voltage-current transitions and do not adequately model

power loss due the reverse-recovery of the upper and lower

MOSFET’s body diode. The gate-charge losses are dissipated

by the ISL6530 and don't heat the MOSFETs. However, large

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

FALL

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

Input Capacitor Selection

gate-charge increases the switching interval, t which

SW

increases the MOSFET switching losses.

LOSSES WHILE SOURCING CURRENT

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

2

1

--

× D + ⋅ Io × V × t

P

= Io × r

× f

to supply the current needed each time Q turns on. Place the

UPPER

DS(ON)

IN SW s

1

2

small ceramic capacitors physically close to the MOSFETs

P

= Io x r

x (1 - D)

LOWER

DS(ON)

and between the drain of Q and the source of Q .

1

2

LOSSES WHILE SINKING CURRENT

2

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

P

= Io x r

2

x D

DS(ON)

UPPER

1

2

--

× (1 – D) + ⋅ Io × V × t

P

= Io × r

× f

s

LOWER

DS(ON)

IN SW

Where: D is the duty cycle = V ,

/ V

is the combined switch ON and OFF time, and

OUT IN

t

SW

f is the switching frequency.

s

FN9052.2

13

November 15, 2004

ISL6530

Ensure that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature and air flow.

The bootstrap capacitor begins its refresh cycle when the

gate drive begins to turn-off the upper MOSFET. A refresh

cycle ends when the upper MOSFET is turned on again,

which varies depending on the switching frequency and

duty cycle.

The minimum bootstrap capacitance can be calculated by

Given the reduced available gate bias voltage (5V), logic-

level or sub-logic-level transistors should be used for both N-

MOSFETs. Caution should be exercised when using devices

rearranging the previous equation and solving for C

.

BOOT

Q

GATE

----------------------------------------------------

C

≥

BOOT

V

– V

BOOT1

BOOT2

with very low gate thresholds (V ). The shoot-through

TH

protection circuitry may be circumvented by these

Typical gate charge values for MOSFETs considered in

these types of applications range from 20 to 100nC. Since

the voltage drop across Q is negligible, V is

MOSFETs. Very high dv/dt transitions on the phase node

may cause the Miller capacitance to couple the lower gate

with the phase node and cause an undesireable turn on of

the lower MOSFET while the upper MOSFET is on.

LOWER BOOT1

simply VCC - V . A Schottky diode is recommended to

D

minimize the voltage drop across the bootstrap capacitor

during the on-time of the upper MOSFET. Initial calculations

Bootstrap Component Selection

with V

no less than 4V will quickly help narrow the

External bootstrap components, a diode and capacitor, are

required to provide sufficient gate enhancement to the upper

MOSFET. The internal MOSFET gate driver is supplied by

the external bootstrap circuitry as shown in Figure 10. The

BOOT2

bootstrap capacitor range.

For example, consider an upper MOSFET is chosen with a

maximum gate charge, Q , of 100nC. Limiting the voltage

drop across the bootstrap capacitor to 1V results in a value

of no less than 0.1µF. The tolerance of the ceramic capacitor

should also be considered when selecting the final bootstrap

capacitance value.

g

boot capacitor, C

, develops a floating supply voltage

BOOT

referenced to the PHASE pin. This supply is refreshed each

cycle, when D conducts, to a voltage of VCC less the

BOOT

boot diode drop, V , plus the voltage rise across Q

D

.

LOWER

VCC

A fast recovery diode is recommended when selecting a

bootstrap diode to reduce the impact of reverse recovery

D

BOOT

+

V

-

V

IN

D

charge loss. Otherwise, the recovery charge, Q , would

RR

have to be added to the gate charge of the MOSFET and

taken into consideration when calculating the minimum

bootstrap capacitance.

BOOTn

C

ISL6530

BOOT

UGATEn

PHASEn

Q

UPPER

NOTE:

ª V

V

-V

D

G-S

CC

LGATEn

LOWER

-

+

NOTE:

ª V

V

G-S

CC

GND

FIGURE 10. UPPER GATE DRIVE BOOTSTRAP

Just after the PWM switching cycle begins and the charge

transfer from the bootstrap capacitor to the gate capacitance

is complete, the voltage on the bootstrap capacitor is at its

lowest point during the switching cycle. The charge lost on

the bootstrap capacitor will be equal to the charge

transferred to the equivalent gate-source capacitance of the

upper MOSFET as shown:

Q

= C

× (V

– V

)

BOOT2

GATE

BOOT

BOOT1

where Q

is the maximum total gate charge of the upper

GATE

MOSFET, C

BOOT

is the bootstrap capacitance, V

is

BOOT1

the bootstrap voltage immediately before turn-on, and

V

is the bootstrap voltage immediately after turn-on.

BOOT2

FN9052.2

November 15, 2004

14

ISL6530

ISL6530 DC-DC Converter Application Circuit

Figure 11 shows an application circuit for a DDR SDRAM

of-Materials and circuit board description, can be found in

power supply, including V (+2.5V) and V (+1.25V).

Application Note AN9993.

DDQ TT

Detailed information on the circuit, including a complete Bill-

+5V

C

0.1µF

R

C

2

1

3.48kΩ

1000pF

D

1

C

3

4,5

150µF(x2)

OCSET/SD

VCC

1.0µF

BOOT1

V2_SD

Q

1

PGOOD

VREF

UGATE1

PHASE1

C

0.1µF

6

V

DDQ

@10A

L

1µH

1

VREF_IN

GNDA

C

PVCC1

7,8,9,10

150µF(x4)

Q

C

2

30

100pF

LGATE1

C

15

0.1µF

PGND1

ISL6530

D

2

C

26

5600pF

COMP1

BOOT2

C

17

1.0µF

C

R

27

100pF

26

UGATE2

6.34kΩ

C

16

0.1µF

V

TT

@5A

L

1µH

FB1

PHASE2

LGATE2

2

R

19

3.01kΩ

C

R

18,19

150µF(x2)

20

1.43kΩ

Q

3

C

25

15000pF

PGND2

SENSE1

COMP2

FB2

SENSE2

R

25

100Ω

C

68pF

R

24

21

3.01kΩ

R

23

8.87kΩ

22

158Ω

C

10000pF

2700pF

22

23

Component Selection Notes:

C4,5,7,8,9,10,18,19 - Each 150mF, Panasonic EEF-UE0J151R

D1,2 - Each 30mA Schottky Diode, MA732

Q1,2 - Each Fairchild MOSFET; ITF86130DK8

Q3 - Fairchild MOSFET; ITF86110DK8

L1,2 - Each 1mH Inductor, Panasonic P/N ETQ-P6F1ROSFA

FIGURE 11. DDR SDRAM VOLTAGE REGULATOR

FN9052.2

November 15, 2004

15

Small Outline Plastic Packages (SOIC)

N

M24.3 (JEDEC MS-013-AD ISSUE C)

INDEX

AREA

0.25(0.010)

M

B M

H

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

0.30

0.51

0.32

15.60

7.60

NOTES

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.020

-

1

2

3

L

-

9

SEATING PLANE

A

0.0091

0.5985

0.2914

0.0125

-

-A-

o

h x 45

D

0.6141 15.20

3

0.2992

7.40

4

-C-

α

µ

0.05 BSC

1.27 BSC

-

e

A1

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

C

B

0.10(0.004)

5

0.25(0.010) M

C A M B S

L

6

N

α

24

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN9052.2

16

November 15, 2004

ISL6530

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L32.5x5

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.18

2.95

0.23

0.30

3.25

5,8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7,8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7,8

0.50 BSC

-

k

0.25

0.30

-

L

0.40

0.50

0.15

8

L1

N

-

32

8

-

10

2

Nd

Ne

P

3

8

-

3

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9052.2

17

November 15, 2004


型号：	ISL6530EVAL2
厂家：	Intersil
描述：	Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination 5V双路同步降压型脉宽调制器（PWM ）控制器，用于DDRAM内存VDDQ和VTT终端动态存储器双倍数据速率控制器
文件：	总17页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6530EVAL2 [INTERSIL]

相关型号：

ISL6531

ISL6531CB

ISL6531CB-T

ISL6531CBZ

ISL6531CBZ-T

ISL6531CR

ISL6531CR-T

ISL6531EVAL1

ISL6532

ISL6532A

ISL6532ACR

ISL6532ACR-T