ISL6753 [INTERSIL]
ZVS Full-Bridge PWM Controller; ZVS全桥PWM控制器![ISL6753](http://pdffile.icpdf.com/pdf1/p00082/img/icpdf/ISL6753_431886_icpdf.jpg)
型号: | ISL6753 |
厂家: | ![]() |
描述: | ZVS Full-Bridge PWM Controller |
文件: | 总15页 (文件大小:457K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISL6753
®
Data Sheet
March 10, 2005
FN9182.1
ZVS Full-Bridge PWM Controller
Features
The ISL6753 is a high-performance, low-pin-count
alternative zero-voltage switching (ZVS) full-bridge PWM
controller. Like the ISL6551, it achieves ZVS operation by
driving the upper bridge FETs at a fixed 50% duty cycle while
the lower bridge FETS are trailing-edge modulated with
adjustable resonant switching delays. Compared to the more
familiar phase-shifted control method, this algorithm offers
equivalent efficiency and improved overcurrent and light-
load performance with less complexity in a lower pin count
package.
• Adjustable Resonant Delay for ZVS Operation
• Voltage- or Current-Mode Operation
• 3% Current Limit Threshold
• 175µA Startup Current
• Supply UVLO
• Adjustable Deadtime Control
• Adjustable Soft-Start
• Adjustable Oscillator Frequency Up to 2MHz
This advanced BiCMOS design features low operating
current, adjustable oscillator frequency up to 2MHz,
adjustable soft-start, internal over temperature protection,
precision deadtime and resonant delay control, and short
propagation delays. Additionally, Multi-Pulse Suppression
ensures alternating output pulses at low duty cycles where
pulse skipping may occur.
• Tight Tolerance Error Amplifier Reference Over Line,
Load, and Temperature
• 5MHz GBWP Error Amplifier
• Adjustable Cycle-by-Cycle Peak Current Limit
• Fast Current Sense to Output Delay
• 70ns Leading Edge Blanking
Ordering Information
• Multi-Pulse Suppression
TEMP. RANGE
(°C)
PKG.
PART NUMBER
PACKAGE
DWG. #
• Buffered Oscillator Sawtooth Output
• Internal Over Temperature Protection
• Pb-free and ELV, WEEE, RoHS Compliant
ISL6753AAZA
(See Note)
-40 to 105
16 Ld QSOP
(Pb-free)
M16.15A
Add -T suffix to part number for tape and reel packaging
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
Pinout
ISL6753 (QSOP)
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VERR
CTBUF
RTD
VREF
SS
VDD
OUTLL
OUTLR
OUTUL
OUTUR
GND
RESDEL
CT
FB
RAMP
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD
VDD
OUTUL
OUTUR
50%
VREF
UVLO
PWM
STEERING
LOGIC
OVER-
TEMPERATURE
PROTECTION
OUTLL
OUTLR
PWM
GND
VREF
+
CS
-
1.00V
70 nS
LEADING
EDGE
OVER CURRENT
COMPARATOR
RESDEL
BLANKING
80mV
+
RAMP
-
0.33
PWM
OSCILLATOR
COMPARATOR
CT
VREF
1 mA
VREF
RTD
VERR
FB
CTBUF
SS
+
0.6V
SOFTSTART
CONTROL
-
Typical Application - High Voltage Input ZVS Full-Bridge Converter
P1
VIN+
Q1
FQB6N50
Q2
T3
P0544
FQB6N50
C17
100pF
250V
COG
R18
10
4
5
6
3
5%
Q5
3
2
3
2
2512
Q6
BSS138LT1
BSS138LT1
1
1
R16
10.0k
R13
10.0k
R15
R14
4.99
0805
8
1
CR3
CR4
4.99
+
+
SS12
SS12
0805
15, 16
Ns
T1
C1-C4
33uF
450V
2
1,C
2, 3
CR5
+
+
R1
4.7k
5%
CSD10060G
13, 14
11, 12
P4
300 - 400
VDC
Np
RETURN
7,8
5,6
7,8
5,6
C13
0.1uF
CR6
2512
CSD10060G
Ns
1
3
1
3
Q9
6, 7
Q10
2
2
4
ZXTDB2M832
R2
4.7k
5%
ZXTDB2M832
L1
9, 10
+
PB2020.103
4
2
C18
1uF
100V
1210
R28
10.0k
2512
1,C
2512
+
C19
1uF
C20
C21
470uF
63V
470uF
63V
R3
4.7k
5%
100V
1210
P3
Q4
FQB6N50
+ Vout
2512
(48V@10A)
7,8
5,6
7,8
5,6
C16
R19
10
100pF
250V
COG
1
1
3
2
4
2
4
2512
C12
1.0uF
Q3
C22
C23
FQB6N50
R17
10.0
4700pF
250VAC
SAFETY
4700pF
3
250VAC
SAFETY
Q8
ZXTDB2M832
P2
VIN-
Q7
ZXTDB2M832
8
7
U1
ISL6753
2
1
3
R27
3
1
10.0k
0805
T2
R11
VERR
VREF
SS
P8205
3.65k
R25
CTBUF
37.4k
0805
R21
R26
10.0k
0805
C15
220pF
CR1
3.74k
1206
RTD
VDD
BAV70
R8
R5
OUTLL
OUTLR
OUTUL
OUTUR
GND
RESDEL
CT
45.3k
100k
1206
R22
3.74k
1206
CR7
BAT54
R4
FB1
3
1
4.7k
5%
U2
PS2701-1P
R20
499
RAMP
CS
2512
4
3
1
2
2
R6
R24
100k
R9
C14
5.11k
499
4.7nF
2
3
Q11
1
R12
20.0k
MJD50
CR2
BAT54C
3
1
1
3
1
BIAS
VR2
BZX84-C6V8
U3
R29
20.0k
R30
20.0k
2
3
2
C6
R7A, B
180pF
3
1
18.7
R23
5% COG
C5
0.1uF
0805
1.10k
C10
C11
C8
1.0nF
C9
0.47uF
C7
VR1
R10
10.0k
0.1uF
0.1uF
47pF
BZX84-C12
ISL6753
Absolute Maximum Ratings
Thermal Information
Thermal Resistance Junction to Ambient (Typical)
16 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . .-55°C to 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(QSOP- Lead Tips Only)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
θ
(°C/W)
95
JA
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
+ 0.3V
REF
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Operating Conditions
Temperature Range
ISL6753AAxx . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9 V < VDD< 20 V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C
A
PARAMETER
SUPPLY VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
-
-
20
400
15.5
9.00
7.50
-
-
µA
mA
V
Start-Up Current, IDD
Operating Current, IDD
UVLO START Threshold
UVLO STOP Threshold
Hysteresis
VDD = 5.0V
, C
-
-
175
11.0
8.75
7.00
1.75
R
= 0
LOAD OUT
8.00
6.50
-
V
V
REFERENCE VOLTAGE
Overall Accuracy
I
= 0 - -10mA
4.850
-
5.000
5.150
V
VREF
Long Term Stability
Operational Current (source)
Operational Current (sink)
Current Limit
T
= 125°C, 1000 hours (Note 4)
3
-
-
mV
mA
mA
mA
A
-10
5
-
-
-
VREF = 4.85V
-15
-
-100
CURRENT SENSE
Current Limit Threshold
CS to OUT Delay
VERR = VREF
Excl. LEB (Note 4)
(Note 4)
0.97
1.00
1.03
50
V
ns
ns
ns
Ω
-
50
-
35
70
-
Leading Edge Blanking (LEB) Duration
CS to OUT Delay + LEB
100
130
20
T
= 25°C
A
CS Sink Current Device Impedance
Input Bias Current
V
V
= 1.1V
= 0.3V
-
-
CS
CS
-1.0
-
1.0
µA
RAMP
RAMP Sink Current Device Impedance
RAMP to PWM Comparator Offset
V
= 1.1V
-
-
20
95
Ω
RAMP
T
= 25°C
65
80
mV
A
FN9182.1
March 10, 2005
4
ISL6753
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9 V < VDD< 20 V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C (Continued)
A
PARAMETER
TEST CONDITIONS
MIN
-5.0
6.5
TYP
MAX
-2.0
8.0
UNITS
µA
Bias Current
V
= 0.3V
-
-
RAMP
Clamp Voltage
(Note 4)
V
PULSE WIDTH MODULATOR
Minimum Duty Cycle
VERR < 0.6V
-
-
0
%
%
Maximum Duty Cycle (per half-cycle)
VERR = 4.20V, V
= 0V,
RAMP
V
= 0V (Note 5)
-
-
-
94
97
99
-
-
-
CS
RTD = 2.00kΩ, CT = 220pF
RTD = 2.00kΩ, CT = 470pF
Zero Duty Cycle VERR Voltage
VERR to PWM Comparator Input Offset
VERR to PWM Comparator Input Gain
Common Mode (CM) Input Range
ERROR AMPLIFIER
0.85
0.7
0.31
0
-
0.8
0.33
-
1.20
0.9
V
V
T
= 25°C
A
0.35
V/V
V
(Note 4)
V
SS
Input Common Mode (CM) Range
GBWP
(Note 4)
(Note 4)
0
5
-
VREF
-
V
MHz
V
-
-
VERR VOL
I
I
= 2mA
= 0mA
-
0.4
LOAD
LOAD
VERR VOH
4.20
0.8
-
-
V
VERR Pull-Up Current Source
EA Reference
VERR = 2.5V
= 25°C
1.0
0.600
0.600
1.3
mA
V
T
0.594
0.590
0.606
0.612
A
EA Reference + EA Input Offset Voltage
OSCILLATOR
V
Frequency Accuracy, Overall
(Note 4)
165
-10
-
183
0.3
201
+10
1.7
kHz
%
Frequency Variation with VDD
Temperature Stability
T
= 25°C, (F
- - F
)/F
0°C 0°C
%
A
20V
10V 10V
VDD = 10V, |F
- F |/F
-
-
4.5
1.5
-
-
%
-40°C
|/F
|F
0°C
- F
105°C 25°C
(Note 4)
= 25°C
Charge Current
T
-193
19
-200
20
-207
23
µA
A
Discharge Current Gain
CT Valley Voltage
CT Peak Voltage
CT Pk-Pk Voltage
RTD Voltage
µA/µA
Static Threshold
Static Threshold
Static Value
0.75
2.75
1.92
1.97
0
0.80
2.80
2.00
2.00
-
0.88
2.88
2.05
2.03
2
V
V
V
V
RESDEL Voltage Range
V
CTBUF Gain (V
/V
CTBUFp-p CTp-p
)
V
V
= 0.8V, 2.6V
= 0.8V
1.95
0.34
-
2.0
0.40
-
2.05
0.44
0.10
V/V
V
CT
CT
CTBUF Offset from GND
CTBUF VOH
∆V(I
V
= 0mA, I
= -2mA),
= 0mA),
V
LOAD
= 2.6V
LOAD
LOAD
CT
CTBUF VOL
∆V(I
V
= 2mA, I
-
-
0.10
V
LOAD
= 0.8V
CT
FN9182.1
March 10, 2005
5
ISL6753
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9 V < VDD< 20 V, RTD = 10.0kΩ, CT = 470pF, T = -40°C to 105°C (Note 3), Typical values are at
A
T
= 25°C (Continued)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Charging Current
SS Clamp Voltage
SS = 3V
-60
4.410
10
-70
4.500
-
-80
4.590
-
µA
V
SS Discharge Current
Reset Threshold Voltage
OUTPUTS
SS = 2V
= 25°C
mA
V
T
0.23
0.27
0.33
A
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Rise Time
I
I
= -10mA, VDD - VOH
-
-
-
-
-
0.5
0.5
110
90
-
1.0
1.0
V
V
OUT
OUT
= 10mA, VOL - GND
C
= 220pF, VDD = 15V(Note 4)
= 220pF, VDD = 15V(Note 4)
200
150
1.25
ns
ns
V
OUT
OUT
Fall Time
C
UVLO Output Voltage Clamp
THERMAL PROTECTION
Thermal Shutdown
VDD = 7V, I
= 1mA (Note 6)
LOAD
(Note 4)
(Note 4)
(Note 4)
130
115
-
140
125
15
150
135
-
°C
°C
°C
Thermal Shutdown Clear
Hysteresis, Internal Protection
NOTE:
3. Specifications at -40°C and 105°C are guaranteed by 25°C test with margin limits.
4. Guaranteed by design, not 100% tested in production.
5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 - 5.
6. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
FN9182.1
6
March 10, 2005
ISL6753
Typical Performance Curves
25
24
23
22
21
20
19
18
1.02
1.01
1
0.99
0.98
40 25 10 5 20 35 50 65 80 95 110
0
200
400
600
800 1000
Temperature (C)
RTD Current (uA)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
3
.
4
CT =
.
1 10
1 10
1000pF
680pF
470pF
330pF
220pF
100pF
3
.
1 10
100
100
10
RTD=
10k
Ω
50k
Ω
100k
Ω
10
0
10 20 30 40 50 60 70 80 90 100
RTD (kohms)
0.1
1
10
CT (nF)
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
Supply voltage under-voltage lock-out (UVLO) start and stop
thresholds track each other resulting in relatively constant
hysteresis.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1.00V nominal.
The CS pin is shorted to GND at the termination of either
PWM output.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200µA
current source and discharged with a user adjustable current
source controlled by RTD.
RAMP - This is the input for the sawtooth waveform for the
PWM comparator. The RAMP pin is shorted to GND at the
termination of the PWM signal. A sawtooth voltage
FN9182.1
7
March 10, 2005
ISL6753
waveform is required at this input. For current-mode control
this pin is connected to CS and the current loop feedback
signal is applied to both inputs. For voltage-mode control,
the oscillator sawtooth waveform may be buffered and used
to generate an appropriate signal, RAMP may be connected
to the input voltage through a RC network for voltage feed
forward control, or RAMP may be connected to VREF
through a RC network to produce the desired sawtooth
waveform.
Functional Description
Features
The ISL6753 PWM is an excellent choice for low cost ZVS
full-bridge applications employing conventional output
rectification. If synchronous rectification is required, please
consider the ISL6752 or ISL6551 products.
With the ISL6753’s many protection and control features, a
highly flexible design with minimal external components is
possible. Among its many features are support for both
current- and voltage-mode control, a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
voltage controlled resonant delay, and adjustable frequency
with precise deadtime control.
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
Oscillator
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
The ISL6753 has an oscillator with a programmable
frequency range to 2MHz, and can be programmed with an
external resistor and capacitor.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
3
T
≈ 11.5 ⋅ 10 ⋅ CT
S
(EQ. 1)
C
OUTLL and OUTLR - These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
–9
(EQ. 2)
T
≈ (0.06 ⋅ RTD ⋅ CT) + 50 ⋅ 10
S
D
1
T
= T + T = ------------
S
(EQ. 3)
SW
C
D
F
SW
where T and T are the charge and discharge times,
C
D
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input for closed loop regulation. VERR
has a nominal 1mA pull-up current source.
respectively, T
is the oscillator period, and F is the
SW
SW
oscillator frequency. One output switching cycle requires two
oscillator cycles. The actual times will be slightly longer than
calculated due to internal propagation delays of
approximately 10nS/transition. This delay adds directly to
the switching duration, but also causes overshoot of the
timing capacitor peak and valley voltage thresholds,
effectively increasing the peak-to-peak voltage on the timing
capacitor. Additionally, if very small discharge currents are
used, there will be increased error due to the input
impedance at the CT pin.
FB - FB is the inverting input to the error amplifier (EA).
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of
the capacitor determines the rate of increase of the duty
cycle during start up.
SS may also be used to inhibit the outputs by grounding
through a small transistor in an open collector/drain
configuration.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
T
C
(EQ. 4)
D = ------------
T
SW
DT = 1 – D
(EQ. 5)
FN9182.1
8
March 10, 2005
ISL6753
by the leading edge blanking (LEB) interval. The effective
Soft-Start Operation
delay is the sum of the two delays and is nominally 105nS.
The ISL6753 features a soft-start using an external capacitor
in conjunction with an internal current source. Soft-start
reduces component stresses and surge currents during start
up.
Voltage Feed Forward Operation
Voltage feed forward is a technique used to regulate the
output voltage for changes in input voltage without the
intervention of the control loop. Voltage feed forward is often
implemented in voltage-mode control loops, but is redundant
and unnecessary in peak current-mode control loops.
Upon start up, the soft-start circuitry limits the error voltage
input (VERR) to a value equal to the soft-start voltage. The
output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the soft-
start period. When the soft-start voltage exceeds the error
voltage, soft-start is completed. Soft-start occurs during
start-up and after recovery from a fault condition. The soft-
start charging period may be calculated as follows:
Voltage feed forward operates by modulating the sawtooth
ramp in direct proportion to the input voltage. Figure 5
demonstrates the concept.
VIN
(EQ. 6)
t = 64.3 ⋅ C
mS
ERROR VOLTAGE
RAMP
where t is the charging period in mS and C is the value of the
soft-start capacitor in µF.
CT
The soft-start voltage is clamped to 4.50V with a tolerance of
2%. It is suitable for use as a “soft-started” reference
provided the current draw is kept well below the 70µA
charging current.
OUTLL, LR
The outputs may be inhibited by using the SS pin as a
disable input. Pulling SS below 0.25V forces all outputs low.
An open collector/drain configuration may be used to couple
the disable signal into the SS pin.
FIGURE 5. VOLTAGE FEED FORWARD BEHAVIOR
Input voltage feed forward may be implemented using the
RAMP input. An RC network connected between the input
voltage and ground, as shown in Figure 7, generates a
voltage ramp whose charging rate varies with the amplitude
of the source voltage. At the termination of the active output
pulse RAMP is discharged to ground so that a repetitive
sawtooth waveform is created. The RAMP waveform is
compared to the VERR voltage to determine duty cycle. The
selection of the RC components depends upon the desired
input voltage operating range and the frequency of the
oscillator. In typical applications the RC components are
selected so that the ramp amplitude reaches 1.0V at
minimum input voltage within the duration of one half-cycle.
Gate Drive
The ISL6753 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50Ω.
Overcurrent Operation
The cycle-by-cycle peak current limit results in pulse-by-
pulse duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the
threshold, the active output pulse is immediately terminated.
This results in a decrease in output voltage as the load
current increases beyond the current limit threshold. The
ISL6753 operates continuously in an overcurrent condition
without shutdown.
If voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. The DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. A latching overcurrent shutdown
method using external components is recommended.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
FN9182.1
9
March 10, 2005
ISL6753
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
1
Fm = -------------------
(EQ. 9)
SnTsw
ISL6753
R3
C7
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
RAMP
GND
1
1
(EQ. 10)
Fm = -------------------------------------- = ---------------------------
(Sn + Se)Tsw m SnTsw
c
where Se is slope of the external ramp and
Se
Sn
m
= 1 + -------
(EQ. 11)
c
FIGURE 6. VOLTAGE FEED FORWARD CONTROL
The charging time of the ramp capacitor is
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for Q >
1, and under-damped for Q < 1. An under-damped condition
can result in current loop instability.
V
RAMP(PEAK)
t = –R3 ⋅ C7 ⋅ ln 1 – ---------------------------------------
S
(EQ. 7)
V
IN(MIN)
For optimum performance, the maximum value of the
capacitor should be limited to 10nF. The maximum DC
current through the resistor should be limited to 2mA
maximum. For example, if the oscillator frequency is
400kHz, the minimum input voltage is 300V, and a 4.7nF
ramp capacitor is selected, the value of the resistor can be
determined by rearranging EQ. 7.
1
(EQ. 12
Q = -------------------------------------------------
π(m (1 – D) – 0.5)
c
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields
–6
–t
–2.5 ⋅ 10
R3 = ------------------------------------------------------------------------- = ------------------------------------------------------------
–9
1
300
V
RAMP(PEAK)
4.7 ⋅ 10 ⋅ ln 1 – ---------
C7 ⋅ ln 1 – ---------------------------------------
1
1
π
(EQ. 13)
-------------
S
= S
-- + 0.5
– 1
V
e
n
IN(MIN))
1 – D
= 159
kΩ
(EQ. 8)
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by Ton to obtain the voltage change that occurs during Ton.
where t is equal to the oscillator period minus the deadtime.
If the deadtime is short relative to the oscillator period, it can
be ignored for this calculation.
1
1
-------------
V
= V
-- + 0.5
– 1
(EQ. 14)
e
n
1 – D
π
If feed forward operation is not desired, the RC network may
be connected to VREF rather than the input voltage.
Alternatively, a resistor divider from CTBUF may be used as
the sawtooth signal. Regardless, a sawtooth waveform must
be generated on RAMP as it is required for proper PWM
operation.
where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
T
⋅ V ⋅ R
Slope Compensation
N
SW
CS
O
S
1
π
----------------------------------------- -------
V
=
⋅
-- + D – 0.5
V
(EQ. 15)
e
N
P
N
⋅ L
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
CT
O
where R
is the current sense burden resistor, N is the
CT
CS
current transformer turns ratio, L is the output inductance,
O
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
V
is the output voltage, and Ns and Np are the secondary
O
and primary turns, respectively.
FN9182.1
10
March 10, 2005
ISL6753
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields
peak amplitude of CT (0.4 - 4.4V). A typical application sums
this signal with the current sense feedback and applies the
result to the CS pin as shown in Figure 7.
N
⋅ R
D ⋅ T
N
S
CS
SW
S
------------------------
--------------------
-------
V
=
I
+
V
⋅
– V
O
V
CS
O
IN
N
⋅ N
2L
O
N
P
1
P
CT
(EQ. 16)
2
3
4
5
6
7
8
CTBUF
where V
is the voltage across the current sense resistor
CS
and I is the output current at current limit.
O
ISL6753
R9
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
CS
V
+ V
= 1
CS
(EQ. 17)
e
R6
RCS
C4
Substituting EQs. 15 and 16 into EQ. 17 and solving for R
yields
CS
N
⋅ N
1
P
CT
----------------------- ------------------------------------------------------
R
=
⋅
Ω
(EQ. 18)
CS
N
V
O
S
1
D
-------
I
+
T
-- + ---
SW
π
O
L
2
O
FIGURE 7. ADDING SLOPE COMPENSATION
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
(D(V
– 0.4) + 0.4) ⋅ R6
R6 + R9
CTBUF
(EQ. 22)
V
– ∆V
= ------------------------------------------------------------------------------
CS
V
e
Rearranging to solve for R9 yields
V
⋅ DT
IN
SW
(EQ. 19)
∆I = -------------------------------
A
(D(V
– 0.4) – V + ∆V
+ 0.4) ⋅ R6
CS
P
CTBUF
e
L
R9 = ------------------------------------------------------------------------------------------------------------------
– ∆V
Ω
m
V
e
CS
(EQ. 23)
where V is the input voltage that corresponds to the duty
IN
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
The value of R
determined in EQ. 18 must be rescaled so
CS
that the current sense signal presented at the CS pin is that
predicted by EQ. 16. The divider created by R6 and R9
makes this necessary.
resistor, R , is
CS
∆I ⋅ R
P
CS
(EQ. 20)
∆V
= -------------------------
V
CS
N
CT
R6 + R9
----------------------
⋅ R
CS
(EQ. 24)
R′
=
CS
R9
If ∆V
CS
is greater than or equal to Ve, then no additional
slope compensation is needed and R
becomes
CS
Example:
N
CT
V
V
= 280V
R
= -------------------------------------------------------------------------------------------------------------------------------------
IN
CS
N
DT
N
V
⋅ DT
SW
S
SW
S
IN
-------
----------------
-------
⋅
I
+
⋅
V
⋅
– V
O
+ -------------------------------
= 12V
O
IN
O
N
P
2L
O
N
P
L
m
(EQ. 21)
L
= 2.0µH
O
Np/Ns = 20
Lm = 2mH
If ∆V is less than Ve, then EQ. 18 is still valid for the value
CS
of R , but the amount of slope compensation added by the
CS
external ramp must be reduced by ∆V
.
CS
I
= 55A
O
Adding slope compensation is accomplished in the ISL6753
using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-
Oscillator Frequency, Fsw = 400kHz
Duty Cycle, D = 85.7%
N
= 50
CT
FN9182.1
11
March 10, 2005
ISL6753
R6 = 499Ω
Solve for the current sense resistor, R , using EQ. 18.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that EQs. 21 and 22
require modification. EQ. 21 becomes:
CS
R
= 15.1Ω.
CS
2D ⋅ R6
R6 + R9
V
– ∆V
= ----------------------
CS
V
(EQ. 25)
e
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using EQ. 15.
and EQ. 22 becomes:
Ve = 153mV
(2D – V + ∆V ) ⋅ R6
e
CS
(EQ. 26)
R9 = ------------------------------------------------------------
– ∆V
Ω
Next, determine the effect of the magnetizing current from
EQ. 20.
V
e
CS
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
∆V
CS
= 91mV
Using EQ. 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
ZVS Full-Bridge Operation
Determine the new value of R , R’ , using EQ. 24.
CS CS
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
R’
CS
= 15.4Ω
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
f the application requires deadtime less than about 500nS,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400nS. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
CT
DEADTIME
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
PWM
PWM
OUTLL
OUTLR
OUTUR
PWM
PWM
1
2
3
4
5
6
7
8
VREF 16
15
14
13
12
11
10
9
RESONANT
DELAY
ISL6753
OUTUL
RESDEL
WINDOW
CT
CS
R9
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
R6
RCS
C4
CT
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
FN9182.1
12
March 10, 2005
ISL6753
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
the node to VIN and then forward biases the body diode of
upper switch UR.
VIN+
UL
UR
VIN+
IS
D1
UL
UR
D1
VOUT+
RTN
LL
VOUT+
RTN
LL
IP
LL
LR
LL
LR
D2
D2
VIN-
VIN-
FIGURE 12. UL - UR FREE-WHEELING PERIOD
FIGURE 10. IDEALIZED FULL-BRIDGE
The primary leakage inductance, L , maintains the current
L
In Figure 10, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. This condition persists through the
remainder of the half-cycle.
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 11, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from EQ. 27.
are indicated by I and I , respectively.
P
S
VIN+
UL
LL
UR
LR
IS
D1
VOUT+
RTN
LL
IP
π
2
1
-------------------------------------
τ =
(EQ. 27)
2
1
R
-------------- – ---------
2
L
L C
D2
L
P
4L
VIN-
where τ is the resonant transition time, L is the leakage
L
FIGURE 11. UL - LR POWER TRANSFER CYCLE
inductance, C is the parasitic capacitance, and R is the
P
equivalent resistance in series with L and C .
L
P
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR which charges
The resonant delay is always less than or equal to the
deadtime and may be calculated using the following
equation.
V
resdel
2
-------------------
τ
=
⋅ DT
S
(EQ. 28)
resdel
where τ
resdel
is the desired resonant delay, V
voltage between 0 and 2V applied to the RESDEL pin, and
DT is the deadtime (see EQs. 1 - 5).
is a
resdel
When the upper switches toggle, the primary current that
was flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
FN9182.1
13
March 10, 2005
ISL6753
RESDEL is set properly, switch LL will be turned on at this
time.
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
UL
UR
VIN+
IS
D1
UL
UR
IS
D1
VOUT+
RTN
LL
VOUT+
RTN
LL
IP
IP
LL
LR
LL
LR
D2
D2
VIN-
VIN-
FIGURE 13. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated below.
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
VIN+
2
UL
LL
UR
LR
stored is proportional to the square of the current (1/2 L I
,
L P
D1
D2
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
VOUT+
RTN
LL
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected, the soft-
start capacitor is quickly discharged, and the outputs are
disabled low. When the fault condition clears and the soft-
start voltage is below the reset threshold, a soft-start cycle
begins.
VIN-
FIGURE 14. UR - LL POWER TRANSFER
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to VIN and then forward biases the body diode of upper
An overcurrent condition is not considered a fault and does
not result in a shutdown.
switch UL. The primary leakage inductance, L , maintains
L
the current, which now circulates around the path of switch
UR, the transformer primary, and switch UL. When switch LL
opens, the output inductor current free-wheels through both
output diodes, D1 and D2. This condition persists through
the remainder of the half-cycle.
Thermal Protection
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed 140°C. There is
approximately 15°C of hysteresis.
VIN+
Ground Plane Requirements
UL
UR
IS
D1
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
VOUT+
RTN
LL
IP
LL
LR
References
D2
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
VIN-
FIGURE 15. UR - UL FREE-WHEELING PERIOD
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
FN9182.1
14
March 10, 2005
ISL6753
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
M
M
B
0.25(0.010)
H
AREA
3
E
INCHES
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MIN
MAX
MIN
1.55
0.102
1.40
0.20
0.191
4.80
3.81
MAX
1.73
0.249
1.55
0.31
0.249
4.98
3.99
NOTES
A
A1
A2
B
0.061
0.004
0.055
0.008
0.0075
0.189
0.150
0.068
0.0098
0.061
0.012
0.0098
0.196
0.157
-
1
2
-
L
-
0.25
0.010
SEATING PLANE
A
9
-A-
D
h x 45°
C
D
E
-
3
-C-
4
α
A2
e
A1
e
0.025 BSC
0.635 BSC
-
C
B
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
0.10(0.004)
M
M
S
B
0.17(0.007)
C
A
5
L
6
NOTES:
N
α
16
16
7
1. Symbols are defined in the “MO Series Symbol List” in Section
0°
8°
0°
8°
-
2.2 of Publication Number 95.
Rev. 2 6/04
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9182.1
15
March 10, 2005
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