ISL68200IRZ [INTERSIL]
Single-Phase R4 Digital Hybrid PWM Controller with Integrated Driver;型号: | ISL68200IRZ |
厂家: | Intersil |
描述: | Single-Phase R4 Digital Hybrid PWM Controller with Integrated Driver |
文件: | 总32页 (文件大小:755K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
Single-Phase R4™ Digital Hybrid PWM Controller with
2
Integrated Driver, PMBus/SMBus/I C and PFM
ISL68200
Features
The ISL68200 is a single-phase synchronous-buck PWM
controller featuring Intersil’s proprietary R4™ Technology. It
supports a wide 4.5V to 24V input voltage range and a wide
0.5V to 5.5V output range. Integrated LDOs provide controller
bias voltage, allowing for single supply operation. The
• Intersil’s proprietary R4™ Technology
- Linear control loop for optimal transient response
- Variable frequency and duty cycle control during load
transient for fastest possible response
- Inherent voltage feed-forward for wide range input
2
ISL68200 includes a PMBus/SMBus/I C interface for device
configuration and telemetry (V , V , I
and temperature)
• Input voltage range: 4.5V to 24V
IN OUT OUT
and fault reporting.
• Output voltage range: 0.5V to 5.5V
• ±0.5% DAC accuracy with remote sense
• Support all ceramic solutions
Intersil’s proprietary R4™ control scheme has extremely fast
transient performance, accurately regulated frequency control
and all internal compensation. An efficiency enhancing PFM
mode can be enabled to greatly improve light-load efficiency.
The ISL68200’s series bus allows for easy R4™ loop
• Integrated LDOs for single input rail solution
2
• SMBus/PMBus/I C compatible, up to 1.25MHz
optimization, resulting in fast transient performance over a
wide range of applications, including all ceramic output filters.
• 256 boot-up voltage levels with a configuration pin
• Eight switching frequency options from 300kHz to 1.5MHz
• PFM operation option for improved light-load efficiency
• Start-up into precharged load
Built-in MOSFET drivers minimize external components,
significantly reducing design complexity and board space,
while also lowering BOM cost. The 4A drive strength allows for
faster switching time, improving regulator efficiency. An
integrated high-side gate-to-source resistor helps avoid Miller
coupling shoot-through and improve system reliability.
• Precision enable input to set higher input UVLO and power
sequence as well as fault reset
• Power-good monitor for soft-start and fault detection
The ISL68200 has four 8-bit configuration pins, which provide
• Comprehensive fault protection for high system reliability
- Over-temperature protection
very flexible configuration options (frequency, V , R4™ gain,
etc.) without the need for built-in NVM memory. This results in
a design flow that closely matches traditional analog
OUT
- Output overcurrent and short-circuit protection
- Output overvoltage and undervoltage protection
- Open remote sense protection
controllers, while still offering the design flexibility and feature
2
set of a digital PMBus/SMBus/I C interface. The ISL68200
also features remote voltage sensing and completely eliminates
any potential difference between remote and local grounds. This
improves regulation and protection accuracy. A precision enable
input is available to coordinate the start-up of the ISL68200 with
other voltage rails, especially useful for power sequencing.
- Integrated high-side gate-to-source resistor to prevent self
turn-on due to high input bus dv/dt
• Integrated power MOSFETs 4A drivers with adaptive
shoot-through protection and bootstrap function
• Compatible with Intersil’s PowerNavigator™ software
Applications
• High efficiency and high density POL digital power
Related Literature
UG067, “ISL68200DEMO1Z Demonstration Board User Guide”
• FPGA, ASIC and memory supplies
• Datacenter: servers, storage systems
• Wired infrastructure: routers/switches/optical networking
• Wireless infrastructure: base station
TABLE 1. SINGLE-PHASE R4™ DIGITAL HYBRID PWM CONTROLLER OPTIONS
2
PART
NUMBER
INTEGRATED
DRIVER
PWM
OUTPUT
PMBus/SMBus/I C
INTERFACE
COMPATIBLE DEVICES
ISL68200
ISL68201
Yes
No
No
Yes
Discrete MOSFETs or Dual Channel MOSFETs
Yes
Yes
Intersil Power Stages: ISL99140
Intersil Drivers: ISL6596, ISL6609, ISL6627, ISL6622, ISL6208
March 7, 2016
FN8705.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved.
Intersil (and design), R3 Technology, R4 Technology and PowerNavigator are trademarks owned by Intersil Corporation or
one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
1
ISL68200
Table of Contents
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IC Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resistor Reader (Patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot-Up Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal Monitoring and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUT
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PGOOD Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Adaptive Shoot-Through Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PFM Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
SMBus, PMBus and I C Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
R4™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
General Application Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Design and Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Voltage Regulator Design Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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ISL68200
Typical Applications Circuits
1.0µF
4.7µF
VCC
PVCC
VIN
7VLDO
1.0µF
4.75V TO 24V
0.1µF
BOOT
I2C/SMBus/
SALERT
SCL
PMBus
V
< 7VLDO - 1.7V
UGATE
OUT
SDA
0.5V TO 5.5V
PGOOD
EN
PGOOD
EN
PHASE
VCC
IOUT
LGATE
VCC
10k
NTC
1.54k
VCC
NTC
NCP15XH103J03RC
BETA = 3380
0.1µF
4
PROG1-4
CSEN
CSRTN
VSEN
RGND
GND
FIGURE 1. WIDE RANGE INPUT AND OUTPUT APPLICATIONS
1.0µF
1.0µF
4.7µF
VCC
PVCC
VIN
7VLDO
4.5V TO 5.5V
0.1µF
BOOT
2
SALERT
SCL
I C/SMBus/
PMBus
V
< 7VLDO - 1.7V
0.5V TO 2.5V
OUT
UGATE
SDA
PGOOD
EN
PGOOD
EN
PHASE
LGATE
VCC
IOUT
10k
VCC
NTC
1.54k
0.1µF
VCC
NTC
NCP15XH103J03RC
BETA = 3380
4
PROG1-4
CSEN
CSRTN
VSEN
RGND
GND
FIGURE 2. 5V INPUT APPLICATION
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ISL68200
Block Diagram
SDA SALERT
PROG2 PROG3
PROG4
SCL
7VLDO
VINPVCC
VCC
EN
POR
SOFT-START
AND
FAULT LOGIC
2
SMBUS/PMBUS/I C
INTERFACE
BOOT
OTP OCP
VIN VOUT IOUT TEMP
DRIVER
UGATE
PGOOD
CIRCUITRY
PGOOD
PHASE
PVCC
DEAD TIME
GENERATION
RGND
VSEN
INTERNAL
COMPENSATION
AMPLIFIER
OVERVOLTAGE/
UNDERVOLTAGE
+
DRIVER
LGATE
GND
5V LDO
R4™
MODULATOR
VIN
7V LDO
7VLDO
REFERENCE
VOLTAGE
CIRCUITRY
PROG1
GND
CSEN
CURRENT SENSE
AND TEMPERATURE
COMPENSATION
OVERCURRENT (OCP) AND
OVER-TEMPERATURE (OTP)
CSRTN
NTC
SWITCHING
FREQUENCY
IOUT
FIGURE 3. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL68200
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ISL68200
Pin Configuration
ISL68200
(24 LD 4x4 QFN)
TOP VIEW
24 23 22 21 20 19
EN
VIN
PROG1
PROG2
PROG3
PROG4
IOUT
18
17
16
15
14
13
1
2
3
4
5
6
7VLDO
VCC
25
GND PAD
SCL
SALERT
NTC
7
8
9
10 11 12
Functional Pin Descriptions
PIN NUMBER SYMBOL
DESCRIPTION
1
2
3
4
EN
Precision Enable input. Pulling EN above the rising threshold voltage initiates the soft-start sequence, while pulling EN below the
failing threshold voltage suspends the Voltage Regulator (VR) operation.
VIN
Input voltage pin for R4™ loop and LDOs (5V and 7V). Place a high quality low ESR ceramic capacitor (1.0μF, X7R) in close
proximity to the pin. External series resistor is not advised.
7VLDO 7V LDO from VIN is used to bias current sensing amplifier. Place a high quality low ESR ceramic capacitor (1.0μF, X7R, 10V+)
in close proximity to the pin.
VCC
SCL
Logic bias supply that should be connected to PVCC rail externally. Place a high quality low ESR ceramic capacitor (1.0μF,
X7R) from this pin to GND.
2
5
6
Synchronous clock signal input of SMBus/PMBus/I C.
SALERT Output pin for transferring the active low signal driven asynchronously from the VR controller to SMBus/PMBus.
2
7
SDA
I/O pin for transferring data signals between SMBus/PMBus/I C host and VR controller.
8
PGOOD Open-drain indicator output.
9
RGND
VSEN
This pin monitors the negative rail of regulator output. Connect to ground at point of regulation.
This pin monitors the positive rail of regulator output. Connect to point of regulation
10
11
12
CSRTN This pin monitors the negative flow of output current for overcurrent protection and telemetry.
CSEN
This pin monitors the positive flow of output current with a series resistor and for overcurrent protection and telemetry. The
series resistor sets the current gain and should be within 40Ωand 3.5kΩ.
13
NTC
Input pin for the temperature measurement. Connect this pin through an NTC thermistor (10kΩ, ~ 3380) and a decoupling
capacitor (~0.1μF) to GND and a resistor (1.54kΩ)to VCC of the controller. The voltage at this pin is inversely proportional to
the VR temperature.
14
15
16
IOUT
Output current monitor pin. An external resistor sets the gain and an external capacitor provides the averaging function; an
external pull-up resistor to VCC is recommended to calibrate the no load offset. See “I
Calibration” on page 19.
OUT
PROG4 Programming pin for Modulator (R4™) RR impedance and output slew rate during Soft-Start (SS) and Dynamic VID (DVID).
It also sets AV gain multiplier to 1x or 2x and determines the AV gain on PROG3.
PROG3 Programming pin for ultrasonic PFM operation, fault behavior, switching frequency and R4™ (AV) control loop gain.
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ISL68200
Functional Pin Descriptions(Continued)
PIN NUMBER SYMBOL
DESCRIPTION
2
17
18
19
20
21
22
23
PROG2 Programming pin for PWM/PFM mode, temperature compensation and serial bus (SMBus/PMBus/I C) address.
PROG1 Programming pin for boot-up voltage.
GND
Return current path for the LGATE MOSFET driver. Connect directly to system ground plane.
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
PHASE Return path for the UGATE high-side MOSFET driver, and zero inductor current detector input for diode emulation.
UGATE
BOOT
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
Positive input supply for the UGATE high-side MOSFET gate driver. Connect an MLCC (0.22µF, X7R) between BOOT and
PHASE pins.
24
25
PVCC
Output of the 5V LDO and input for the LGATE and UGATE MOSFET driver circuits. Place a high quality low ESR ceramic
capacitor (4.7μF, X7R) in close proximity to the pin.
GND PAD Return of logic bias supply VCC. Connect directly to system ground plane with at least 5 vias.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL68200IRZ
ISL 68200I
-40 to +85
24 Ld 4x4 QFN
L24.4x4C
ISL68200DEMO1Z
NOTES:
20A Demonstration Board with on-board transient
1. Add “-T” suffix for 6k units, “-T7A” = suffix for 250 units and “-TK” for 1k units. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL68200. For more information on MSL please see techbrief TB363.
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ISL68200
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, VSEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V
7VLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to GND, 7.75V
Thermal Resistance (Typical)
24 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
39
(°C/W)
2.5
JA
JC
BOOT Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT-GND
BOOT to PHASE Voltage (V
). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
BOOT-PHASE
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 28V
(GND - 9V) (<20ns Pulse Width, 10µJ)
Recommended Operating Conditions
UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . (V
- 0.3V) (DC) to V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
PHASE
- 5V) (<20ns Pulse Width, 10µJ) to V
BOOT
BOOT
(V
Wide Range Input Voltage, V , Figure 1. . . . . . . . . . . . . . . . . 4.75V to 24V
PHASE
IN
LGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) (DC) to VCC + 0.3V
5V Application Input Voltage, V , Figure 2. . . . . . . . . . . . . . . . 4.5V to 5.5V
IN
(GND - 2.5V) (<20ns Pulse Width, 5µJ) to VCC + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
ESD Ratings
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Human Body Model (Tested per JS-001-2010). . . . . . . . . . . . . . . . .2.5kV
Latch-Up (Tested per JESD78D, Class 2, Level A). . . . ±100mA at +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All typical specifications T = +25°C, V = 5V. Boldface limits apply across the operating temperature range,
A
CC
-40°C to +85°C, unless otherwise stated.
MIN
MAX
PARAMETER
VCC AND PVCC
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
VCC Input Bias Current
I
EN = 5V, V = 5V, f
CC
= 500kHz, DAC = 1V
= 500kHz, DAC = 1V
14
14
2
16.5
16.5
mA
mA
mA
mA
VCC
SW
EN = 0V, V = 5V
CC
PVCC Input Bias Current
I
EN = 5V, V = 5V, f
CC
PVCC
SW
EN = 0V, V = 5V
CC
1.0
VCC AND VIN POR THRESHOLD
VCC, PVCC Rising POR Threshold Voltage
VCC, PVCC Falling POR Threshold Voltage
4.20
3.95
4.20
3.95
4.35
4.15
4.35
4.15
V
V
V
V
3.80
3.80
V
V
, 7VLDO Rising POR Threshold Voltage
, 7VLDO Falling O POR Threshold Voltage
IN
IN
ENABLE INPUT
EN High Threshold Voltage
EN Low Threshold Voltage
DAC ACCURACY
V
0.81
0.71
0.84
0.76
0.87
0.81
V
V
ENTHR
V
ENTHF
DAC Accuracy
2.5V < DAC ≤ 5.5V
1.6V < DAC ≤ 2.5V
1.2V < DAC ≤ 1.6V
0.5V ≤ DAC ≤ 1.2V
2.5V < DAC ≤ 5.5V
1.6V < DAC ≤ 2.5V
1.2V < DAC ≤ 1.6V
0.5V ≤ DAC ≤ 1.2V
-0.5
-0.75
-10
0.5
0.75
10
%
%
(T = 0°C to +85°C)
A
mV
mV
%
-8
8
DAC Accuracy
-0.75
-1.0
-11
0.75
1.0
11
(T = -45°C to +85°C)
A
%
mV
mV
-9
9
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ISL68200
Electrical Specifications All typical specifications T = +25°C, V = 5V. Boldface limits apply across the operating temperature range,
A
CC
-40°C to +85°C, unless otherwise stated. (Continued)
MIN
MAX
PARAMETER
CHANNEL FREQUENCY
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
300kHz Configuration
400kHz Configuration
500kHz Configuration
600kHz Configuration
700kHz Configuration
850kHz Configuration
1000kHz Configuration
1500kHz Configuration
SOFT-START AND DYNAMIC VID
Soft-Start and DVID Slew Rate
PWM mode
PWM mode
PWM mode
PWM mode
PWM mode
PWM mode
PWM mode
PWM mode
260
345
435
510
610
730
865
1320
300
400
335
450
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
500
562
600
670
700
790
850
950
1000
1500
1120
1660
0.0616 0.078
0.096
0.18
0.37
0.70
1.40
2.80
5.60
10.9
260
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
µs
0.13
0.25
0.53
1.05
2.10
4.20
8.60
140
0.157
0.315
0.625
1.25
2.50
5.00
10.0
200
Soft-Start Delay from Enable High
Excluding 5.5ms POR timeout, See Figures 22
and 23 on page 22
REMOTE SENSE
Bias Current of VSEN and RGND Pins
Maximum Differential Input Voltage
POWER-GOOD
250
µA
V
6.0
PGOOD Pull-Down Impedance
PGOOD Leakage Current
LDOs
R
PGOOD = 5mA sink
PGOOD = 5V
10
5.00
7.4
50
Ω
PG
I
1.0
µA
PG
5V LDO Regulation
V
V
= 12V, load = 50mA
= 4.75V, load = 50mA
4.85
4.45
125
7.2
5.15
7.5
V
V
IN
5V LDO Regulation
IN
5V LDO Current Capability
7V LDO Regulation
mA
V
250µA load
= 4.75V, 250µA load
7V Dropout
V
4.50
2
V
IN
7V LDO Current Capability
CURRENT SENSE
Not recommended for external use
mA
Average OCP Trip Level
Short-Circuit Protection Threshold
Sensed Current Tolerance
Sensed Current Tolerance
Maximum Common-Mode Input Voltage
I
82
100
130
78
123
µA
OC_TRIP
% I
OCP
74
35
83
42
µA
38
µA
V
7VLDO = 7.4V
5.7
2.8
VCC = PVCC = 7VLDO = 4.5V
V
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ISL68200
Electrical Specifications All typical specifications T = +25°C, V = 5V. Boldface limits apply across the operating temperature range,
A
CC
-40°C to +85°C, unless otherwise stated. (Continued)
MIN
MAX
PARAMETER
FAULT PROTECTION
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
UVP Threshold Voltage
Latch
68
74
1.15
1.65
1.95
2.15
2.65
3.45
5.65
100
80
% DAC
Start-Up OVP Threshold Voltage
0V ≤ V
≤ 1.08V
1.10
1.58
1.88
2.09
2.56
3.36
5.52
1.25
1.75
2.05
2.25
2.75
3.6
V
BOOT
1.08V < V
1.55V < V
1.85V < V
2.08V < V
2.53V < V
3.33V < V
≤ 1.55V
≤ 1.85V
≤ 2.08V
≤ 2.53V
≤ 3.33V
≤ 5.5V
V
BOOT
BOOT
BOOT
BOOT
BOOT
BOOT
V
V
V
V
5.85
V
Start-Up OVP Hysteresis
mV
OVP Rising Threshold Voltage
V
0.5 ≤ DAC ≤ 5.5
0.5 ≤ DAC ≤ 5.5
READ_TEMP = 72h
READ_TEMP = 8Eh
114
96
120
127
108
26
% DAC
% DAC
% VCC
% VCC
OVRTH
OVP Falling Threshold Voltage
V
100
OVFTH
Over-Temperature Shutdown Threshold
Over-Temperature Shutdown Reset Threshold
20
22.31
27.79
25
30
2
SMBus/PMBus/I C
Signal Input Low Voltage
Signal Input High Voltage
Signal Output Low Voltage
DATE, ALERT # Pull-Down Impedance
CLOCK Maximum Speed
CLOCK Minimum Speed
Telemetry Update Rate
Timeout
1
V
V
1.6
1.25
25
4mA pull-up current
0.4
50
V
11
Ω
MHz
MHz
µs
0.05
108
30
35
ms
ms
PMBus Accessible Timeout from All Rails’ POR
GATE DRIVER
See Figure 22 on page 22
5.5
6.5
UGATE Pull-Up Resistance
UGATE Source Current
UGATE Sink Resistance
UGATE Sink Current
R
200mA source current
UGATE - PHASE = 2.5V
250mA sink current
1.0
2.0
1.0
2.0
1.0
2.0
0.5
4.0
10
Ω
A
UGPU
I
UGSRC
R
Ω
A
UGPD
I
UGATE - PHASE = 2.5V
250mA source current
LGATE - GND = 2.5V
UGSNK
LGATE Pull-Up Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
R
Ω
A
LGPU
I
LGSRC
R
250mA sink current
Ω
A
LGPD
I
LGATE - GND = 2.5V
LGSNK
UGATE to LGATE Dead Time
LGATE to UGATE Dead Time
BOOTSTRAP DIODE
t
UGATE falling to LGATE rising, no load
LGATE falling to UGATE rising, no load
ns
ns
UGFLGR
LGFUGR
t
18
ON-Resistance
R
16
30
Ω
F
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL68200
In addition, based upon ON_OFF_CONFIG [02h] setting, the IC be
enabled or disabled by series bus command “OPERATION [01h]”
and/or EN pin. See Table 11 on page 25 for more details.
Operation
The following sections will provide a detailed description of the
ISL68200 operation.
Resistor Reader (Patented)
IC Supplies
The ISL68200 offers four programming pins to customize their
regulator specifications. The details of these pins are summarized
in Table 2, followed by the detailed description of resistor reader
operation.
The ISL68200 has 4 bias pins: VIN, 7VLDO, PVCC and VCC. The
PVCC and 7VLDO voltage rails are 5V LDO and 7.4V LDO supplied
by VIN, respectively, while the VCC pin needs to connect to PVCC
rail externally to be biased. For 5V input applications, all these
pins should be tied together and biased by a 5V supply. Since the
VIN pin voltage information is used by the R4™ Modulator loop,
the user CANNOT bias VIN with a series resistor. In addition, the
VIN pin CANNOT be biased independently from other rails.
TABLE 2. DEFINITION OF PROG PINS
PIN
BIT
NAME
DESCRIPTION
PROG1 [7:0]
BOOT-UP
VOLTAGE
Set output boot-up voltage, 256 different
options: 0, 0.5V to 5.5V (see Table 7)
Enable and Disable
PROG2 [7:7]
PWM/PFM
Enables PFM mode or forced PWM.
The IC is disabled until the 7VLDO, PVCC, VCC, VIN and EN pins
increase above their respective rising threshold voltages and the
typical 5.5ms timeout (worst case = 6.5ms) expires, as shown in
Figures 22 and 23 on page 22. The controller will become
disabled when the 7VLDO, PVCC, VCC, VIN or EN pins drop below
their respective falling POR threshold voltages.
[6:5] Temperature Adjust NTC temperature compensation:
Compensation OFF, +5, +15, +30°C.
[4:0]
ADDR
Set serial bus 32 different addresses
(see Table 10).
PROG3 [7:7]
uSPFM
Ultrasonic (25kHz clamp) PFM enable
The precision threshold EN pin allows the user to set a precision
input UVLO level with an external resistor divider, as shown in
Figure 4. For 5V input applications or wide range input
applications, the EN pin can directly connect to VCC, as shown in
Figure 5. If an external enable control signal is available and is an
open-drain signal, a pull-up impedance (100k or higher) can be
used.
[6:6] Fault Behavior OCP fault behavior:
Latch, Infinite 9ms retry
[5:3]
[2:0]
FSW
Set switching frequency (f ).
SW
R4™ Gain
Set error amplifier gain (AV).
PROG4 [7:5] RAMP_RATE Set soft-start and DVID ramp rate.
[4:3]
[2:2]
[1:0]
RR
Select RR impedance for R4™ loop.
Select AV Gain Multiplier (1x or 2x)
EXTERNAL CIRCUIT
ISL68200
AVMLTI
Not Used
VIN
100k
Intersil has developed a high resolution ADC using a patented
technique with a simple 1%, 100ppm/K or better temperature
coefficient resistor divider. The same type of resistors are
preferred so that it has similar change over-temperature. In
SOFT-
START
EN
addition, the divider is compared to the internal divider off V
9.09k
CC
and GND nodes and therefore must refer to V and GND pins,
CC
VIN UVLO = 10.2V/9.24V
not through any RC decoupling network.
FIGURE 4. INPUT UVP CONFIGURATION
EXTERNAL CIRCUIT
ISL68200
V
CC
EXTERNAL CIRCUIT
ISL68200
R
UP
VCC
EN
REGISTER
TABLE
ADC
R
OPTIONAL
EN
R
DW
SOFT-
START
VIN UVLO = 4.20/3.95V
is ONLY needed when the user wants to
FIGURE 6. SIMPLIFIED RESISTOR DIVIDER ADC
R
EN
control the IC with an external enable signal
FIGURE 5. 5V INPUT OR WIDE RANGE INPUT CONFIGURATION
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ISL68200
Tables 3 through 6 show the R and R
UP
values of each pin for
TABLE 5. PROG 3 RESISTOR READER EXAMPLE
DW
a specific system design with some tie-high and tie-low options,
which are for easy programming with reduced resistors and can
be used to validate the regulator operation during In-Circuit Test
(ICT) for 0V boot-up voltage option. Additional options are
available using Intersil’s PowerNavigator™ or Resistor Reader
calculator, please contact Intersil Application support at
www.intersil.com/en/support. DATA for corresponding registers
can be read out via series bus command (DC to DF). Note that
more options are in PowerNavigator™ GUI or Resistor Reader
calculator and the case of 10kΩ tie-high or tie-low is equivalent
0Ω tie-high or tie-low.
R4 GAIN
PROG3
(DE)
R
(kΩ)
R
(kΩ)
ULTRASONIC
PFM
FAULT
BEHAVIOR (kHz)
f
SW
UP
DW
1x
42
42
42
42
42
42
42
42
1
2x
84
84
84
84
84
84
84
84
2
00h
20h
40h
60h
80h
A0h
C0h
E0h
1Fh
3Fh
5Fh
7Fh
9Fh
BFh
DFh
FFh
Open
0
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Retry
Retry
Latch
Latch
Retry
Retry
Latch
Latch
Retry
Retry
Latch
Latch
Retry
Retry
Latch
Latch
300
700
300
700
300
700
300
700
600
1500
600
1500
600
1500
600
1500
Open 21.5
Open 34.8
Open 52.3
Open
Open
Open
Open
0
75
105
147
499
Open
TABLE 3. PROG 1 RESISTOR READER EXAMPLE
R
R
(kΩ)
VOUT
(V)
UP
DW
PROG1 (DC)
00h
20h
40h
60h
80h
A0h
C0h
(kΩ)
Open
Open
Open
Open
Open
Open
Open
Open
0
0
0.797
0.852
0.898
0.953
1.000
1.047
1.102
1.203
1.352
1.500
1.797
2.500
3.000
3.297
5.000
0.000
20
21.5 Open
34.8 Open
52.3 Open
1
2
34.8
52.3
75
1
2
1
2
75
Open
Open
Open
Open
1
2
105
147
105
147
499
1
2
1
2
E0h
499
Open
Open
Open
Open
Open
Open
Open
Open
1Fh
1
2
3Fh
20
TABLE 6. PROG 4 RESISTOR READER EXAMPLE
5Fh
34.8
52.3
75
PROG4
(DF
R
R
DW
(kΩ)
SS RATE
(mV/µs)
RR
(kΩ
7Fh
UP
(kΩ)
Open
Open
Open
Open
Open
Open
Open
Open
0
AVMLTI
9Fh
00h
20h
40h
60h
80h
A0h
C0h
E0h
1Fh
3Fh
5Fh
7Fh
9Fh
BFh
DFh
FFh
0
1.25
2.5
200
200
200
200
200
200
200
200
800
800
800
800
800
800
800
800
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
BFh
105
147
20
DFh
FFh
499
34.8
52.3
75
5
10
TABLE 4. PROG 2 RESISTOR READER EXAMPLE
0.078
0.157
0.315
0.625
1.25
2.5
PROG2
(DD)
R
R
(kΩ)
TEMP
COMP
PM_ADDR
(7-BIT)
UP
DW
105
147
(kΩ)
Open
Open
Open
Open
Open
Open
Open
Open
0
PWM/PFM
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
00h
20h
40h
60h
80h
A0h
C0h
E0h
1Fh
3Fh
5Fh
7Fh
9Fh
BFh
DFh
FFh
0
30
15
5
60h
60h
60h
60h
60h
60h
60h
60h
7F
20
499
Open
Open
Open
Open
Open
Open
Open
Open
34.8
52.3
75
OFF
30
15
5
20
34.8
52.3
75
5
105
147
10
0.078
0.157
0.315
0.625
499
Open
Open
Open
Open
Open
Open
Open
Open
OFF
30
15
5
105
147
20
7F
34.8
52.3
75
7F
499
OFF
30
15
5
7F
7F
105
147
7F
7F
499
OFF
7F
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ISL68200
ISL68200 supports precharged load start-up up to the maximum
of 5.5V with sufficient boot capacitor charge. For an
Soft-Start
V
OUT
extended precharged load, the boot capacitor will be discharged
to “PVCC - V - V ” by high-side drive circuits’ standby current.
The ISL68200 based regulator has 4 periods during soft-start, as
shown in Figure 7 on page 12. After a 5.5ms timeout (worst
case = 6.5ms) of bias supplies, as shown in Figures 22 and 23 on
page 22, once the EN pin reaches above its enable threshold, the
controller begins the first soft-start ramp after a fixed soft-start
OUT
D
For instance, an extended 4V precharged load, the boot capacitor
will reduce to a less than 1V boot capacitor voltage, which is
insufficient to power-up the VR. In this case, it is recommended
to let the output drop below 2.5V with an external bleed resistor
before issuing another soft-start command.
delay period of t . The output voltage reaches the boot-up voltage
D1
(V
) at a fixed slew rate in period t . Then, the controller will
BOOT D2
regulate the output voltage at V
SMBus/PMBus/ I C sends a new V
command is valid, the ISL68200 will initiate the ramp until the
voltage reaches the new V command voltage in period t . The
soft-start time is the sum of the 4 periods, as shown in
Equation 1.
for another period t until the
BOOT D3
2
command. If the V
OUT OUT
Boot-Up Voltage Programming
An 8-bit pin PROG1 is dedicated for the boot-up voltage
programmability, which offers 256 options 0V and 0.5V to 5.5V,
as in Table 7. The most popular boot-up voltage levels are placed
on the tie-low spots (0h, 20h, 40h, 60h, 80h, A0h, C0h, E0h) and
the tie-high spots (1Fh, 3Fh, 5Fh, 7Fh, 9Fh, BFh, DFh, FFh) for
easy programming, as summarized in Table 3. 0V boot-up
voltage is considered as “OFF,” the driver will be in tri-state and
the internal DAC will set to 0V.
OUT D4
t
= t + t + t + t
D1 D2 D3 D4
(EQ. 1)
SS
t
is a fixed delay with the typical value as 200µs. t is
D3
D1
determined by the time to obtain a new valid V
command
command is
OUT
voltage from the SMBus/PMBus/I C bus. If the V
2
OUT
valid before the output reaches the boot-up voltage, the output will
turn around to respond to the new V command code.
In addition, if the VOUT_COMMAND (21h) is executed
successfully 5.5ms (typically, worst 6.5ms) after VCC POR and
prior to Enable, it will override the boot-up voltage set by the
PROG1 pin.
OUT
V
OUT
V
< PRECHARGED < OVP
BOOT
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE)
V
BOOT
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
CODE (mV)
PRECHARGED <
0V
V
BOOT
BINARY
CODE
V
BOOT
(V)
HEX CODE
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
0
1
0.7969
0.5000
0.5078
0.5156
0.5234
0.5313
0.5391
0.5469
0.5547
0.5625
0.5703
0.5781
0.5859
0.5938
0.6016
0.6094
0.6172
0.6250
0.6328
0.6406
0.6484
0.6563
66
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
t
t
t
t
D2
D3
D1
D4
EN
2
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
3
PGOOD
4
5
FIGURE 7. SOFT-START WAVEFORMS
6
During t and t , ISL68200 digitally controls the DAC voltage
D2 D4
7
change. The ramp time t and t can be calculated based on
D2 D4
Equations 2 and 3, once the slew rate is set by the PROG4 pin.
8
V
BOOT
9
-------------------------------------
t
=
s
(EQ. 2)
D2
RAMP_RATE
A
V
– V
OUT
BOOT
B
-----------------------------------------
t
=
s
(EQ. 3)
D4
RAMP_RATE
C
The ISL68200 supports precharged start-up, it initiates the first
PWM pulse until the internal reference (DAC) reaches the
pre-charged level at RAMP_RATE, programmed by PROG4 or
D
E
D5[2:0]. When the precharged level is below V
, the output
at RAMP_RATE and releases PGOOD at
BOOT
F
walks up to the V
BOOT
+ t , when the precharged output is above V
10
11
12
13
14
15
t
but below
D1
D2
BOOT
OVP, it walks down to V
at RAMP_RATE and then releases
BOOT
PGOOD at t +t , in which t is defined in Equation 4 and
longer than a normal start-up.
D1 D2
D2
V
V
– V
PRECHARGED BOOT
PRECHARGED
RAMP_RATE
-------------------------------------------- ----------------------------------------------------------------------
s
t
=
+
(EQ. 4)
D2
RAMP_RATE
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ISL68200
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
CODE (mV)
BINARY
CODE
V
BINARY
CODE
V
BOOT
(V)
BOOT
(V)
HEX CODE
16
17
CODE (mV)
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
HEX CODE
3D
3E
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
0.6641
0.6719
0.6797
0.6875
0.6953
0.7031
0.7109
0.7188
0.7266
1.3516
0.8516
0.7344
0.7422
0.7500
0.7578
0.7656
0.7734
0.7813
0.7891
0.7969
0.8047
0.8125
0.8203
0.8281
0.8359
0.8438
0.8516
0.8594
0.8672
0.8750
0.8828
0.8906
0.8984
0.9063
0.9141
0.9219
0.9297
0.9375
0.9453
55
56
57
58
59
5A
5B
5C
5D
AD
6D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
00111101
00111110
00111111
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
0.9531
0.9609
1.5000
0.8984
0.9688
0.9766
0.9844
0.9922
1.0000
1.0078
1.0156
1.0234
1.0313
1.0391
1.0469
1.0547
1.0625
1.0703
1.0781
1.0859
1.0938
1.1016
1.1094
1.1172
1.1250
1.1328
1.1406
1.1484
1.1563
1.1641
1.1719
1.1797
1.1875
1.1953
1.7969
0.9531
1.2031
1.2109
1.2188
7A
7B
C0
73
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
E6
7A
9A
9B
9C
7.8125
7.8125
18
19
1A
1B
1C
1D
1E
3F
40
41
42
43
44
45
46
47
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
5F
60
61
62
63
7.8125
7.8125
7.8125
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ISL68200
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
CODE (mV)
BINARY
CODE
V
BINARY
CODE
V
BOOT
(V)
BOOT
(V)
HEX CODE
64
65
66
67
68
69
6A
6B
6C
6D
6E
CODE (mV)
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
HEX CODE
8B
8C
8D
8E
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
1.2266
1.2344
1.2422
1.2500
1.2578
1.2656
1.2734
1.2813
1.2891
1.2969
1.3047
1.3125
1.3203
1.3281
1.3359
1.3438
1.3516
1.3594
1.3672
1.3750
1.3828
1.3906
1.3984
1.4063
1.4141
1.4219
1.4297
2.5000
1.0000
1.4375
1.4453
1.4531
1.4609
1.4688
1.4766
1.4844
1.4922
1.5000
1.5078
9D
9E
9F
10001011
10001100
10001101
10001110
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
1.5156
1.5234
1.5313
1.5391
1.5469
1.5547
1.5625
1.5703
1.5781
1.5859
1.5938
1.6016
1.6094
1.6172
1.6250
1.6328
1.6406
1.6484
1.6563
1.6641
3.0000
1.0469
1.6719
1.6797
1.6875
1.6953
1.7031
1.7109
1.7188
1.7266
1.7344
1.7422
1.7500
1.7578
1.7656
1.7734
1.7813
1.7891
1.7969
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
140
80
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
8F
90
91
92
93
94
95
96
97
6F
70
71
98
99
9A
9B
9C
9D
9E
72
73
74
D0
D1
D2
D3
D4
D5
180
86
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
75
76
77
78
79
7A
7B
7C
7D
7E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7F
80
81
82
83
84
85
86
87
88
89
8A
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
AF
B0
B1
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ISL68200
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
TABLE 7. PROG1 8-BIT (BOOT-UP VOLTAGE) (Continued)
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
VOUT
COMMAND
CODE (HEX)
DELTA FROM
PREVIOUS
CODE (mV)
BINARY
CODE
V
BINARY
CODE
V
BOOT
(V)
BOOT
(V)
HEX CODE
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
CODE (mV)
7.8125
7.8125
7.8125
7.8125
7.8125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
HEX CODE
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
1.8047
1.8125
1.8203
1.8281
1.8359
1.9141
1.9922
2.0703
2.1484
2.2266
2.3047
2.3828
2.4609
3.2969
1.1016
2.4688
2.4766
2.4844
2.4922
2.5000
2.5078
2.5156
2.5234
2.6016
2.6797
2.7578
2.8359
2.9141
2.9922
3.0703
3.1484
3.2266
3.2813
3.2891
3.2969
3.3047
3.3125
3.3203
3.3281
E7
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
3.4063
3.4844
3.5625
3.6406
3.7188
3.7969
5.0000
1.2031
3.8750
3.9531
4.0313
4.1094
4.1875
4.2656
4.3438
4.4219
4.5000
4.5781
4.6563
4.7344
4.8125
4.8906
4.9688
4.9766
4.9844
4.9922
5.0000
5.0078
5.0156
5.0234
5.0313
5.1094
5.1875
5.2656
5.3438
5.4219
5.4922
5.5000
0
1B4
1BE
1C8
1D2
1DC
1E6
280
9A
78.125
78.125
78.125
78.125
78.125
78.125
E8
E9
EA
EB
F5
FF
109
113
11D
127
131
13B
1A6
8D
1F0
1FA
204
20E
218
222
22C
236
240
24A
254
25E
268
272
27C
27D
27E
27F
280
281
282
283
284
28E
298
2A2
2AC
2B6
2BF
2C0
0
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
78.125
78.125
78.125
78.125
78.125
70.3125
7.8125
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
13C
13D
13E
13F
140
141
142
143
14D
157
161
16B
175
17F
189
193
19D
1A4
1A5
1A6
1A7
1A8
1A9
1AA
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
78.125
54.6875
7.8125
7.8125
7.8125
7.8125
7.8125
7.8125
EF
F0
F1
F2
F3
F4
F5
CF
F6
D0
D1
D2
D3
D4
D5
D6
D7
D8
F7
F8
F9
FA
FB
FC
FD
FE
FF
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ISL68200
-7
As shown in Table 7, 1 step is 2 = 7.8125mV; some selections
are higher than 1 step from adjacent codes. However, the
resolution is ±7.8125mV around the popular voltage regulation
points, as in Table 3 on page 11, for fine tune purpose. For finer
than 7.8125mV tuning, a large ratio resistor divider can be
The inductor DCR value will increase as the temperature
increases. Therefore, the sensed current will increase as the
temperature of the current sense element increases. In order to
compensate the temperature effect on the sensed current signal,
the integrated temperature compensation function of ISL68200
should be utilized. The integrated temperature compensation
function is described in “Thermal Monitoring and Compensation”
on page 17.
placed on the VSEN pin between the output (V
positive offset or V for negative offset, as in Figure 8.
) and RGND for
OUT
CC
V
CC
V
IN
I
s
L
V
OUT
V
OUT
VSEN
VSEN
L
+
-
DCR
V
OUT
+
-
DRIVER
INDUCTOR
-
C
OUT
V
L
ISL68200
INTERNAL CIRCUIT
RGND
A. V
PLACE THESE IN CLOSE
PROXIMITY TO ISL68200
B. V
OUT
LOWER THAN DAC
HIGHER THAN DAC
OUT
-
(s)
OPTIONAL
V
C
I
FIGURE 8. EXTERNAL PROGRAMMABLE REGULATION
OUT
R
C
Current Sensing
R
ISEN
CURRENT
SENSE
The ISL68200 supports inductor DCR sensing, or resistive
sensing techniques, and senses current continuously for fast
response. The current sense amplifier uses the CSEN and CSRTN
inputs to reproduce a signal proportional to the inductor current,
CSEN
+
-
CSRTN
I . The sense current, I
, is proportional to the inductor current
L
SEN
and is used for current reporting and overcurrent protection.
DCR
= I -------------------
I
SEN
L
R
ISEN
The input bias current of the current sensing amplifier is typically
10s of nA; less than 15kΩ input impedance connected to CSEN
pin is preferred to minimize the offset error, i.e., use a larger C
value (select 0.22µF to 1µF instead of 0.1µF when needed). In
addition, the current sensing gain resistor connected to CSRTN
pin should be within 40Ωto 3.5kΩ.
FIGURE 9. DCR SENSING CONFIGURATION
RESISTIVE SENSING
For accurate current sense, a dedicated current-sense resistor
R
, in series with each output inductor can serve as the current
SENSE
INDUCTOR DCR SENSING
sense element (see Figure 10). This technique, however, reduces
overall converter efficiency due to the additional power loss on the
current sense element R
An inductor’s winding is characteristic of a distributed resistance,
as measured by the DCR (Direct Current Resistance) parameter.
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 9.
.
SENSE
I
L
The voltage on the capacitor V , can be shown to be proportional
C
L
R
ESL
V
SEN
R
OUT
to the inductor current I as in Equation 5.
L ,
L
C
SENSE
OUT
-------------
s
+ 1 DCR I
-
L
(EQ. 5)
V
DCR
R
--------------------------------------------------------------------
V
s =
C
ISL68200
INTERNAL CIRCUIT
s RC + 1
PLACE THESE IN CLOSE
PROXIMITY TO ISL68200
If the R-C network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
I
-
(s)
R
OUT
V
C
OPTIONAL
(= L/DCR), the voltage across the capacitor V is equal to the
voltage drop across the DCR. With the internal low-offset current
C
CURRENT
SENSE
C
CSEN
amplifier, the capacitor voltage V is replicated across the sense
R
C
ISEN
+
resistor R
ISEN
is proportional to the inductor current.
. Therefore, the current out of the CSRTN pin, I
,
SEN
-
CSRTN
Equation 6 shows that the ratio of the inductor current to the
R
SEN
I
sensed current, I , is driven by the value of the sense resistor
-----------------
= I
SEN
SEN
L
R
ISEN
and the DCR of the inductor.
DCR
-----------------
I
= I
FIGURE 10. SENSE RESISTOR IN SERIES WITH INDUCTORS
(EQ. 6)
SEN
L
R
ISEN
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ISL68200
A current sensing resistor has a distributed parasitic inductance,
known as ESL (equivalent series inductance, typically less than
1nH) parameter. A simple R-C network across the current sense
on current sensing will not provide a fast OCP response and hurt
system reliability.
resistor extracts the R
page 16.
voltage, as shown in Figure 10 on
SEN
LOAD
The voltage on the capacitor V , can be shown to be proportional
C
to the inductor current I , see Equation 7.
L
VIOUT
ESL
---------------
s
+ 1 R
I
SEN L
R
SEN
FIGURE 13. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
(EQ. 7)
V
s = -------------------------------------------------------------------------
C
s RC + 1
If the R-C network components are selected such that the RC
time constant matches the ESL-R time constant
SEN
), the voltage across the capacitor V is equal
LOAD
(R*C = ESL/R
SEN
to the voltage drop across the R
C
, i.e., proportional to the
SEN
inductor current. As an example, a typical 1mΩ sense resistor
can use R = 348 and C = 820pF for the matching. Figures 11 and
12 show the sensed waveforms without and with matching RC
when using resistive sense.
V
IOUT
FIGURE 14. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO SMALL
LOAD
FIGURE 11. VOLTAGE ACROSS R WITHOUT RC
V
IOUT
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO LARGE
FIGURE 12. VOLTAGE ACROSS C WITH MATCHING RC
Note that the integrated thermal compensation applies to the DC
current, but not the AC current; therefore, the peak current seen
by the controller will increase as the temperature decreases and
can potentially trigger an OCP event. To overcome this issue, the
RC should be over-matching L/DCR at room temperature by
(-40°C +25°C) * 0.385%/°C = +25% for -40°C operation.
Equation 8 shows that the ratio of the inductor current to the
sensed current, I
, is driven by the value of the sense resistor
SEN
and the R
.
ISEN
R
SEN
(EQ. 8)
-----------------
I
= I
SEN
L
R
ISEN
Thermal Monitoring and Compensation
The block diagram of thermal monitoring function is shown in
Figure 16 on page 18. One NTC resistor should be placed close to
the respective power stage of the voltage regulator VR to sense
the operational temperature and pull-up resistors are needed to
form the voltage dividers for the NTC pin. As the temperature of
the power stage increases, the resistance of the NTC will reduce,
resulting in the reduced voltage at the NTC pin. Figure 18 on
page 18 shows the TM voltage over the temperature for a typical
design with a recommended 10kΩ NTC (P/N:
L/DCR OR ESL/R
MATCHING
SEN
Figure 13 shows the expected load transient response waveforms
if L/DCR or ESL/R is matching the R-C time constant. When
SEN
the load current has a square change, the IOUT pin voltage (V
without a decoupling capacitor also has a square response.
)
IOUT
However, there is always some PCB contact impedance of current
sensing components between the two current sensing points; it
hardly accounts into the L/DCR or ESL/R
Fine tuning the matching is necessarily done at the board level to
improve overall transient performance and system reliability.
matching calculation.
SEN
NCP15XH103J03RC from Murata, = 3380) and 1.54kΩ resistor
R
. It is recommended to use those resistors for the accurate
TM
temperature compensation since the internal thermal digital
code is developed based upon these two components. If a
different value is used, the temperature coefficient must be close
If the R-C timing constant is too large or too small, V (s) will not
C
accurately represent real-time output current and will worsen the
overcurrent fault response. Figure 14 shows the IOUT pin
transient voltage response when the R-C timing constant is too
to 3380 and R must be scaled accordingly. For instance, say
TM
NTC = 20kΩ ( = 3380), then R should be
20kΩ/10kΩ*1.54kΩ = 3.08kΩ.
small. V
will sag excessively upon load insertion and may
TM
IOUT
create a system failure or early overcurrent trip. Figure 15 shows
the transient response when the R-C timing constant is too large.
V
is sluggish in reaching its final value. The excessive delay
IOUT
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17
ISL68200
to the NTC temperature of the practical design should be similar
to that in Figure 18.
VCC
THERMAL TRIP
+136°C/+122ºC
100
90
80
70
60
50
40
30
20
RTM
NTC
+
OTP
-
RNTC
BETA~ 3380
ºC
ISL68200
FIGURE 16. BLOCK DIAGRAM OF THERMAL MONITORING AND
PROTECTION
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
The ISL68200 supports inductor DCR sensing, or resistive
sensing techniques. The inductor DCR has a positive temperature
coefficient, which is about +0.385%/°C. Since the voltage across
the inductor is sensed for the output current information, the
sensed current has the same positive temperature coefficient as
the inductor DCR. In order to obtain the correct current
information, the ISL68200 utilizes the voltage at the NTC pin and
“TCOMP” register to compensate the temperature impact on the
sensed current. The block diagram of this function is shown in
Figure 17.
FIGURE 18. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE
WITH RECOMMENDED PART
Since the NTC attaches to the PCB, but not directly to the current
sensing component, it inherits high thermal impedance between
the NTC and the current sensing element. The “TCOMP” register
values can be utilized to correct the temperature difference
between NTC and the current sense component. As shown in
Figure 19, the NTC should be placed in proximity to the output
rail; DON’T place it close to the MOSFET side, which generates
much more heat.
VCC
ISL68200
CHANNEL
CURRENT
SENSE
CSSEN
CSRTN
RTM
NTC
OUTPUT
INDUCTOR
NON-LINEAR
A/D
NTC
VOUT
POWER STAGE
IPH
oc
RNTC
k
i
D/A
PLACE NTC
CLOSE TO
INDUCTOR
FIGURE 19. RECOMMENDED PLACEMENT OF NTC
The ISL68200 multiplexes the “TCOMP” value with the NTC
digital signal to obtain the adjustment gain to compensate the
temperature impact on the sensed channel current. The
IOUT MONITOR AND
OVERCURRENT
PROTECTION
A/D
TCOMP
compensated current signal is used for I and overcurrent
OUT
protection functions. The TCOMP “OFF” code is to disable thermal
compensation when the current sensing element is the resistor
or smart power stage (internally thermal compensated) that has
little thermal drifting.
FIGURE 17. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE
COMPENSATION
When the NTC is placed close to the current sense component
(inductor), the temperature of the NTC will track the temperature
of the current sense component. Therefore, the NTC pin voltage
can be utilized to obtain the temperature of the current sense
component. Since the NTC could pick up noise from the phase
node, a 0.1µF ceramic decoupling capacitor is recommended on
the NTC pin in close proximity to the controller.
TABLE 8. “TCOMP” VALUES
D1h
0h
TCOMP (°C)
D1h
2h
TCOMP (°C)
30
15
5
1h
3h
OFF
Based on the VCC voltage, the ISL68200 converts the NTC pin
voltage to a digital signal for temperature compensation. With
the nonlinear A/D converter of the ISL68200, the NTC digital
signal is linearly proportional to the NTC temperature. For
accurate temperature compensation, the ratio of the NTC voltage
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ISL68200
Thermal compensation design procedure for inductor current
sensing is summarized as follows:
63.875A load current. The IOUT voltage is linearly digitized every
108µs and stored in the READ_IOUT register (8Ch).
1. Properly choose the voltage divider for the NTC pin to match
the NTC voltage vs temperature curve with the recommended
curve in Figure 18 on page 18.
EXTERNAL CIRCUIT
ISL68200
VCC
2. Run the actual board under the full load and the desired
airflow condition.
R
IOUT_UP
3. After the board reaches the thermal steady state (often takes
15 minutes), record the temperature (T
sense component (inductor) and the voltage at NTC and VCC
pins.
) of the current
CSC
IOUT
DIGITIZED
IOUT (8Ch)
R
IOUT_DW
4. Use Equation 9 to calculate the resistance of the NTC, and
find out the corresponding NTC temperature T
from the
NTC
NTC datasheet or using Equation 10, where is equal to 3380
for recommended NTC.
FIGURE 20. IOUT NO LOAD OFFSET CALIBRATION
V
xR
TM
TM
(EQ. 9)
R
@T
= -----------------------------
A small capacitor can be placed between IOUT and GND to
reduce the noise impact and provide averaging, > 200µs
(typically).
NTC
NTC
V
– V
CC
TM
-------------------------------------------------------------------------------
T
=
– 273.15
NTC
0
R
@25 C
To deal with layout and design variation of different platforms,
ISL68200 is intentionally trimmed to negative at no load, thus,
an offset can easily be added to calibrate the digitized IOUT
reading (8Ch). Hence, the analog vs digitized current slope is set
NTC
(EQ. 10)
------------------------------------------
-----------------
ln
+
R
@T
NTC
298.15
NTC
5. Choose a number close to the result as in Equation 11 for the
“TCOMP” register.
by the equivalent impedance of R
//R
=R
IOUT_UP
IOUT_DW
IOUT
(as in Figure 20); the slope of the ideal curve should set to 1 A/A
with 0A offset.
T
= T
– T
CSC NTC
(EQ. 11)
COMP
6. Run the actual board under full load again.
For a precision digital I , follow the fine-tune procedure below
OUT
step-by-step; steps 1 to 5 must be completed before step 6.
7. Record the IOUT pin voltage as V1 immediately after the
output voltage is stable with the full load. Record the IOUT pin
voltage as V2 after the VR reaches the thermal steady state.
1. Properly tune L/DCR or ESL/R
SEN
matching as shown on
page 17 over the range of temperature operation. +25% over-
matching L/DCR at room temperature is needed for -40°C
operation.
8. If the IOUT pin voltage increases over 10mV as the
temperature increases, i.e., V2 - V1 > 10mV, reduce “TCOMP”
value. If the IOUT pin voltage decreases over 10mV as the
temperature increases, i.e., V1 - V2 > 10mV, increase
“TCOMP” value. “TCOMP” value can be adjusted via the series
bus for easy thermal compensation optimization.
2. Properly complete thermal compensation as shown on
“Thermal Monitoring and Compensation” on page 17.
3. Finalize R
ISEN
resistor to set OCP for overall operating
conditions and board variations as shown in “Overcurrent and
Short-Circuit Protection” on page 20.
I
Calibration
OUT
4. Collect no load I
OUT
current with sufficient prototypes and
current.
The current flowing out of the IOUT pin is equal to the sensed
average current inside ISL68200. A resistor is placed from the
IOUT pin to GND to generate a voltage, which is proportional to
the load current and the resistor value, as shown in Equation 12:
determine the mean of no load I
OUT
5. The pull-up impedance on IOUT pin should be
“VCC/IOUT_NO_LOAD”; for instance, a mean of -2.5µA I
at
OUT
0A load, it will need R
= 2MΩ.
IOUT_UP
R xI
x
OCP
6. Start with the value below and then fine tune the R
IOUT_DW
------------------------
2.5Vx
2.5VxR
100A
ISEN
R
= ---------------------------------- = -----------------------------------------------
value until the average slope of various boards equals 1A/A.
IOUT
63.875AxR
63.875AxR
x
x
(EQ. 12)
R
xR
IOUT
–R
IOUT
IOUT_UP
(EQ. 13)
--------------------------------------------------
=
R
IOUT_DW
2.5VxI
25VxI
R
OCP
OCP
IOUT_UP
--------------------------------------------
----------------------------
k
=
=
63.875Ax100A
63.875A
Where V
IOUT
between the IOUT pin and GND, I
is the voltage at the IOUT pin, R
is the resistor
is the total output current
IOUT
LOAD
is the sense resistor connected to the
of the converter, R
ISEN
CSRTN pin and R is the DC resistance of the current sense
X
element, either the DCR of the inductor or R
depending on
SENSE
resistor should be scaled to
the sensing method. The R
IOUT
ensure that the voltage at the IOUT pin is typically 2.5V at
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ISL68200
overvoltage threshold (typically 120%). By doing so, the IC protects
the load when there is a consistent overvoltage condition.
Fault Protection
The ISL68200 provides high system reliability with many fault
protections, as summarized in Table 9.
In addition to normal operation OVP, 5.5ms (typically, worst
6.5ms) after all rails (VCC, PVCC, 7VLDO, VIN) POR and prior to
the end of soft-start, the start-up OVP circuits are enabled to
protect against OVP event, while the OVP level is set higher than
TABLE 9. FAULT PROTECTION SUMMARY
FAULT
DESCRIPTION
FAULT ACTION
V
. See Electrical Specifications on page 7.
Input UVLO VIN pin UVLO; or set by EN pin with Shutdown and recover
BOOT
an external divider for higher
level. See Figures 4 and 5.
when VIN > UVLO
UNDERVOLTAGE PROTECTION
The UVP fault detection circuit triggers after the output voltage is
below the undervoltage threshold (typically 74% of DAC). When an
UVP fault is declared, the controller will be latched off, forcing the
LGATE and UGATE gate-driver outputs low, and the PGOOD pin will
be asserted low. The fault will remain latched and can be reset by
VCC cycling or toggling EN pin and/or series bus OPERATION
command based upon ON_OFF_CONFIG setting.
Bias UVLO
VCC, PVCC, 7VLDO UVLO
Shutdown and recover
when Bias > UVLO
Start-Up
OVP
Higher than V . See Electrical Latch OFF, reset by VCC
BOOT
Specifications on page 7.
or toggling Enable
(including EN pin and/
or OPERATION
command based upon
ON_OFF_CONFIG
setting)
Output OVP Rising = 116%; Falling = 100%
Output UVP 74% of V , Latch OFF
OUT
OVERCURRENT AND SHORT-CIRCUIT PROTECTION
Output OCP Average OCP = 100µA with
128µs blanking time.
Latch OFF (reset by
VCC or toggling enable
including EN pin and/
or OPERATION
command based upon
ON_OFF_CONFIG
setting), or retry every
9ms; option is
programmable by
PROG3 or D3[0]
The average Overcurrent Protection (OCP) is triggered when the
internal current out of the IOUT pin goes above the fault
threshold (typically 100µA) with 128µs blanking time. It also has
a fast (50ns filter) secondary overcurrent protection whose
threshold is +30% above average OCP; this protects inductor
saturation from a short-circuit event and provides a more robust
power train and system protection. When an OCP or short-circuit
fault is declared, the controller will be latched off, forcing the
LGATE and UGATE gate-driver outputs low, or retry with a hiccup
time of 9ms; the fault response is programmable by PROG3 or
D3[0]. The latched off event however can be reset by VCC cycling
or toggling EN pin and/or series bus OPERATION command
Short-Circuit Peak OCP = 130% of Average
Protection
OCP with 50ns filter.
OTP
Rising = 22.31%VCC (~+136°C); Shut down above
Falling =27.79%VCC (~+122°C). +136°C and recover
when temperature
based upon ON_OFF_CONFIG setting
drops below +122°C
.
Equation 14 provides a starting point to set a preliminary OCP trip
Input UVLO and OTP faults will respond to the current state with
hysteresis, while output OVP and output UVP faults are latch
events, while output OCP and output short-circuit faults can be
latch or retry events depending upon PROG3 or D3[0] setting. All
fault latch events can be reset by VCC cycling, toggling the Enable
pin and/or series bus OPERATION command based upon
ON_OFF_CONFIG setting, while the OCP retry event has a hiccup
time of 9ms and the regulator can be recovered when the fault is
removed.
point, where I
is the targeted OCP trip point and I (as in
OCP
Equation 15 on page 28) is the peak-to-peak inductor ripple
current.
R xI
x
OCP
R
= ------------------------
ISEN1
100A
I
2
(EQ. 14)
-----
R x
+ I
x
OCP
R
R
= -------------------------------------------------------------
ISEN2
ISEN
100Ax100% + 30%
OVERVOLTAGE PROTECTION
= MAX (R
R
ISEN2
ISEN1,
The OVP fault detection circuit triggers after the voltage between
VSEN+ and VSEN- is above the rising overvoltage threshold. When
an OVP fault is declared, the controller will be latched off and the
PGOOD pin will be asserted low. The fault will remain latched and
can be reset by VCC cycling or toggling EN pin and/or series bus
To deal with layout and PCB contact impedance variation, follow
the fine tune procedure below step-by-step for a more precision
OCP; steps 1 to 3 must be completed before step 4.
1. Properly tune L/DCR or ESL/R
SEN
matching as shown on
OPERATION command based upon ON_OFF_CONFIG setting
.
page 17 over the range of temperature operation. +25%
over-matching L/DCR at room temperature is needed for
-40°C operation.
Although the controller has latched-off in response to an OVP
fault, the LGATE gate-driver output will retain the ability to toggle
the low-side MOSFET on and off, in response to the output
voltage transversing the OVP rising and falling thresholds. The
LGATE gate-driver will turn on the low-side MOSFET to discharge
the output voltage, protecting the load. The LGATE gate driver will
turn off the low-side MOSFET once the sensed output voltage is
lower than the falling overvoltage threshold (typically 100%). If
the output voltage rises again, the LGATE driver will again turn on
the low-side MOSFET when the output voltage is above the rising
2. Properly complete thermal compensation as shown on
“Thermal Monitoring and Compensation” on page 17.
3. Collect OCP trip points (IOCP_MEASURED) with sufficient
prototypes and determine the means for overall operating
conditions and board variations.
4. Change R
by IOCP_TARGETED/IOCP_MEASURED
percentage to meet the targeted OCP.
ISEN
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ISL68200
Note that if the inductor peak-to-peak current is higher or closer
PFM Mode Operation
to 30%, the +30% threshold could be triggered instead of the
average OCP threshold. However, the fine tune procedure still can
be used.
In PFM mode, programmable by PROG2 or series bus D0[0:0],
the switching frequency is dramatically reduced to minimize the
switching loss and significantly improve light-load efficiency. The
ISL68200 can enter and exit PFM mode seamlessly as load
OVER-TEMPERATURE PROTECTION
changes. For high V
applications implemented with high Qg
OUT
As shown in Figure 16, there is a comparator with hysteresis to
compare the NTC pin voltage to the threshold set. When the NTC
pin voltage is lower than 22.31% of VCC voltage (typically
+136°C), it triggers Over-Temperature Protection (OTP) and shuts
down ISL68200 operation, when the NTC pin voltage is above
27.79% of VCC voltage (typically +122.4°C), it will resume
normal operation. When an OTP fault is declared, the controller
will force the LGATE and UGATE gate-driver outputs low.
MOSFETs, the LGATE might not turn on long enough to charge the
boot capacitor in PFM mode with 0A load. It is recommended to
enable ISL68200’s ultrasonic PFM feature (by PROG3 or series
bus D2[0:0]), which maintains LGATE switching frequency above
20kHz and keeps the boot capacitor charged for immediate load
apply event. Alternatively, an external Schottky diode or
maintaining a minimum load can enhance the boot capacitor
charge.
PGOOD Monitor
2
SMBus, PMBus and I C Operation
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. If there is a fault condition of a rail’s
(VCC, PVCC, 7VLDO, or VIN) UVLO, output Overcurrent (OCP),
Overvoltage (OVP), Undervoltage (UVP), or Over-Temperature (OTP),
PGOOD is asserted low. Note that the PGOOD pin is an undefined
2
The ISL68200 features SMBus, PMBus and I C with 32
programmable addresses via PROG2 pin, while SMBus/PMBus
includes an Alert# line (SALERT) and Packet Error Check (PEC) to
ensure data properly transmitted. The telemetry update rate is
108µs (Typically). The supported SMBus/PMBus/I C addresses
are summarized in Table 10. The 7-bit format address does not
include the last bit (write and read): 40-47h, 60-67h and 70-7Fh.
2
impedance with insufficient V (typically <2.5V).
CC
Adaptive Shoot-Through Protection
2
SMBus/PMBus/I C allows to program the registers as in
Table 11, except for SMBus/PMBus/I C addresses, 5.5ms
(typically, worst 6.6ms) after all rails (VCC, PVCC, 7VLDO and VIN)
above POR. Figures 22 and 23 on page 22 show the initialization
timing diagram for the series bus with different state of EN
(enable) pin.
The LGATE and UGATE pins are MOSFET driver outputs. The
LGATE pin drives the low-side MOSFET of the converter while the
UGATE pin drives the high-side MOSFET of the converter. Adaptive
shoot-through protection prevents a gate-driver output from
turning on until the opposite gate-driver output has fallen below
approximately 1V. The dead time shown in Figure 21 is extended
by the additional period that the falling gate voltage remains
above the 1V threshold. The high-side gate-driver output voltage
is measured across the UGATE and PHASE pins while the low-side
gate-driver output voltage is measured across the LGATE and
GND pins.
2
For proper operation, users should follow the SMBus, PMBus and
I C protocol, as shown Figure 24 on page 23. Note that STOP (P)
bit is NOT allowed before the repeated START condition when
“reading” contents of register.
2
When the device’s series bus is not used, simply ground the
device’s SCL, SDA and SALERT pins and do not connect them to
the bus.
2
TABLE 10. SMBus/PMBus/I C 7-BIT FORMAT ADDRESS (HEX)
7-BIT ADDRESS
7-BIT ADDRESS
7-BIT ADDRESS
UGATE-PHASE
40
41
42
43
44
45
46
47
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
1V
1V
t
t
UGFLGR
LGFUGR
1V
1V
LGATE-GND
FIGURE 21. GATE DRIVE ADAPTIVE SHOOT-THROUGH PROTECTION
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ISL68200
VIN, PVCC,
7VLDO,
VCC
200µs
SS DELAY
WRITE AND READ
CONFIGURATION
WRITE AND READ
CONFIGURATION
WRITE AND READ
CONFIGURATION
WRITE AND READ
CONFIGURATION
VCC POR
TIMEOUT
READER
DONE
0ms TO INFINITY
5ms
0.5ms
0ms TO INFINITY
ENABLE
PMBus COMMUNICATION
NOT ACTIVATED
PMBus
COMMAND
PMBus
COMMAND
PMBus
COMMAND
PMBus
COMMAND
VBOOT
0V
VOUT
2
FIGURE 22. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM WITH ENABLE LOW
VIN, PVCC,
7VLDO,
VCC
200 µs
SS DELAY
WRITE AND READ
CONFIGURATION
WRITE AND READ
CONFIGURATION
READER
DONE
0.5ms
VCC POR
TIMEOUT
5ms
WRITE AND READ
CONFIGURATION
0ms TO INFINITY
ENABLE
PMBus COMMUNICATION
NOT ACTIVATED
PMBus
COMMAND
PMBus
COMMAND
PMBus
COMMAND
VBOOT
VOUT
0V
2
FIGURE 23. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM WITH ENABLE HIGH
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ISL68200
S: Start Condition
1. Send Byte Protocol
A: Acknowledge (“0”)
1
7 + 1
1
8
1
8
1
1
N: Not Acknowledge (“1”)
S
A
Command Code
Slave Address_0
A
PEC
A
P
W: Write (“0”)
RS: Repeated Start Condition
R: Read (“1”)
Optional 9 Bits for SMBus/PMBus
2
PEC: Packet Error Checking
P: Stop Condition
NOT used in I C
Example command: 03h Clear Faults
(This will clear all of the bits in Status Byte for the selected Rail)
Acknowledge or DATA from Slave,
ISL68200
Not Used for One Byte Word
2. Write Byte/Word Protocol
1
7 + 1
1
8
1
8
1
8
1
8
1
1
S
A
Command Code
Slave Address_0
A
A
High Data Byte
Low Data Byte
A
PEC
A
P
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
Example command: D0h ENABLE_PFM (one word, High Data Byte and ACK are not used)
3. Read Byte/Word Protocol
1
7 + 1
1
8
1
Not Used for One Byte Word Read
S
Slave Address_0
A
Command Code
A
1
7 + 1
1
8
1
8
1
8
1
1
RS
A
Low Data Byte
Slave Address_1
A
High Data Byte
A
PEC
P
N
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
Example command: 8B READ_VOUT (Two words, read voltage of the selected rail).
NOTE: That all Writable commands are read with one byte word protocol.
STOP (P) bit is NOT allowed before the repeated START condition when “reading” contents of a register.
4. Block Write Protocol
1
7 + 1
1
8
1
8
1
8
1
8
1
S
A
Command Code
Slave Address_0
A
A
Lowest Data Byte
Byte Count = N
A
Data Byte 2
A
1
1
8
8
1
1
Data Byte N
A
A
PEC
A
P
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
Example command: ADh IC_DEVICE_ID (2 Data Byte)
2
FIGURE 24. SMBus/PMBus/I C COMMAND PROTOCOL
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ISL68200
5. Block Read Protocol
1
7 + 1
1
1
1
1
8
1
7 + 1
8
8
S
Byte Count = N
Lowest Data Byte
A
Command Code
A
A
Slave Address_0
A
RS
Slave Address_1
1
8
1
1
8
8
1
1
Data Byte 2
A
A
Data Byte N
A
PEC
P
N
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
Example command: 8B READ_VOUT (Two words, read voltage of the selected rail).
NOTE: That all Writable commands are read with one byte word protocol.
STOP (P) bit is NOT allowed before the repeated START condition when “reading” contents of a register.
6. Group Command Protocol - No more than one command can be sent to the same Address
1
7 + 1
1
1
8
8
1
8
1
8
1
S
Slave ADDR1_0
A
Command Code
A
A
High Data Byte
Low Data Byte
A
PEC
A
1
7 + 1
8
1
1
8
1
8
1
RS
A
Command Code
Data Byte
A
Slave ADDR2_0
A
PEC
A
1
8
1
7 + 1
8
1
1
8
1
8
1
1
Command Code
A
RS
A
Low Data Byte
A
High Data Byte
A
Slave ADDR3_0
PEC
A
P
Optional 9 Bits for SMBus/PMBus
2
NOT used in I C
2
FIGURE 25. SMBus/PMBus/I C COMMAND PROTOCOL
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ISL68200
2
TABLE 11. SMBus, PMBus, AND I C SUPPORTED COMMANDS
WORD
LENGTH
(BYTE)
COMMAND
CODE
DEFAULT
VALUE
ACCESS
R/W
COMMAND NAME
OPERATION
DESCRIPTION
01h[7:0]
ONE
80h
VR Enable (depending upon ON_OFF_CONFIG configuration):
Bit[7]: 0 = OFF (0-F); 1 = ON (80-8Fh)
Bit[6:4] = 0
Bit[3:0] = Don’t care
02h[7:0]
R/W
ONE
1Fh
ON_OFF_CONFIG
Configure VR Enabled by OPERATION and/or EN pin:
Bit[7:5] = 0
Bit[4] = 1
Bit[3] = OPERATION command Enable
0h = OPERATION command has no control on VR
1h = OPERATION command can turn ON/OFF VR
Bit[2] = CONTROL pin Enable
0h = EN Pin has no control on VR
1h = EN pin can turn ON/OFF VR
Bit[1] = 1
Bit[0] = 1
Bit[3:2] = 00b = 13h (ALWAYS ON)
Bit[3:2] = 01b = 17h (EN controls VR)
Bit[3:2] = 10b = 1Bh (OPERATION controls VR)
Bit[3:2] = 11b = 1Fh (EN and OPERATION control VR)
03h
SEND BYTE
R
N/A
ONE
CLEAR_FAULTS
VOUT_MODE
Clear faults in status registers
20h[7:0]
19h
Set host format of VOUT command.
Always Linear Format: N = -7
21h[2:0]
R/W
R/W
TWO
TWO
PROG1[7:0]
VBOOT+500mV
VOUT_COMMAND
VOUT_MAX
Set output voltage
-7
HEX Code = DEC2HEX [ROUND(V
/2 )]
OUT
24h[15:0]
Set maximum output voltage that VR can command
(DAC ≤ VOUT_MAX). Linear Format. N = -7
HEX Code = DEC2HEX(ROUNDUP(VOUT_MAX/ 2
-7
)
33h[15:0]
R/W
TWO
PROG3[5:3]
FREQUENCY_SWITCH Set VR Switching Frequency (In Linear Format)
Support 8 options (N = 0):
12Ch = 300kHz; 190h = 400kHz; 1F4h = 500kHz
258h = 600kHz; 2BCh = 700kHz; 352h = 850kHz
3E8h = 1MHz; 5DCh = 1.5MHz*
* Very high frequency is not recommended for very high duty cycle
applications as the boot capacitor will not has enough time to be
charged due to low LGATE ON time.
78h[8:0]
R
ONE
STATUS_BYTE
Fault Reporting;
Bit7 = Busy
Bit6 = OFF (Reflect current state of operation and ON_OFF_CONFIG
registers as well as VR Operation)
Bit5 = OVP
Bit4 = OCP
Bit3 = 0
Bit2 = OTP
Bit1 = Bus communication error
Bit0 = NONE OF ABOVE (OUTPUT UVP, VOUT_COMAND >
VOUT_MAX, or VOUT OPEN SENSE)
88h[15:0]
8Bh[15:0]
8Ch[15:0]
R
R
R
TWO
TWO
TWO
READ_VIN
READ_VOUT
READ_IOUT
Input Voltage (N = - 4, Max = 31.9375V)
VIN (V) = HEX2DEC(88 hex data - E000h) * 0.0625V
-7
VR Output Voltage, Resolution = 7.8125mV = 2
-7
VOUT (V) = HEX2DEC(8B hex data) * 2
VR Output Current (N = -3, IMAX = 63.875A)
IOUT (A) = HEX2DEC(8C hex data-E800) * 0.125A when IOUT pin
voltage = 2.5V at 63.875A load.
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ISL68200
2
TABLE 11. SMBus, PMBus, AND I C SUPPORTED COMMANDS (Continued)
WORD
COMMAND
CODE
LENGTH
(BYTE)
DEFAULT
VALUE
ACCESS
R
COMMAND NAME
READ_TEMP
DESCRIPTION
8Dh[15:0]
TWO
VR Temperature
TEMP (°C) = 1/{ln[Rup*HEX2DEC(8D hex
data)/(511 - HEX2DEC(8D hex data)/RNTC(at +25°C)]/Beta +
1/298.15} -273.15
98h[7:0]
AD[15:0]
AE[15:0]
D0[0:0]
R
ONE
TWO
TWO
ONE
02h
8200h
PMBUS_REVISION
IC_DEVICE_ID
Indicates PMBus Revision 1.2
ISL68200 Device ID
BLOCK R
BLOCK R
R/W
0003h
IC_DEVICE_REVISION ISL68200 Device Revision
PROG2[7:7]
ENABLE_PFM
TEMP_COMP
PFM OPERATION
0h = PFM Enabled (DCM at light load)
1h = PFM Disabled (always CCM mode)
D1[1:0]
D2[0:0]
R/W
R/W
ONE
ONE
PROG2[6:5]
PROG3[7:7]
Thermal Compensation:
0h = 30°C; 01h = 15°C; 02h = 5°C; 03h = OFF
ENABLE_ULTRASONIC Ultrasonic PFM Enable
0h = 25kHz Clamp Disabled
1h = 25kHz Clamp Enabled
D3[0:0]
D4[2:0]
R/W
R/W
ONE
ONE
PROG3[6:6]
PROG3[2:0]
OCP_BEHAVIOR
AV_GAIN
Set latch or infinite retry for OCP fault:
0h = Retry every 9ms; 01 = Latch-OFF
R4 AV GAIN (PROG4, AV Gain Multiplier = 2x)
0h = 84; 1h = 73; 2h = 61; 3h = 49
4h = 38; 5h = 26; 6h = 14; 7h = 2
R4 AV GAIN (PROG4, AV Gain Multiplier = 1x)
0h = 42; 1h = 36.5; 2h = 30.5; 3h = 29.5
4h = 19; 5h = 13; 6h = 7; 7h = 1
D5{2:0]
D6[1:0]
R/W
R/W
ONE
ONE
PROG4[7:5]
PROG4[4:3]
RAMP_RATE
SET_RR
Soft-Start and Margining DVID Rate (mV/µs)
0h = 1.25; 1h = 2.5; 2h = 5; 3h = 10; 4h = 0.078; 5h = 0.157
6h = 0.315; 7h = 0.625;
Set RR
0h = 200k; 01h = 400k; 02h = 600k; 03h = 800k
DC[7:0]
DD{7:0]
DE[7:0]
DF[7:0]
R
R
R
R
ONE
ONE
ONE
ONE
READ_PROG1
READ_PROG2
READ_PROG3
READ_PROG4
Read PROG1
Read PROG2
Read PROG3
Read PROG4
NOTE: Series bus communication is valid 5.5m (typically, worst 6.5ms) after VCC, VIN, 7VLDO and PVCC above POR. The telemetry update rate is 108µs.
STABILITY
R4™ Modulator
The removal of compensation derives from the R4™ modulator’s
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
low frequencies. That, combined with the double-pole from the
output L/C filter, creates a three pole system that must be
compensated to maintain stability.
The R4™ modulator is an evolutionary step in R3™ technology.
Like R3™, the R4™ modulator is a linear control loop and
variable frequency control during load transients to eliminate
beat frequency oscillation at the switching frequency and
maintains the benefits of current-mode hysteretic controllers.
However, in addition, the R4™ modulator reduces regulator
output impedance and uses accurate referencing to eliminate
the need for a high-gain voltage amplifier in the compensation
loop. The result is a topology that can be tuned to voltage-mode
hysteretic transient speed while maintaining a linear control
model and removes the need for any compensation. This greatly
simplifies the regulator design for customers and reduces
external component cost.
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-valley, current-mode hysteric, R3™ and
R4™) generate a zero at or near the L/C resonant point,
effectively canceling one of the system’s poles. The system still
contains two poles, one of which must be canceled with a zero
before unity gain crossover to achieve stability.
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ISL68200
Figure 28 shows the R4™ error-amplifier that does not require an
integrator for high DC gain to achieve accurate regulation. The
result to the open-loop response can be seen in Figure 29.
COMPENSATION TO COUNTER
INTEGRATOR POLE
INTEGRATOR
FOR HIGH DC GAIN
R4™ LOOP GAIN (dB)
V
OUT
V
L/C DOUBLE-POLE
COMP
V
DAC
p1
SYSTEM HAS 2 POLES
FIGURE 26. CLASSICAL INTEGRATOR ERROR-AMPLIFIER
CONFIGURATION
p2
AND 1 ZERO
NO COMPENSATOR IS
NEEDED
CURRENT-MODE
Figure 26 illustrates the classic integrator configuration for a
voltage loop error amplifier. While the integrator provides the
high DC gain required for accurate regulation in traditional
technologies, it also introduces a low-frequency pole into the
control loop. Figure 27 shows the open-loop response that results
from the addition of an integrating capacitor in the voltage loop.
The compensation components found in Figure 26 are necessary
to achieve stability.
ZERO
z1
f (Hz)
FIGURE 29. UNCOMPENSATED R4™ OPEN-LOOP RESPONSE
TRANSIENT RESPONSE
Because R4™ does not require a high-gain voltage loop, the
integrator can be removed, reducing the number of inherent
poles in the loop to two. The current-mode zero continues to
cancel one of the poles, ensuring a single-pole crossover for a
wide range of output filter choices. The result is a stable system
with no need for compensation components or complex
equations to properly tune the stability.
In addition to requiring a compensation zero, the integrator in
traditional architectures also slows system response to transient
conditions. The change in COMP voltage is slow in response to a
rapid change in output voltage. If the integrating capacitor is
removed, COMP moves as quickly as VOUT, and the modulator
immediately increases or decreases switching frequency to
recover the output voltage.
R3™ LOOP GAIN (dB)
INTEGRATOR POLE
I
OUT
t
t
R4™
p1
L/C DOUBLE-POLE
R3™
V
COMP
p2
-20dB CROSSOVER
p3
REQUIRED FOR STABILITY
V
OUT
COMPENSATOR TO
CURRENT-MODE
ADD z2 IS NEEDED
ZERO
z1
t
FIGURE 30. R3™ vs R4™ IDEALIZED TRANSIENT RESPONSE
The dotted red and blue lines in Figure 30 represent the time
f (Hz)
delayed behavior of V
and V in response to a load
OUT
COMP
FIGURE 27. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE
transient when an integrator is used. The solid red and blue lines
illustrate the increased response of R4™ in the absence of the
integrator capacitor.
To optimize transient response and improve phase margin for
very wide range applications, ISL68200 integrates a couple of
selectable AV and RR options that move DC gain and z1 point, as
shown in Figure 27. The defaulted AV gain of 42 and RR of
200kΩ however, can cover many cases and provides sufficient
gain and phase margin. For some extreme cases, lower AV gain
and bigger RR values are needed to provide a better phase
margin and improve transient ringback. The optimal choice AV
and RR can be obtained, by simple monitoring transient
response when playing with AV and RR values via the series bus.
R
2
V
OUT
V
COMP
R
1
V
DAC
FIGURE 28. NON-INTEGRATED R4™ ERROR-AMPLIFIER
CONFIGURATION
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Thus, once the output capacitors are selected, the maximum
allowable ripple voltage, V , determines the lower limit on
General Application Design
Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase buck converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs that include
schematics, bills of materials and example board layouts.
P-P(MAX)
the inductance, as shown in Equation 16.
V
V
V
–
OUT
OUT
IN
(EQ. 16)
L
--------------------------------------------------------------
ESR
OUT
f
V V
IN P–PMAX
SW
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
Output Filter Design
before the output voltage decreases more than V
. This
MAX
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter necessarily limits the system transient response. The
output capacitor must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
places an upper limit on inductance.
Equation 17 gives the upper limit on L for cases when the trailing
edge of the current transient causes a greater output-to-voltage
deviation than the leading edge. Equation 18 addresses the
leading edge. Normally, the trailing edge dictates the selection of
L because duty cycles are usually less than 50%. Nevertheless,
both inequalities should be evaluated, and L should be selected
based on the lower of the two results. In each equation, L is the
per-channel inductance, C is the total output capacitance.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I; the load current slew rate,
di/dt; and the maximum allowable output voltage deviation under
2 C V
OUT
(EQ. 17)
L
---------------------------------- V
– I ESR
OUT
MAX
2
I
(EQ. 18)
C
1.25
L
--------------------- V
– I ESR
V
– V
IN OUT
OUT
MAX
2
I
transient loading, V
. Capacitors are characterized according
MAX
to their capacitance, ESR and ESL (equivalent series inductance).
Input Capacitor Selection
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL and
ESR so that the total output voltage deviation is less than the
allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 15:
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases. The input
RMS current can be calculated with Equation 19.
D
12
(EQ. 19)
2
2
2
------
I
=
D – D Io
+
I
IN RMS
Use Figure 31 to determine the input capacitor RMS current
requirement given the duty cycle, maximum sustained output
current (I ), and the ratio of the per-phase peak-to-peak inductor
ESL
1
I
(EQ. 15)
---------------
---------------- -----------------------------
V I ESR +
V
+
IN
L
C
8 N f
OUT
OUT
SW
O
current (I
to I . Select a bulk capacitor with a ripple current
V
1 – D
L(P-P)
O
OUT
L
---------------------------------------
I=
rating, which will minimize the total number of input capacitors
required to support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage.
f
OUT
SW
The filter capacitor must have sufficiently low ESL and ESR so
that V < V
.
MAX
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates
produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each
upper MOSFET drain to minimize board parasitic impedances
and maximize noise suppression.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with bulk
capacitors having high capacitance but limited high-frequency
performance. Minimizing the ESL of the high-frequency capacitors
allows them to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply the
increased current with less output voltage deviation. The ESR of the
bulk capacitors also creates the majority of the output voltage
ripple. As the bulk capacitors sink and source the inductor AC
ripple current, a voltage develops across the bulk-capacitor ESR
equal to I
(ESR).
C(P-P)
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ISL68200
TABLE 12. DESIGN AND LAYOUT CHECKLIST
NOISE
0.6
0.4
0.2
0
PIN
NAME
SENSITIVITY
DESCRIPTION
EN
Yes
There is an internal 1µs filter. Decoupling the
capacitor is NOT needed, but if needed, use a
low time constant one to avoid too large a
shutdown delay.
I
= 0.75 I
O
L(P-P)
I
= 0
L(P-P)
L(P-P)
I
= 0.5 I
O
VIN
7VLDO
VCC
Yes
Yes
Yes
Yes
Place 16V+ X7R 1µF in close proximity to VIN
pin and the system ground plane.
Place 10V+ X7R 1µF in close proximity to
7VLDO pin and the system ground plane.
Place X7R 1µF in close proximity to VCC pin
and the system ground plane.
0
0.2
0.4
0.6
/V
OUT IN
0.8
1.0
DUTY CYCLE (V
)
SCL, SDA
50kHz to 1.25MHz signal when the SMBus,
2
PMBus, or I C is sending commands. Pairing
FIGURE 31. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
up with SALERT and routing carefully back to
2
SMBus, PMBus or I C master. 20 mils spacing
within SDA, SALERT, and SCL; and more than
30 mils to all other signals. Refer to the
SMBus, PMBus or I C design guidelines and
place proper terminated (pull-up) resistance
for impedance matching. Tie them to GND
when not used.
Design and Layout Considerations
To ensure a first pass design, the schematics design must be
done right and the board must be carefully laid out.
2
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between power layers and
the signal layers to provide shielding, often the layer below the
top and the layer above the bottom should be the ground layers.
SALERT
PGOOD
No
Open drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
No
Open-drain pin. Tie it to ground when not used.
RGND,
VSEN
Yes
Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE and BOOT.
CSRTN
Yes
Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ωand 3.5kΩ. Decoupling
(~0.1µF/X7R) on the output end (not the pin)
is optional and might be required for long
sense trace and a poor layout (see Figures 9
and 10 on page 16).
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. Input high frequency capacitors should be
placed close to the drain of the upper MOSFETs and the source of
the lower MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High frequency
output decoupling capacitors (ceramic) should be placed as
close as possible to the decoupling target, making use of the
shortest connection paths to any internal planes. Place the
components in such a way that the area under the IC has less
noise traces with high dV/dt and di/dt, such as gate signals,
phase node signals and VIN plane.
CSEN
Yes
Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/R
matching network in close
SEN
proximity to CSEN and CSRTN pins.
Differentially routing back to the controller
with at least 20 mils spacing from other
traces. Should NOT cross or go above/under
the switching nodes [BOOT, PHASE, UGATE,
LGATE] and power planes (VIN, PHASE, VOUT)
even though they are not in the same layer.
Tables 12 and 13 provide design and layout checklists that
designer must pay attention to.
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ISL68200
TABLE 12. DESIGN AND LAYOUT CHECKLIST (Continued)
NOISE
TABLE 13. TOP LAYOUT TIPS
DESCRIPTION
PIN
#
1
NAME
SENSITIVITY
DESCRIPTION
The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least 4
vias.
NTC
Yes
Place NTC 10k (Murata, NCP15XH103J03RC,
= 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET side
(see Figure 19); the return trace should be 20
mils away from other traces. Place 1.54kΩ
pull-up and decoupling capacitor (typically
0.1µF) in close proximity to the controller. The
pull-up resistor should be exactly tied to the
same point as VCC pin, not through an RC filter.
If not used, connect this pin to VCC.
2
Never place controller and its external components above or
under VIN plane or any switching nodes.
3
4
Never share CSRTN and VSEN on the same trace.
Place the input rail decoupling ceramic capacitors close to
the high-side FET on the same layer as possible. Never use
only one via and a trace to connect the input rail decoupling
ceramics capacitors; must connect to VIN and GND planes.
IOUT
Yes
Scale R such that IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
5
6
Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
function for the digital I . An external pull-up
OUT
resistor to VCC is recommended cancel I
OUT
Calibration” on
Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
below or above switching noise plane.
offset at 0A load. See “I
page 19
OUT
PROG1-4
GND
No
Resistor divider must be referenced to VCC pin
and the system ground; they can be placed
anywhere. DO NOT use decoupling capacitors
on these pins.
7
Always double check critical component pinout and their
respective footprints.
Voltage Regulator Design Materials
Yes
Directly connect to low noise area of the
system ground. The GND PAD should use at
least 4 vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
To support VR design and layout, Intersil also developed a set of
tools and evaluation boards, as listed in Tables 14 and 15,
respectively. Contact Intersil’s local office or field support at
www.intersil.com/ask for the latest available information.
LGATE
UGATE
No
No
Low-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
TABLE 14. AVAILABLE DESIGN ASSISTANCE MATERIALS
ITEM
1
DESCRIPTION
2
SMBus/PMBus/I C communication tool with
PowerNavigator GUI
High-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
2
Evaluation board schematics in OrCAD format and
layout in allegro format. See Table 15 for details.
BOOT,
PHASE
Yes
Yes
Place X7R 0.1µF or 0.22µF in proximity to
BOOT and PHASE pins. High dV/dt signals
should not be close to any sensitive signals.
TABLE 15. AVAILABLE DEMO BOARDS
DEMO BOARD
DESCRIPTION
2
ISL68200DEMO1Z
17x17mm 1-phase, 20A solution,
400kHz, with Dual FET
PVCC
Place X7R 4.7µF in proximity to PVCC pin and
the system ground plane.
2
ISL68201_99140DEMO1Z 17x17mm 1-phase, 35A solution,
400kHz, with ISL99140
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Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8705.1
FN8705.0
CHANGE
Removed unreleased parts from Tables 1 and 15
Initial Release
March 7, 2016
March 2, 2016
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL68200
Package Outline Drawing
L24.4x4C
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 50 ± 0 . 15
13
(4X)
0.15
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 50 )
( 20X 0 . 5 )
5
0 . 2 REF
C
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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ISL68201IRZ-T
Single-Phase R4 Digital Hybrid PWM Controller with PMBus/SMBus/I2C and PFM; QFN24; Temp Range: -40° to 85°C
RENESAS
ISL68201IRZ-T7A
Single-Phase R4 Digital Hybrid PWM Controller with PMBus/SMBus/I2C and PFM; QFN24; Temp Range: -40° to 85°C
RENESAS
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