ISL89165FRTAZ_技术文档

High Speed, Dual Channel, 6A, Power MOSFET

Driver with Enable Inputs

ISL89163, ISL89164, ISL89165 Features

• Dual output, 6A peak current (sink and source)

• Dual AND-ed input logic, (INput and ENable)

• Typical ON-resistance <1Ω

The ISL89163, ISL89164, and ISL89165 are high-speed,

6A, dual channel MOSFET drivers with enable inputs.

These parts are identical to the ISL89160, ISL89161,

ISL89162 drivers but with an added enable input for

each channel occupying NC pins 1 and 8 of the

ISL89160, ISL89161, ISL89162.

• Specified Miller plateau drive currents

• Very low thermal impedance (θ = 3°C/W)

JC

• Input logic levels for 3.3V CMOS, 5V CMOS, TTL and

Precision thresholds on all logic inputs allow the use of

external RC circuits to generate accurate and stable time

delays on both the main channel inputs, INA and INB,

and the enable inputs, ENA and ENB. The precision

delays capable of these precise logic threshold makes

these parts very useful for dead time control and

synchronous rectifiers. Note that the ENable and INput

logic inputs can be interchanged for alternate logic

implementations.

Logic levels proportional to V

DD

• Hysteretic logic inputs for high noise immunity

• Precision threshold inputs for time delays with

external RC components

• ~ 20ns rise and fall time driving a 10nF load.

• Low operating bias currents

Applications

Three input logic thresholds are available: 3.3V (CMOS),

5.0V (CMOS or TTL compatible), and CMOS thresholds

that are proportional to VDD.

• Synchronous Rectifier (SR) Driver

• Switch mode power supplies

• Motor Drives, Class D amplifiers, UPS, Inverters

• Pulse Transformer driver

At high switching frequencies, these MOSFET drivers

use very little internal bias currents. Separate,

non-overlapping drive circuits are used to drive each

CMOS output FET to prevent shoot-thru currents in the

output stage.

• Clock/Line driver

Related Literature

• AN1602 “ISL8916xA, ISL8916xB, ISL8916xC,

Evaluation Board User’s Guide”

The under voltage lockout (UV) insures that driver

outputs remain off (low) during turn-on until VDD is

sufficiently high for correct logic control. This prevents

unexpected glitches when VDD is being turn-on or

turn-off.

• AN1603 “ISL6752_54 Evaluation Board Application

Note”

Typical Application

Temp Stable Logic Thresholds

3.0

POSITIVE THRESHOLD LIMITS

2.5

2.0

V_DD

ENB

ENA

1

2

3

4

8

7

6

5

INA

GND

INB

OUTA

1.5

NEGATIVE THRESHOLD LIMITS

EPAD

1.0

0.5

0.0

OUTB

4.7µF

-40 -25 -10

5

20 35 50 65 80 95 110125

TEMPERATURE (°C)

October 12, 2010

FN7707.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL89163, ISL89164, ISL89165

Block Diagram

VDD

FOR OPTIONS A AND B,

SEPARATE FET DRIVES, WITH NON-

FOR CLARITY, ONLY

ONE CHANNEL IS

SHOWN

THE UV COMPARATOR

HOLDS OFF THE OUTPUTS

UNTIL VDD ~> 3.3VDC.

FOR OPTION C, THE UV

RELEASE IS ~> 6.5V

OVERLAPPING OUTPUTS, PREVENT

SHOOT-THRU CURRENTS IN THE

OUTPUT CMOS FETS RESULTING

WITH VERY LOW HIGH FREQUENCY

OPERATING CURRENTS.

ENx

ISL89163

ENX AND INX INPUTS

ARE IDENTICAL AND

MAY BE INTERCHANGED

FOR ALTERNATE LOGIC

OUTx

INx

10k

ISL89164, ISL89165

GND

EPAD

FOR PROPER THERMAL AND

ELECTRICAL PERFORMANCE, THE

EPAD MUST BE CONNECTED TO

THE PCB GROUND PLANE.

Pin Configurations

Pin Descriptions

ISL89163FR, ISL89163FB

(8 LD TDFN, EPSOIC)

TOP VIEW

ISL89164FR, ISL89164FB

(8 LD TDFN, EPSOIC)

TOP VIEW

DESCRIPTION

(See Truth Table for

Logic Polarities)

NUMBER SYMBOL

1

2

3

4

5

ENA

INA

Channel A enable, 0V to VDD

Channel A input, 0V to VDD

Power Ground, 0V

1

8

1

2

8

7

6

5

ENA

ENB

ENA

INA

ENB

INA 2

7 OUTA

6 VDD

/OUTA

VDD

GND

INB

3

GND 3

INB

GND

Channel B enable, 0V to VDD

Channel B output

/OUTB

INB 4

OUTB

4

5

OUTB,

/OUTB

ISL89165FR, ISL89165FB

(8 LD TDFN, EPSOIC)

TOP VIEW

6

7

VDD

Power input, 4.5V to 16V

OUTA,

/OUTA

Channel A output, 0V to VDD

1

8

ENA

ENB

8

ENB

Channel B enable, 0V to VDD

Power Ground, 0V

INA 2

7 /OUTA

EPAD

3

GND

VDD

6

5

INB 4

/OUTB

ENx

INx

ENx

OUTx

INx

NON-INVERTING

INVERTING

ENx* INx* OUTx*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

*SUBSTITUTE A OR B FOR x

FN7707.0

October 12, 2010

2

ISL89163, ISL89164, ISL89165

Ordering Information

PART NUMBER

PART

TEMP RANGE

(°C)

INPUT

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 2, 3, 4)

MARKING

CONFIGURATION INPUT LOGIC

ISL89163FRTAZ

ISL89163FRTBZ

ISL89163FRTCZ

ISL89164FRTAZ

ISL89164FRTBZ

ISL89164FRTCZ

ISL89165FRTAZ

ISL89165FRTBZ

ISL89165FRTCZ

ISL89163FBEAZ

ISL89163FBEBZ

ISL89163FBECZ

ISL89164FBEAZ

ISL89164FBEBZ

ISL89164FBECZ

ISL89165FBEAZ

ISL89165FBEBZ

ISL89165FBECZ

NOTES:

163A

-40 to +125

non-inverting

3.3V

5.0V

VDD

3.3V

5.0V

VDD

3.3V

5.0V

VDD

3.3V

5.0V

VDD

3.3V

5.0V

VDD

3.3V

5.0V

VDD

8 Ld 3x3 TDFN L8.3x3I

163B

163C

164A

inverting

164B

164C

165A

inverting + non-

inverting

165B

165C

89163 FBEAZ

89163 FBEBZ

89163 FBECZ

89164 FBEAZ

89164 FBEBZ

89164 FBECZ

89165 FBEAZ

89165 FBEBZ

89165 FBECZ

non-inverting

inverting

8 Ld EPSOIC

M8.15D

inverting + non-

inverting

1. Add “-T”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. Input Logic Voltage: A = 3.3V, B = 5.0V, C = VDD.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL89163, ISL89164, ISL89165. For more

information on MSL, please see Technical Brief TB363.

FN7707.0

October 12, 2010

3

ISL89163, ISL89164, ISL89165

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

DD

Logic Inputs (INA, INB, ENA, ENB) GND - 0.3v to V

Outputs (OUTA, OUTB). . . . . . . . . GND - 0.3v to V

Relative to GND . . . . . . . . -0.3V to 18V

Thermal Resistance (Typical)

θ

(°C/W) θ (°C/W)

JC

JA

+ 0.3V

DD

8 Ld TDFN Package (Notes 5, 6). . .

8 Ld EPSOIC Package (Notes 5, 6) .

44

42

3

Average Output Current (Note 7) . . . . . . . . . . . . . . . 150mA

Max Power Dissipation at +25°C in Free Air . . . . . . . . .2.27W

Max Power Dissipation at +25°C with Copper Plane . . .33.3W

Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C

Operating Junction Temp Range . . . . . . . . . -40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

ESD Ratings

Human Body Model Class 2 (Tested per JESD22-A114E) 2000V

Machine Model Class B (Tested per JESD22-A115-A) . . . 200V

Charged Device Model Class IV . . . . . . . . . . . . . . . . . 1000V

Latch-Up

Maximum Recommended Operating

Conditions

(Tested per JESD-78B; Class 2, Level A)

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

Junction Temperature. . . . . . . . . . . . . . . . . -40°C to +125°C

Options A and B

Supply Voltage, V

Relative to GND . . . . . . . . 4.5V to 16V

DD

Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . 0V to VDD

Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . 0V to VDD

Option C

Supply Voltage, V

Relative to GND . . . . . . . . 7.5V to 16V

DD

Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . 0V to VDD

Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . 0V to VDD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

JA

features. See Tech Brief TB379 for details.

6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

7. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output

current. The peak output currents of this driver are self limiting by transconductance or r

and do not required any

DS(ON)

external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output

current must be limited by external means to less than the specified absolute maximum.

DC Electrical Specifications

V

= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.

DD

Boldface limits apply over the operating junction temperature range,

-40°C to +125°C.

T = +25°C

T = -40°C to +125°C

J

MIN

MIN TYP MAX (Note 8)

MAX

(Note 8) UNITS

PARAMETERS

POWER SUPPLY

SYMBOL

TEST CONDITIONS

Voltage Range (Option A

and B)

V

-

4.5

16

V

DD

Voltage Range (Option C)

-

5

-

7.5

16

-

V

ENx = INx = GND

-

mA

V

Quiescent Current

I

DD

INA = INB = 1MHz, square wave

25

-

UNDERVOLTAGE

VDD Undervoltage

Lock-out (Option A or B)

(Note 12)

-

3.3

6.5

-

V

UV

ENA = ENB = True

INA = INB = True (Note 9)

VDD Undervoltage

Lock-out (Option C)

Hysteresis (Option A or B)

Hysteresis (Option C)

-

~25

-

mV

V

~0.95

FN7707.0

October 12, 2010

4

ISL89163, ISL89164, ISL89165

DC Electrical Specifications

V

= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.

DD

Boldface limits apply over the operating junction temperature range,

-40°C to +125°C. (Continued)

T = +25°C

T = -40°C to +125°C

J

MIN

MIN TYP MAX (Note 8)

MAX

(Note 8) UNITS

PARAMETERS

INPUTS

SYMBOL

TEST CONDITIONS

Input Range for INA, INB

V

Option A, B, or C

-

GND

1.12

1.70

V

IN

DD

Option A, nominally 37% x 3.3V

Option B, nominally 37% x 5.0V

1.22

1.85

1.32

2.00

Logic 0 Threshold

for INA, INB, ENA, ENB

(Note 11)

V

IL

Option C, nominally 20% x 12V

(Note 9)

-

2.4

-

2.00

2.76

V

Option A, nominally 63% x 3.3V

Option B, nominally 63% x 5.0V

-

2.08

3.15

-

1.98

3.00

2.18

3.30

V

Logic 1 Threshold

for INA, INB, ENA, ENB

(Note 11)

V

C

IH

Option C, nominally 80% x12V

(Note 9)

-

9.6

2

-

9.24

-

9.96

-

V

Input Capacitance of INA,

INB, ENA, ENB (Note 10)

pF

µA

IN

Input Bias Current

for INA, INB, ENA, ENB

I

GND<V <V

IN

-

-10

+10

IN

DD

OUTPUTS

V

OHA

OHB

High Level Output Voltage

-

V

- 0.1

V

DD

V

OLA

OLB

Low Level Output Voltage

GND

GND + 0.1

Peak Output Source

Current

I

V

(initial) = 0V, C

LOAD

= 10nF

-

-6

-

A

O

Peak Output Sink Current

NOTES:

I

(initial) =12V, C

LOAD

+6

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

9. The nominal 20% and 80% thresholds for option C are valid for any value of VDD.

10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated

by the PCB parasitic capacitance.

11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input

voltage for the inverted inputs is less than the logic 0 threshold voltage.

12. A 200µs delay further inhibits the release of the output state when the UV positive going threshold is crossed.

FN7707.0

October 12, 2010

5

ISL89163, ISL89164, ISL89165

AC Electrical Specifications

V

= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface

DD

limits apply over the operating junction temperature range,

-40°C to +125°C.

TEST

T = +25°C

J

T = -40°C to +125°C

J

CONDITIONS

/NOTES

PARAMETERS

SYMBOL

MIN TYP MAX

MIN

MAX

40

UNITS

Output Rise Time (see Figure 2)

t

C

= 10 nF,

-

20

25

-

ns

R

LOAD

10% to 90%

Output Fall Time (see Figure 2)

t

C

= 10 nF,

LOAD

-

40

50

ns

F

90% to 10%

Output Rising Edge Propagation Delay for

Non-Inverting Inputs (see Figure 1)

t

No load

RDLYn

Output Rising Edge Propagation Delay with

Inverting Inputs (see Figure 1)

t

No load

RDLYi

FDLYn

Output Falling Edge Propagation Delay with

Non-Inverting Inputs (see Figure 1)

Output Falling Edge Propagation Delay with

Inverting Inputs (see Figure 1)

t

FDLYi

Rising Propagation Matching (see Figure 1)

Falling Propagation Matching (see Figure 1)

t

-

<1ns

6

-

ns

A

RM

t

FM

Miller Plateau Sink Current

(See Test Circuit Figure 3)

-I

V

= 10V,

MP

DD

MILLER

= 5V

= 3V

= 2V

= 5V

= 3V

= 2V

V

= 10V,

-

4.7

3.7

5.2

5.8

6.9

-

A

DD

MILLER

V

= 10V,

DD

MILLER

Miller Plateau Source Current

(See Test Circuit Figure 4)

I

V

= 10V,

DD

MILLER

V

= 10V,

DD

MILLER

V

= 10V,

DD

MILLER

FN7707.0

October 12, 2010

6

ISL89163, ISL89164, ISL89165

Test Waveforms and Circuits

3.3V*

0V

50%

t_RDLY

50%

t_FDLY

INA,

INB

90%

10%

/OUTA

OUTA

t_RDLY

t_FDLY

OUTA

OR

OUTB

/OUTB

OUTB

t_R

t_F

t_RM

t_FM

* LOGIC LEVELS: A OPTION = 3.3V, B OPTION = 5.0V,

C OPTION = VDD

FIGURE 1. PROP DELAYS AND MATCHING

FIGURE 2. RISE/FALL TIMES

10V

ISL8916x

200ns

0.1µF

10k

0.1µF

10k

V_MILLER

10µF

200ns

10nF

+I_SENSE

10nF

50m

-I_SENSE

FIGURE 3. MILLER PLATEAU SINK CURRENT TEST

CIRCUIT

FIGURE 4. MILLER PLATEAU SOURCE CURRENT TEST

CIRCUIT

CURRENT THROUGH

I_MP

10V

0A

0.1Ω RESISTOR

V_MILLER

V_OUT

V_MILLER

CURRENT THROUGH

-I_MP

0V

0.1

Ω

RESISTOR

0

200ns

FIGURE 5. MILLER PLATEAU SINK CURRENT

FIGURE 6. MILLER PLATEAU SOURCE CURRENT

FN7707.0

October 12, 2010

7

ISL89163, ISL89164, ISL89165

Typical Performance Curves

3.5

3.0

2.5

2.0

35

30

25

20

15

10

5

+125°C

+25°C

-40°C

+25°C

-40°C

4

8

12

16

4

8

12

16

V

DD

FIGURE 8. I

vs V

(1 MHz)

DD

FIGURE 7. I

vs V

(STATIC)

DD

50

40

30

20

10

0

1.1

1.0

16V

V

LOW

OUT

NO LOAD

0.9

0.8

0.7

10V

5V

V

HIGH

OUT

12V

0.6

0.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

FREQUENCY (MHz)

-45

-20

5

30

55

80

105

130

TEMPERATURE (°C)

FIGURE 9. I

vs FREQUENCY (+25°C)

FIGURE 10. r vs TEMPERATURE

DS(ON)

DD

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

POSITIVE THRESHOLD

NEGATIVE THRESHOLD

POSITIVE THRESHOLD

NEGATIVE THRESHOLD

-45

-20

5

30

55

80

105

130

-45

-20

5

30

55

80

105

130

TEMPERATURE (°C)

FIGURE 11. OPTION A THRESHOLDS

FIGURE 12. OPTION B THRESHOLDS

FN7707.0

October 12, 2010

8

ISL89163, ISL89164, ISL89165

Typical Performance Curves(Continued)

25

20

15

30

FALL TIME, C

= 10nF

LOAD

OUTPUT FALLING PROP DELAY

OUTPUT RISING PROP DELAY

25

RISE TIME, C

= 10nF

LOAD

20

15

-45

-20

5

30

55

80

105

130

5

7

9

11

DD

13

15

V

TEMPERATURE (°C)

FIGURE 13. OUTPUT RISE/FALL TIME

FIGURE 14. PROPAGATION DELAY vs V

DD

ISL89164, ISL89165 driver from turning on. The A and B

input threshold options force the driver outputs to be low

when VDD < ~3.2 VDC regardless of the input logic

Functional Description

Overview

The ISL89163, ISL89164, ISL89165 MOSFET drivers

incorporate several features optimized for Synchronous

Rectifier (SR) driver applications including precision input

logic thresholds, enable inputs, undervoltage lock-out,

and high output drive currents.

states. The C option shuts down when V

< ~ 6.5 VDC.

DD

Application Information

Precision Thresholds for Time Delays

Three input logic voltage levels are supported by the

ISL89163, ISL89164, ISL89165. Option A is used for

3.3V logic, Option B is used for 5.0V logic, and Option C

is used for higher voltage logic when it is desired to have

The precision input thresholds facilitate the use of an

external RC network to delay the rising or falling

propagation of the driver output. This is a useful feature

for adjusting when the SRs turn-on relative to the

primary side FETs. In a similar manner, these drivers can

also be used to control the turn-on/off timing of the

primary FETs.

voltage thresholds that are proportional to V . The A

DD

and B options have nominal thresholds that are 37% and

63% of 3.3V and 5.0V respectively and the C option is

20% and 80% of VDD.

The Enable inputs (ENA, ENB) are used to emulate diode

operation of the SRs by disabling the driver output when

it is necessary to prevent negative currents in the SRs.

An example is turning off the SRs when the power supply

output is turned off. This prevents the output capacitor

from being discharged through the output inductor. If

this is allowed to happen, the voltage across the output

capacitor will ring negative possibly damaging the

capacitor (if it is polarized) and probably damaging the

load. Another example is preventing circulating currents

between paralleled power supplies during no or light load

conditions. During light load conditions (expecially when

active load sharing is not active), energy will be

ENx

D

INx

c_del

OUTx

R_del

FIGURE 15. DELAY USING RCD NETWORK

In Figure 15, R

del

and C delay the rising edge of the

del

input signal. For the falling edge of the input signal, the

Diode shorts out the resistor resulting in a minimal falling

edge delay.

transfered from the paralled power supply that has a

higher voltage to the paralleled power supply with the

lower voltage. Consequently, the energy that is absorbed

by the low voltage output is then transfered to the

primary side causing the bus voltage to increase until the

primary side is damaged by excessive voltage.

The 37% and 63% thresholds of options A and B were

chosen to simplify the calculations for the desired time

delays. When using an RC circuit to generate a time

delay, the delay is simply T (secs) = R (ohms) x C

(farads). Please note that this equation only applies if the

input logic voltage is matched to the 3.3V or 5V threshold

options. If the logic high amplitude is not equal to 3.3V or

5V, then the equations in Equation 1 can be used for

more precise delay calculations.

To prevent unexpected glitches on the output of the

ISL89163, ISL89164, ISL89165 during power-on or

power-off when V

lock-out prevents the outputs of the ISL89163,

is very low, the Undervoltage (UV)

DD

FN7707.0

October 12, 2010

9

ISL89163, ISL89164, ISL89165

High level of the logic signal into the RC

12

10

8

V

= 10V

H

Positive going threshold for 5V logic (B option)

Low level of the logic signal into the RC

= 63% × 5V

thres

V

= 64V

= .3V

DS

L

Timing values

R

= 100Ω

= 1nF

V

= 40V

del

DS

C

t

del

6

V

− V

thres

⎛

⎞

⎟

⎠

L

= −R

C

× ln

+ 1

⎜

⎝

del

del del

V

− V

L

H

4

nominal delay time for this example

t

= 34.788 ns

del

2

(EQ. 1)

In this example, the high logic voltage is 10V, the

0

positive threshold is 63% of 5V and the low level logic is

0.3V. Note the the rising edge propagation delay of the

driver must be added to this value.

0

2

4

6

8

10 12 14 16 18 20 22 24

GATE CHARGE (nC)

Q

g,

FIGURE 16. MOSFET GATE CHARGE vs GATE VOLTAGE

The minimum recommended value of C is 100pF. The

parasitic capacitance of the PCB and any attached scope

probes will introduce significant delay errors if smaller

values are used. Larger values of C will further minimize

errors.

Figure 16 illustrates how the gate charge varies with

the gate voltage in a typical power MOSFET. In this

example, the total gate charge for V = 10V is 21.5nC

gs

when V

DS

= 40V. This is the charge that a driver must

source to turn-on the MOSFET and must sink to

turn-off the MOSFET.

Acceptable values of R are primarily effected by the

source resistance of the logic inputs. Generally, 100Ω

resistors or larger are usable.

Equation 2 shows calculating the power dissipation of

the driver:

R

Power Dissipation of the Driver

gate

--------------------------------------------

P

= 2 • Q • freq • V

•

+ I (freq) • V

D

c

GS

DD

R

+ r

DS(ON)

gate

The power dissipation of the ISL89163, ISL89164,

ISL89165 is dominated by the losses associated with the

gate charge of the driven bridge FETs and the switching

frequency. The internal bias current also contributes to

the total dissipation but is usually not significant as

compared to the gate charge losses.

(EQ. 2)

where:

freq = Switching frequency,

= V bias of the ISL89163, ISL89164, ISL89165

V

GS

DD

Q = Gate charge for V

GS

c

I

(freq) = Bias current at the switching frequency

DD

(see Figure 7)

r

= ON-resistance of the driver

DS(ON)

R

= External gate resistance (if any).

gate

Note that the gate power dissipation is proportionally

shared with the external gate resistor. Do not overlook

the power dissipated by the external gate resistor.

FN7707.0

October 12, 2010

10

ISL89163, ISL89164, ISL89165

Typical Application Circuits

Primary to Secondary

side self biasing,

Isolated SR drive

L

R

L

PWM

/OUTLLN

/OUTLRN

VBIAS

R27

V2

ENABLE

D9

OUTLLN

V1

LRN

Q100

C123

V1

U4

R28

V4

R-SR

LSR

V2

LLN

V3

EL7212

ISL89163

U4

OUTLRN

Q101

T6

V3

LLN

C9 C10

Red dashed lines point out

the turn-on delay of the

SRs when PWM goes low

V4

LRN

This drive circuit provides Primary to Secondary line

isolation. A controller, on the primary side, is the source

of the SR control signals OUTLLN and OUTLRN signals.

The secondary side signals, V1 and V2 are rectified by

the dual diode, D9, to generate the secondary side bias

for U4. V1 and V3 are also inverted by Q100 and Q101

and the rising edges are delayed by R27/C10 and

R28/C9 respectively to generate the SR drive signals,

LRN and LLN. For more complete information on this SR

drive circuit, and other applications for the

• Be aware of magnetic fields emanating from

transformers and inductors. Gaps in these structures

are especially bad for emitting flux.

• If you must have traces close to magnetic devices,

align the traces so that they are parallel to the flux

lines to minimize coupling.

• The use of low inductance components such as chip

resistors and chip capacitors is highly recommended.

• Use decoupling capacitors to reduce the influence of

parasitic inductance in the VDD and GND leads. To be

effective, these caps must also have the shortest possible

conduction paths. If vias are used, connect several

paralleled vias to reduce the inductance of the vias.

ISL89163/4/5, refer to AN1603 “ISL6752_54 Evaluation

Board Application Note”.

General PCB Layout Guidelines

The AC performance of the ISL89163, ISL89164,

ISL89165 depends significantly on the design of the PC

board. The following layout design guidelines are

recommended to achieve optimum performance:

• It may be necessary to add resistance to dampen

resonating parasitic circuits especially on OUTA and

OUTB. If an external gate resistor is unacceptable,

then the layout must be improved to minimize lead

inductance.

• Place the driver as close as possible to the driven

power FET.

• Keep high dv/dt nodes away from low level circuits.

Guard banding can be used to shunt away dv/dt

injected currents from sensitive circuits. This is

especially true for control circuits that source the

input signals to the ISL89163, ISL89164, ISL89165.

• Understand where the switching power currents flow.

The high amplitude di/dt currents of the driven

power FET will induce significant voltage transients

on the associated traces.

• Keep power loops as short as possible by paralleling

the source and return traces.

• Avoid having a signal ground plane under a high

amplitude dv/dt circuit. This will inject di/dt currents

into the signal ground paths.

• Use planes where practical; they are usually more

effective than parallel traces.

• Do power dissipation and voltage drop calculations of

the power traces. Many PCB/CAD programs have

built in tools for calculation of trace resistance.

• Avoid paralleling high amplitude di/dt traces with low

level signal lines. High di/dt will induce currents and

consequently, noise voltages in the low level signal lines.

• Large power components (Power FETs, Electrolytic

caps, power resistors, etc.) will have internal

parasitic inductance which cannot be eliminated.

This must be accounted for in the PCB layout and

circuit design.

• When practical, minimize impedances in low level

signal circuits. The noise, magnetically induced on a

10k resistor, is 10x larger than the noise on a 1k

resistor.

• If you simulate your circuits, consider including

parasitic components especially parasitic inductance.

FN7707.0

October 12, 2010

11

ISL89163, ISL89164, ISL89165

General EPAD Heatsinking

Considerations

EPAD GND

PLANE

EPAD GND

PLANE

The thermal pad is electrically connected to the GND

supply through the IC substrate. The epad of the

ISL89163, ISL89164, ISL89165 has two main functions:

to provide a quiet Gnd for the input threshold

comparators and to provide heat sinking for the IC. The

EPAD must be connected to a ground plane and no

switching currents from the driven FET should pass

through the ground plane under the IC.

BOTTOM

LAYER

COMPONENT

LAYER

Figure 17 is a PCB layout example of how to use vias to

remove heat from the IC through the EPAD.

FIGURE 17. TYPICAL PCB PATTERN FOR THERMAL VIAS

For maximum heatsinking, it is recommended that a

ground plane, connected to the EPAD, be added to both

sides of the PCB. A via array, within the area of the EPAD,

will conduct heat from the EPAD to the gnd plane on the

bottom layer. The number of vias and the size of the gnd

planes required for adequate heatsinking is determined

by the power dissipated by the ISL89163, ISL89164,

ISL89165, the air flow and the maximum temperature of

the air around the IC.

FN7707.0

October 12, 2010

12

ISL89163, ISL89164, ISL89165

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

10/12/10

FN7707.0

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

handheld products, and notebooks. Intersil's product families address power management and analog signal

processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL89163, ISL89164, ISL89165

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/sear

FN7707.0

October 12, 2010

13

ISL89163, ISL89164, ISL89165

Package Outline Drawing

L8.3x3I

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1 6/09

2X 1.950

3.00

A

6X 0.65

B

5

8

(4X)

0.15

1.64 +0.10/ - 0.15

6

PIN 1

INDEX AREA

6

PIN #1 INDEX AREA

4

1

4

8X 0.30

0.10 M C A B

8X 0.400 ± 0.10

TOP VIEW

2.38

+0.10/ - 0.15

BOTTOM VIEW

SEE DETAIL "X"

( 2.38 )

( 1.95)

C

0.10

C

Max 0.80

0.08

C

SIDE VIEW

( 8X 0.60)

(1.64)

( 2.80 )

PIN 1

5

C

0 . 2 REF

(6x 0.65)

0 . 00 MIN.

0 . 05 MAX.

( 8 X 0.30)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN7707.0

October 12, 2010

14

ISL89163, ISL89164, ISL89165

Small Outline Exposed Pad Plastic Packages (EPSOIC)

M8.15D

N

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.52

0.10

0.36

0.19

4.80

3.811

MAX

1.72

0.25

0.46

0.25

4.98

3.99

NOTES

A

A1

B

C

D

E

e

0.059

0.003

0.0138

0.0075

0.189

0.150

0.067

0.009

0.0192

0.0098

0.196

0.157

-

1

2

3

-

TOP VIEW

9

-

L

3

SEATING PLANE

A

4

-A-

D

0.050 BSC

1.27 BSC

-

h x 45°

H

h

0.230

0.010

0.016

0.244

0.019

0.050

5.84

0.25

0.41

6.20

0.50

1.27

-

-C-

5

α

L

6

e

B

A1

C

N

8

7

0.10(0.004)

0°

8°

0°

8°

-

11

α

P

0.25(0.010) M

SIDE VIEW

C A M B S

0.118

0.078

0.137

0.099

3.00

2.00

3.50

2.50

P1

11

Rev. 0 5/07

NOTES:

1

2

3

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

P1

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

N

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

P

BOTTOM VIEW

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced

variations. Values shown are maximum size of exposed pad

within lead count and body size.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7707.0

October 12, 2010

15


型号：	ISL89165FRTAZ
厂家：	Intersil
描述：	High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs 高速，双通道， 6A ，具有使能输入功率MOSFET驱动器驱动器
文件：	总15页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL89165FRTAZ [INTERSIL]

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