ISL89165FRTBZ-T_技术文档

Datasheet

ISL89163, ISL89164, ISL89165

High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs

The ISL89163, ISL89164, and ISL89165 are

high-speed, 6A, dual channel MOSFET drivers with

Features

• Dual output, 6A peak currents, can be paralleled

• Dual AND-ed input logic, (input and enable)

• Typical ON-resistance <1Ω

enable inputs.

Precision thresholds on all logic inputs allow the use

of external RC circuits to generate accurate and

stable time delays on both the main channel inputs,

INA and INB, and the enable inputs, ENA and ENB.

The precision delays capable of these precise logic

thresholds make these parts valuable for dead time

control and synchronous rectifiers. Note, the enable

and input logic inputs can be interchanged for

alternate logic implementations.

• Specified Miller plateau drive currents

• Very low thermal impedance (θ = 3°C/W)

JC

• Hysteretic Input logic levels for 3.3V CMOS, 5V

CMOS, TTL, and Logic levels proportional to V

DD

• Precision threshold inputs for time delays with

external RC components

Three input logic thresholds are available:

• 3.3V (CMOS)

• 20ns rise and fall time driving a 10nF load.

Applications

• 5.0V (CMOS or TTL compatible)

• Synchronous Rectifier (SR) driver

• Switch mode power supplies

• CMOS thresholds that are proportional to V

DD

At high switching frequencies, these MOSFET drivers

use a minimal amount of internal bias currents.

Separate, non-overlapping drive circuits are used to

drive each CMOS output FET to prevent

• Motor drives, Class D amplifiers, UPS, inverters

• Pulse transformer driver

• Clock/line driver

shoot-through currents in the output stage.

Related Literature

The start-up sequence is designed to prevent

unexpected glitches when V is being turned on or

DD

For a full list of related documents, visit our website:

• ISL89163, ISL89164, ISL89165 device pages

turned off. When V < ~1V, an internal 10kΩ resistor

DD

between the output and ground helps to keep the

output voltage low. When ~1V < V < UV, both

DD

outputs are driven low with significantly low resistance

as the logic inputs are ignored, which ensures that the

driven FETs are off. When V > UVLO, and after a

DD

short delay, the outputs begin to respond to the logic

inputs.

3.0

Positive Threshold Limits

2.5

2.0

V

DD

ENB

ENA

1

2

3

4

8

1.5

INA

GND

INB

OUTA

Negative Threshold Limits

7

6

5

EPAD

1.0

0.5

0.0

OUTB

4.7µF

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

Figure 1. Typical Application

Figure 2. Temperature Stable Logic Thresholds

FN7707 Rev.6.00

Jul.9.19

Page 1 of 22

ISL89163, ISL89164, ISL89165

Contents

1.

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

1.2

1.3

1.4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

2.2

2.3

2.4

2.5

2.6

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Test Waveforms and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.

4.

5.

Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

5.2

5.3

5.4

Precision Thresholds for Time Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Paralleling Outputs to Double the Peak Drive Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power Dissipation of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.

7.

8.

9.

General PCB Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

General EPAD Heatsinking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

FN7707 Rev.6.00

Jul.9.19

Page 2 of 22

ISL89163, ISL89164, ISL89165

1. Overview

1.1

Block Diagram

VDD

For options A and B, the UV

comparator holds off the outputs

Separate FET drives, with non-overlapping

outputs, prevent shoot-thru currents in the

output CMOS FETs resulting with very low

high frequency operating currents.

For clarity, only one channel is shown

until V ~> 3.3V . For option C,

DD

DC

the UV release is ~> 6.5V

ENx

ISL89163

ENx and INx inputs are identical and

may be interchanged for alternate logic

OUTx

INx

10k

ISL89164, ISL89165

GND

EPAD

For proper thermal and electrical performance, the

EPAD must be connected to the PCB ground plane.

Figure 3. Block Diagram

1.2

Ordering Information

Part Number

(Notes 2, 3, 4)

Part

Marking

Temp

Input

Tape and Reel

Package

Pkg.

Range (°C)

-40 to +125

Configuration Logic (V) (Units) (Note 1) (RoHS Compliant) Dwg. #

ISL89163FRTAZ

ISL89163FRTAZ-T

ISL89163FRTBZ

ISL89163FRTBZ-T

ISL89164FRTAZ

ISL89164FRTAZ-T

ISL89164FRTBZ

ISL89164FRTBZ-T

ISL89165FRTAZ

ISL89165FRTAZ-T

ISL89165FRTBZ

ISL89165FRTBZ-T

ISL89163FBEAZ

ISL89163FBEAZ-T

ISL89163FBEBZ

ISL89163FBEBZ-T

ISL89164FBEAZ

ISL89164FBEAZ-T

ISL89164FBEBZ

ISL89164FBEBZ-T

163A

163B

164A

164B

165A

165B

Non-inverting

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

-

8 Ld 3x3 TDFN

8 Ld EPSOIC

L8.3x3I

M8.15D

6k

-

6k

Inverting

-

6k

-

6k

Inverting +

Non-inverting

-

6k

-

6k

-

89163 FBEAZ

89163 FBEBZ

89164 FBEAZ

89164 FBEBZ

Non-inverting

Inverting

2.5k

-

2.5k

-

2.5k

-

2.5k

FN7707 Rev.6.00

Jul.9.19

Page 3 of 22

ISL89163, ISL89164, ISL89165

1. Overview

Part Number

(Notes 2, 3, 4)

Part

Marking

Temp

Range (°C)

Input

Tape and Reel

Package

Pkg.

Configuration Logic (V) (Units) (Note 1) (RoHS Compliant) Dwg. #

ISL89165FBEAZ

89165 FBEAZ

-40 to +125

Inverting +

Non-inverting

3.3V

5.0V

-

8 Ld EPSOIC

M8.15D

ISL89165FBEAZ -T 89165 FBEAZ

2.5k

-

ISL89165FBEBZ

ISL89165FBEBZ-T

Notes:

89165 FBEBZ

2.5k

1. See TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J-STD-020.

3. Input Logic Voltage: A = 3.3V, B = 5.0V.

4. For Moisture Sensitivity Level (MSL), see the ISL89163, ISL89164, ISL89165 device pages. For more information about MSL, see TB363.

Table 1. Key Differences Between Family of Parts

I/O Pins

Part Number

ISL89163

ENA

NINV

ENB

NINV

INA

NINV

INV

INB

NINV

INV

OUTA

NINV

OUTB

NINV

ISL89164

ISL89165

INV

NINV

Note: INV: Inverting Input, NINV: Non-inverting input.

FN7707 Rev.6.00

Jul.9.19

Page 4 of 22

ISL89163, ISL89164, ISL89165

1. Overview

1.3

Pin Configurations

ISL89163FR, ISL89163FB

(8 Ld TDFN, EPSOIC)

Top View

ISL89164FR, ISL89164FB

(8 Ld TDFN, EPSOIC)

Top View

ENA

INA

1

2

3

4

8

7

6

5

ENB

ENA

/INA

GND

/INB

1

2

3

4

8

7

6

5

ENB

OUTA

VDD

OUTA

VDD

GND

INB

OUTB

ISL89165FR, ISL89165FB

(8 Ld TDFN, EPSOIC)

Top View

ENA

/INA

GND

INB

1

2

3

4

8

7

6

5

ENB

OUTA

VDD

OUTB

1.4

Pin Descriptions

Description

Pin Number

Symbol

ENA

(See Table 2)

1

2

3

4

5

6

7

8

Channel A enable, 0V to VDD

Channel A input, 0V to VDD

Power Ground, 0V

INA, /INA

GND

INB, /INB

OUTB

VDD

Channel B enable, 0V to VDD

Channel B output

Power input, 4.5V to 16V

Channel A output, 0V to VDD

Channel B enable, 0V to VDD

Power Ground, 0V

OUTA

ENB

EPAD

Table 2. Truth Table for Logic Polarities

ENx

INx

ENx

/INx

OUTx

Non-Inverting

Inverting

UV

ENx*

INx*

OUTx*

UV

ENx* /INx*

OUTx*

0

1

x

0

1

0

1

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

*Substitute A or B for x

FN7707 Rev.6.00

Jul.9.19

Page 5 of 22

ISL89163, ISL89164, ISL89165

2. Specifications

2.1

Absolute Maximum Ratings

Parameter

Minimum

-0.3

Maximum

18

Unit

V

Supply Voltage, VDD Relative to GND

Logic Inputs (INA, INB, ENA, ENB)

Outputs (OUTA, OUTB)

GND - 0.3

V_DD+ 0.3

150

V

Average Output Current (Note 5)

ESD Rating

mA

Unit

kV

V

Value

2

Human Body Model Class 2 (Tested per JESD22-A114E)

Machine Model Class B (Tested per JESD22-A115-A)

Charged Device Model Class IV

200

1

kV

mA

Latch-Up (Tested per JESD-78B; Class 2, Level A)

Output Current

500

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely

impact product reliability and result in failures not covered by warranty.

Note:

5. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The

peak output currents of this driver are self limiting by trans conductance or r_DS(ON)and do not required any external components to

minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external

means to less than the specified absolute maximum.

2.2

Thermal Information

Thermal Resistance (Typical)

θ

_JA(°C/W)

θ_JC(°C/W)

8 Ld TDFN Package (Notes 6, 7)

8 Ld EPSOIC Package (Notes 6, 7)

Notes:

44

42

3

6. θ_JAis measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features.

See TB379.

7. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Parameter

Minimum

Maximum

2.27

Unit

W

Max Power Dissipation at +25°C in Free Air

Max Power Dissipation at +25°C with Copper Plane

Storage Temperature Range

33.3

W

-65

-40

+150

°C

Maximum Operating Junction Temperature Range

Pb-Free Reflow Profile

+150

see TB493

FN7707 Rev.6.00

Jul.9.19

Page 6 of 22

ISL89163, ISL89164, ISL89165

2. Specifications

2.3

Recommended Operating Conditions

Parameter

Minimum

Maximum

Unit

Junction Temperature

-40

+125

°C

Options A and B

Supply Voltage, VDD Relative to GND

Logic Inputs (INA, INB, ENA, ENB)

Outputs (OUTA, OUTB)

4.5

0

16

V

V_DD

0

Option C

Supply Voltage, VDD Relative to GND

Logic Inputs (INA, INB, ENA, ENB)

Outputs (OUTA, OUTB)

7.5

0

16

V

V_DD

0

2.4

Electrical Specifications

2.4.1 DC Electrical Specifications

V_DD= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction

temperature range, -40°C to +125°C.

T_J= +25°C

T_J= -40°C to +125°C

Min Max

Min Typ Max (Note 8) (Note 8) Unit

Parameters

Power Supply

Symbol

Test Conditions

Voltage Range (Option A and B)

Voltage Range (Option C)

V_DDQuiescent Current

V_DD

I_DD

4.5

7.5

16

V

ENx = INx = GND

5

mA

INA = INB = 1MHz, square wave

25

Undervoltage

VDD Undervoltage Lockout (Options A

and B) (Note 12, Figure 10)

V_UV

ENA = ENB = True

INA = INB = True

3.3

6.5

V

VDD Undervoltage Lockout (Option C)

(Note 12, Figure 10)

ENA = ENB = True

INA = INB = True (Note 9)

Hysteresis (Option A or B)

Hysteresis (Option C)

Inputs

~25

mV

V

~0.95

Input Range for INA, INB, ENA, ENB

V_IN

V_IL

Option A, B, or C

GND

1.12

1.70

2.00

V_DD

1.32

2.00

2.76

V

Logic 0 Threshold for INA, INB, ENA,

ENB (Note 11)

Option A, nominally 37% x 3.3V

Option B, nominally 37% x 5.0V

1.22

1.85

2.4

Option C, nominally 20% x 12V

(Note 9)

Logic 1 Threshold for INA, INB, ENA,

ENB (Note 11)

V_IH

Option A, nominally 63% x 3.3V

Option B, nominally 63% x 5.0V

2.08

3.15

9.6

1.98

3.00

9.24

2.18

3.30

9.96

V

Option C, nominally 80% x 12V

(Note 9)

Input Capacitance of INA, INB, ENA,

ENB (Note 10)

C_IN

I_IN

2

pF

µA

Input Bias Current for INA, INB, ENA,

ENB

GND < V_IN< V_DD

-10

+10

V_DD

Outputs

High Level Output Voltage

V_OHA

V_OHB

V_DD- 0.1

V

FN7707 Rev.6.00

Jul.9.19

Page 7 of 22

ISL89163, ISL89164, ISL89165

2. Specifications

V_DD= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction

temperature range, -40°C to +125°C. (Continued)

T_J= +25°C

T_J= -40°C to +125°C

Min Max

Min Typ Max (Note 8) (Note 8) Unit

Parameters

Symbol

Test Conditions

Low Level Output Voltage

V_OLA

V_OLB

GND

GND + 0.1

V

Peak Output Source Current

Peak Output Sink Current

Notes:

I_O

V_O(initial) = 0V, C_LOAD= 10nF

V_O(initial) = 12V, C_LOAD= 10nF

-6

A

+6

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

9. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD.

10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input is dominated by the PCB

parasitic capacitance.

11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the

inverted inputs is less than the Logic 0 threshold voltage.

12. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 10 on page 10.

2.5

AC Electrical Specifications

V_DD= 12V, GND = 0V, No Load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction

temperature range, -40°C to +125°C.

T_J= +25°C

T_J= -40°C to +125°C

Parameters

Output Rise Time (see Figure 5)

Output Fall Time (see Figure 5)

Symbol

Test Conditions

Min Typ Max

Min

Max

40

50

Unit

ns

A

t_R

t_F

C_LOAD= 10nF, 10% to 90%

C_LOAD= 10nF, 90% to 10%

20

25

<1

Output Rising Edge Propagation Delay for

Non-Inverting Inputs (Note 13) (see Figure 4)

t_RDLYnV_DD= 12V Options A and B

V_DD= 8V Option C

Output Rising Edge Propagation Delay with

Inverting Inputs (Note 13) (see Figure 4)

t_RDLYiV_DD= 12V Options A and B

V_DD= 8V Option C

Output Falling Edge Propagation Delay with

Non-Inverting Inputs (Note 13) (see Figure 4)

t_FDLYnV_DD= 12V Options A and B

V_DD= 8V Option C

Output Falling Edge Propagation Delay with

Inverting Inputs (Note 13) (see Figure 4)

t_FDLYi

V_DD= 12V Options A and B

V_DD= 8V Option C

Rising Propagation Matching (see Figure 4)

Falling Propagation Matching (see Figure 4)

t_RM

t_FM

No load

Miller Plateau Sink Current

(See Test Circuit Figure 6)

-I_MP

I_MP

V_DD= 10V, V_MILLER= 5V

V_DD= 10V, V_MILLER= 3V

V_DD= 10V, V_MILLER= 2V

V_DD= 10V, V_MILLER= 5V

V_DD= 10V, V_MILLER= 3V

V_DD= 10V, V_MILLER= 2V

-

6

-

4.7

3.7

5.2

5.8

6.9

400

A

Miller Plateau Source Current

(See Test Circuit Figure 7)

A

Turn-On Delay (Note 12, Figure 10)

Note:

t_{on_delay}see Figure 10

µs

13. Propagation delays for Option C are typically the same for the recommended operating range (7.5V ≤ V_DD≤ 16V).

FN7707 Rev.6.00

Jul.9.19

Page 8 of 22

ISL89163, ISL89164, ISL89165

2. Specifications

2.6

Test Waveforms and Circuits

V

DD

80%

Option C

INA, INB,

ENA, ENB

20%

0V

3.3V Option A

5.0V Option B

50%

Option A or B

INA, INB,

ENA, ENB

0V

t_RDLY

t_FDLY

/OUTA

OUTA

90%

t_RDLY

t_FDLY

/OUTB

OUTB

OUTA

or

OUTB

10%

t_RM

t_FM

t_R

t_F

Logic Levels: Option A = 3.3V, Option B = 5.0V, Option C = V

DD

Figure 4. Prop Delays and Matching

Figure 5. Rise/Fall Times

10V

ISL8916x

0.1µF

10kΩ

0.1µF

10nF

10k

V_MILLER

10µF

200ns

10nF

+I_SENSE

50m

-I_SENSE

Figure 6. Miller Plateau Sink Current Test Circuit

Figure 7. Miller Plateau Source Current Test Circuit

10V

0A

Current through 0.1Ω

I_MP

Resistor

V_MILLER

V_OUT

V_MILLER

Current through 0.1

Resistor

Ω

-I_MP

0V

0

200ns

Figure 8. Miller Plateau Sink Current

Figure 9. Miller Plateau Source Current

FN7707 Rev.6.00

Jul.9.19

Page 9 of 22

ISL89163, ISL89164, ISL89165

2. Specifications

Rising V_DD

This duration is dependant on

rise time of VDD

UV Threshold

This duration is

independent on rise

time of V_DD

~1V

10kΩ to

ground

Outputs Active

Low

OUTA, OUTB

Output State

Outputs Controlled by Logical

Inputs

400µs Typical

(t_{on_delay}

)

<1Ω to Ground

Figure 10. Start-Up Output Characteristic

FN7707 Rev.6.00

Jul.9.19

Page 10 of 22

ISL89163, ISL89164, ISL89165

3. Typical Performance Curves

3.5

35

30

25

20

15

10

5

+125°C

+25°C

3.0

-40°C

+25°C

-40°C

2.5

2.0

4

8

12

16

4

8

12

16

V

DD

Figure 12. I_DDvs V_DD(1MHz)

Figure 11. I_DDvs V_DD(STATIC)

50

40

30

20

10

0

1.1

1.0

16V

V

Low

OUT

No Load

0.9

0.8

0.7

10V

V

High

OUT

12V

5V

0.6

0.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency (MHz)

-45

-20

5

30

55

80

105

130

Temperature (°C)

Figure 13. I_DDvs Frequency (+25°C)

Figure 14. r_DS(ON)vs Temperature

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.5

Positive Threshold

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Positive Threshold

Negative Threshold

-45

-20

5

30

55

80

105

130

-45

-20

5

30

55

80

105

130

Temperature (°C)

Figure 15. Option A Thresholds

Figure 16. Option B Thresholds

FN7707 Rev.6.00

Jul.9.19

Page 11 of 22

ISL89163, ISL89164, ISL89165

3. Typical Performance Curves

25

30

25

Fall Time, C

= 10nF

LOAD

Output Falling Prop Delay

Output Rising Prop Delay

20

Rise Time, C

= 10nF

LOAD

20

15

-45

-20

5

30

55

80

105

130

5

7

9

11

13

15

V

Temperature (°C)

DD

Figure 18. Propagation Delay vs V_DD

Figure 17. Output Rise/Fall Time

FN7707 Rev.6.00

Jul.9.19

Page 12 of 22

ISL89163, ISL89164, ISL89165

4. Functional Description

The ISL89163, ISL89164, ISL89165 MOSFET drivers incorporate several features optimized for Synchronous

Rectifier (SR) driver applications including precision input logic thresholds, enable inputs, undervoltage lockout,

and high-amplitude output drive currents.

The precision input thresholds facilitate the use of an external RC network to delay the rising or falling propagation

of the driver output; this feature is useful for adjusting when the SRs turn on relative to the primary side FETs. In a

similar manner, these drivers can also be used to control the turn-on/off timing of the primary side FETs.

The enable inputs (ENA, ENB) are used to emulate diode operation of the SRs by disabling the driver output, as

necessary, to prevent negative currents in the output filter inductors. One example is turning off the SRs when the

power supply output is turned off, which prevents the output capacitor from being discharged through the output

inductor. If this is allowed to happen, the voltage across the output capacitor rings negative possibly damaging the

capacitor (if it is polarized) and probably damaging the load. Another example is preventing circulating currents

between paralleled power supplies during no or light-load conditions. During light-load conditions (especially

when active load sharing is not active), energy is transferred from the paralleled power supply that has a higher

voltage to the paralleled power supply with the lower voltage. Consequently, the energy that is absorbed by the

low voltage output transfers to the primary side causing the bus voltage to increase until the primary side is

damaged by excessive voltage.

The start-up sequence for input threshold Options A, B, and C prevents unexpected glitches when V is being

DD

turned on or turned off. When V < ~1V, an internal 10kΩ resistor connected between the output and ground

DD

helps keep the gate voltage close to ground. When ~1V < V < UV, both outputs are driven low while ignoring

DD

the logic inputs. This low state has the same current sinking capacity as during normal operation, and it ensures

that the driven FETs are held off even if there is a switching voltage on the drains that can inject charge into the

gates using the Miller capacitance. When V > UVLO, and after a 400µs delay, the outputs now respond to the

DD

logic inputs. See Figure 10 for complete details.

For the negative transition of V through the UV lockout voltage, the outputs of input threshold Options A or B

DD

are active low when V < ~3.2V regardless of the input logic states. Similarly, the C option outputs are active

DD

DC

low when V < ~6.5V

.

DD

DC

FN7707 Rev.6.00

Jul.9.19

Page 13 of 22

ISL89163, ISL89164, ISL89165

5. Application Information

5.1

Precision Thresholds for Time Delays

Three input logic voltage levels are supported by the ISL89163, ISL89164, ISL89165. Option A uses 3.3V logic,

Option B uses 5.0V logic, and Option C uses higher voltage logic when it is desired to have voltage thresholds

that are proportional to V . The A and B options have nominal thresholds that are 37% and 63% of 3.3V and

DD

5.0V, respectively and the C option is 20% and 80% of V

.

DD

ENx

D

INx

OUTx

R

del

c_del

Figure 19. Delay Using RCD Network

In Figure 19, R and C delay the rising edge of the input signal. For the falling edge of the input signal, the

del

diode shorts out the resistor resulting in a minimal falling edge delay.

The 37% and 63% thresholds of Options A and B were chosen to simplify the calculations for the desired time

delays. When using an RC circuit to generate a time delay, the delay is simply T (secs) = R (ohms) x C (farads).

Note: The equation only applies if the input logic voltage is matched to the 3.3V or 5V threshold options. If the

logic high amplitude is not equal to 3.3V or 5V, the equations shown in Equation 1 can be used for more precise

delay calculations.

(EQ. 1)

High level of the logic signal into the RC

Positive going threshold for 5V logic (B option)

Low level of the logic signal into the RC

V

= 10V

H

= 63% × 5V

thres

= .3V

L

Timing values

R

= 100Ω

= 1nF

del

C

t

del

V

− V

thres









L

= −R

C

× ln

+ 1



del

del del

V

− V

L

H



nominal delay time for this example

t

= 34.788 ns

del

In this example, the high logic voltage is 10V, the positive threshold is 63% of 5V and the low level logic is 0.3V.

Note the rising edge propagation delay of the driver must be added to this value.

The minimum recommended value of C is 100pF. The parasitic capacitance of the PCB and any attached scope

probes introduces significant delay errors if smaller values are used. Larger values of C further minimize errors.

Acceptable values of R are primarily effected by the source resistance of the logic inputs. Generally, 100Ω

resistors or larger are usable.

5.2

Paralleling Outputs to Double the Peak Drive Currents

The typical propagation matching of the ISL89163 and ISL89164 is less than 1ns. The matching is so precise that

carefully matched and calibrated scope probes and channels must be used to make this measurement. Because

of the excellent performance, these driver outputs can be safely paralleled to double the current drive capacity. It

is important that the INA and INB inputs are connected together on the PCB with the shortest possible trace,

which is also required of OUTA and OUTB. However, the ISL89165 cannot be paralleled because of the

complementary logic.

FN7707 Rev.6.00

Jul.9.19

Page 14 of 22

ISL89163, ISL89164, ISL89165

5. Application Information

5.3

Power Dissipation of the Driver

The power dissipation of the ISL89163, ISL89164, ISL89165 is dominated by the losses associated with the gate

charge of the driven bridge FETs and the switching frequency. The internal bias current also contributes to the

total dissipation, but it is usually not significant as compared to the gate charge losses.

12

10

V

= 64V

DS

8

6

4

2

0

V

= 40V

DS

0

2

4

6

8

10 12 14 16 18 20 22 24

Gate Charge (nC)

Q

g,

Figure 20. MOSFET Gate Charge vs Gate Voltage

Figure 20 illustrates how the gate charge varies with the gate voltage in a typical power MOSFET. In this example,

the total gate charge for V = 10V is 21.5nC when V = 40V. This is the charge that a driver must source to turn

gs

DS

on the MOSFET and must sink to turn-off the MOSFET.

Equation 2 shows calculating the power dissipation of the driver:

R

gate

--------------------------------------------

(EQ. 2)

P

= 2 • Q • freq • V

•

+ I (freq) • V

DD DD

D

c

GS

R

+ r

gate

DS(ON)

where:

• freq = Switching frequency,

• V = V bias of the ISL89163, ISL89164, ISL89165

GS

DD

• Q = Gate charge for V

c

GS

• I (freq) = Bias current at the switching frequency (see Figure 11)

DD

• r

= ON-resistance of the driver

DS(ON)

• R

= External gate resistance (if any).

gate

Note: The gate power dissipation is proportionally shared with the external gate resistor. Do not overlook the

power dissipated by the external gate resistor.

5.4

Typical Application Circuits

The drive circuit provides primary-to-secondary line isolation. A controller, on the primary side, is the source of the

SR control, OUTLLN, and OUTLRN signals. The secondary side signals, V1 and V2 are rectified by the dual

diode, D9, to generate the secondary side bias for U4. V1 and V3 are also inverted by Q100 and Q101, and the

rising edges are delayed by R /C and R /C respectively to generate the SR drive signals, LRN and LLN. For

27 10

28

9

complete information on this SR drive circuit, and other applications for the ISL89163, ISL89164, ISL89165, see

AN1603, “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with Synchronous Rectifiers User Guide”.

FN7707 Rev.6.00

Jul.9.19

Page 15 of 22

ISL89163, ISL89164, ISL89165

5. Application Information

PWM

/OUTLLN

/OUTLRN

L

R

L

Primary to Secondary Side Self

Biasing, Isolated SR Drive

VBIAS

R27

ENABLE

D9

V2

OUTLLN

V1

LRN

Q100

C123

V1

U4

R28

V4

R-SR

LSR

V2

LLN

V3

EL7212

ISL89163

U4

OUTLRN

Q101

T6

V3

LLN

C9

C10

V4

Red dashed lines point out the turn-on

delay of the SRs when PWM goes low

LRN

FN7707 Rev.6.00

Jul.9.19

Page 16 of 22

ISL89163, ISL89164, ISL89165

6. General PCB Layout Guidelines

The AC performance of the ISL89163, ISL89164, ISL89165 depends significantly on the design of the PC board.

The following layout design guidelines are recommended to achieve optimum performance:

• Place the driver as close as possible to the driven power FET.

• Understand where the switching power currents flow. The high-amplitude di/dt currents of the driven power FET

will induce significant voltage transients on the associated traces.

• Keep power loops as short as possible by paralleling the source and return traces.

• Use planes where practical; they are usually more effective than parallel traces.

• Avoid paralleling high-amplitude di/dt traces with low level signal lines. High di/dt will induce currents and

consequently, noise voltages in the low level signal lines.

• When practical, minimize impedances in low level signal circuits. The noise, magnetically induced on a 10k^Ω

resistor, is 10x larger than the noise on a 1kΩ resistor.

• Be aware of magnetic fields emanating from transformers and inductors. Gaps in the magnetic cores of these

structures are especially bad for emitting flux.

• If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to

minimize coupling.

• The use of low inductance components, such as chip resistors and chip capacitors, is highly recommended.

• Use decoupling capacitors to reduce the influence of parasitic inductance in the V and GND leads. To be

DD

effective, these caps must also have the shortest possible conduction paths. If vias are used, connect several

paralleled vias to reduce the inductance of the vias.

• It may be necessary to add resistance to dampen resonating parasitic circuits especially on OUTA and OUTB. If

an external gate resistor is unacceptable, the layout must be improved to minimize lead inductance.

• Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected

currents from sensitive circuits, which is especially true for control circuits that source the input signals to the

ISL89163, ISL89164, ISL89165.

• Avoid having a signal ground plane under a high-amplitude dv/dt circuit, which injects di/dt currents into the

signal ground paths.

• Do power dissipation and voltage drop calculations of the power traces. Many PCB/CAD programs have built in

tools for calculation of trace resistance.

• Large power components (Power FETs, Electrolytic caps, power resistors, etc.) have internal parasitic

inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design.

• If you simulate your circuits, consider including parasitic components especially parasitic inductance.

FN7707 Rev.6.00

Jul.9.19

Page 17 of 22

ISL89163, ISL89164, ISL89165

7. General EPAD Heatsinking Considerations

The thermal pad is electrically connected to the GND supply through the IC substrate. The EPAD of the ISL89163,

ISL89164, ISL89165 has two main functions:

• Provide a quiet GND for the input threshold comparators

• Provide heat sinking for the IC

The EPAD must be connected to a ground plane, and no switching currents from the driven FET should pass

through the ground plane under the IC.

Figure 21 is a PCB layout example of how to use vias to remove heat from the IC through the EPAD.

For maximum heatsinking, Renesas recommends that a ground plane, connected to the EPAD, is added to both

sides of the PCB. A via array, within the area of the EPAD, conducts heat from the EPAD to the GND plane on the

bottom layer. The number of vias and the size of the GND planes required for adequate heatsinking is determined

by the power dissipated by the ISL89163, ISL89164, ISL89165, the air flow, and the maximum temperature of the

air around the IC.

EPAD GND Plane

Bottom Layer

Component Layer

Figure 21. Typical PCB Pattern for Thermal Vias

FN7707 Rev.6.00

Jul.9.19

Page 18 of 22

ISL89163, ISL89164, ISL89165

8. Revision History

Rev.

Date

Description

6.00

Jul.9.19

Applied new formatting

Updated 1st paragraph on page 1.

Updated links throughout document.

Updated Ordering Information table adding tape and reel information to table and updating notes, and

removed Note 1.

Removed About Intersil section

Updated disclaimer.

5.00

4.00

Oct.13.16

Sep.30.15

t_{on_delay}parameter added to the AC Electrical Specifications.

The “up to 400µs” label of Figure 9 is changed to “400µs typical (t_{on_delay})”.

Updated the Ordering Information table on page 3.

Replaced Products section with About Intersil section.

Updated Package Outline Drawing L8.3x3I to the latest revision. Changes are as follows:

-Tiebar Note updated

From: Tiebar shown (if present) is a non-functional feature.

To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).

3.00

Feb.22.12

(page 5) ENA and ENB added to the Input Range parameter

(page 6) Propagation delay testing parameters changed for option C

(page 6) Note 13 added

(page 7) Figure 3 modified to show different input thresholds for testing prop delays for option C

(page 4) The startup sequence references for the VDD Undervoltage Lock-out parameters for Option C is now

the same as Options A and B. Options A, B, and C now have the same startup sequence.

(page 5) Note 9 is rewritten to be more precise.

(page 8) The old startup sequence for Option C has been deleted (formerly Figure 10)

(page 10) The old startup sequence description in the Functional Description Overview has been deleted.

2.00

Jan.9.12

(page 1) vertical part numbers in the right margin are deleted to conform to new datasheet standards.

(page 1) Last paragraph of the product description is changed to better describe the improved turn on

characteristics.

(page 1) features list is reduced in size to 8 features. Some features are reworded to improve readability.

(page 1) a reference to a non-existent application note is deleted from the Related Literature section.

(page 2) pin configuration pictures are redrawn and relabeled for readability.

(page 2) some pins description names are changed to corollate to the pin name in the pin configuration

pictures. Some descriptions are also corrected. The truth table associated with the pin descriptions is

expanded to include the logic performance of the under-voltage. (these revisions are not a change to function).

(page 4) note and figure references are added to the VDD Under-voltage lock-out parameter for options A, B,

and C

(page 5) note 12 is revised to more clearly describe the turn-on characteristics of options A, B, and C.

(page 6) no load test conditions added to the rising and falling propagation matching parameters.

(page 8) figures 7 and 8 added to clearly define the startup characteristics

(page 10) the last paragraph of the Functional Description overview is replaced by 3 paragraphs to more

clearly describe the under voltage and turn-on and turn-off characteristics.

(page 11). A new section is added to the application information describing how the drivers outputs can be

paralleled.

(pages 1..13) various minor corrections to text for grammar and spelling.

1.00

0.00

Aug.26.11

Oct.12.10

(page 8) Note 12 revised from 200µs to 400µs

(page 6) The Operating Junction Temp Range in the “Thermal Information” was revised to read

“Maximum Operating Junction Temp Range....-40°C to +150°C” from “-40°C to +125°C”

Updated POD M8.15D by converting to new POD format. Removed table of dimensions and moved

dimensions onto drawing. Added land pattern.

Initial release

FN7707 Rev.6.00

Jul.9.19

Page 19 of 22

ISL89163, ISL89164, ISL89165

9. Package Outline Drawings

For the most recent package outline drawing, see L8.3x3I.

9. Package Outline Drawings

L8.3x3I

8 Lead Thin Dual Flat No-Lead Plastic Package

Rev 2 5/15

2X 1.950

3.00

A

6X 0.65

B

5

8

(4X)

0.15

1.64 +0.10/ - 0.15

6

PIN 1

INDEX AREA

6

PIN #1 INDEX AREA

4

1

4

8X 0.30

0.10 M C A B

8X 0.400 ± 0.10

TOP VIEW

2.38

+0.10/ - 0.15

BOTTOM VIEW

SEE DETAIL "X"

( 2.38 )

( 1.95)

C

0.10

C

Max 0.80

0.08

C

SIDE VIEW

( 8X 0.60)

(1.64)

( 2.80 )

PIN 1

5

0 . 2 REF

C

(6x 0.65)

0 . 00 MIN.

0 . 05 MAX.

( 8 X 0.30)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature and may be

located on any of the 4 sides (or ends).

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN7707 Rev.6.00

Jul.9.19

Page 20 of 22

ISL89163, ISL89164, ISL89165

9. Package Outline Drawings

M8.15D

For the most recent package outline drawing, see M8.15D.

8 Lead Narrow Body Small Outline Exposed Pad Plastic Package

Rev 1, 3/11

8

INDEX

AREA

6.20 (0.244)

5.84 (0.230)

DETAIL "A"

1.27 (0.050)

0.41 (0.016)

3.99 (0.157)

3.81 (0.150)

0.50 (0.02)

x 45°

1

2

3

0.25 (0.01)

TOP VIEW

8°

0°

0.25 (0.010)

0.19 (0.008)

SEATING PLANE

SIDE VIEW “B”

1.72 (0.067)

4.98 (0.196)

4.80 (0.189)

1.52 (0.059)

-C-

2.25

(0.089)

1.95

(0.077)

0.25 (0.010)

0.10 (0.004)

1.27 (0.050)

1

2

3

4

8

7

6

5

0.46 (0.019)

0.36 (0.014)

0.60 (0.023)

1.27 (0.050)

SIDE VIEW “A

1

2

3

5.45 (0.214)

2.50 (0.099)

2.00 (0.078)

TYPICAL RECOMMENDED LAND PATTERN

8

Notes:

1. Dimensions are in millimeters. Dimensions in ( ) for reference only.

2. Dimensioning and tolerancing per ASME-Y14.5M-1994.

3. Unless otherwise specified, tolerance: Decimal ± 0.05.

3.50 (0.137)

3.00 (0.118)

4. Dimension does not include interlead flash or protrusions. Interlead flash

BOTTOM VIEW

or protrusions shall not exceed 0.25mm per side.

5. The Pin 1 identifier may be either a mold or a mark feature.

6. The chamfer on the body is optional. If it is not present, a visual index

FN7707 Rev.6.00

Jul.9.19

Page 21 of 22

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TOYOSU FORESIA, 3-2-24 Toyosu,

For further information on a product, technology, the most up-to-date

Koto-ku, Tokyo 135-0061, Japan

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型号：	ISL89165FRTBZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs; DFN8, SOIC8; Temp Range: -40° to 125°C 驱动光电二极管接口集成电路驱动器
文件：	总22页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL89165FRTBZ-T [RENESAS]

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