ISL9222A [INTERSIL]
High Input Voltage Charger Low Component Count and Cost; 高输入电压充电器的低元件数量和成本
| 型号： | ISL9222A |
| 厂家： | 
Intersil |
| 描述： | High Input Voltage Charger Low Component Count and Cost |
| 文件： | 总8页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9222A
®
Data Sheet
July 28, 2008
FN6704.0
High Input Voltage Charger
Features
The ISL9222A is a cost-effective, fully integrated high input
voltage single-cell Li-ion battery charger. The charger uses a
CC/CV charge profile required by Li-ion batteries. The
charger accepts an input voltage up to 28V but is disabled
when the input voltage exceeds the OVP threshold, typically
7.2V, to prevent excessive power dissipation. The 28V rating
eliminates the overvoltage protection circuit required in a low
input voltage charger.
• Complete Charger for Single-Cell Li-ion/Polymer Batteries
• Integrated Pass Element and Current Sensor
• No External Blocking Diode Required
• Low Component Count and Cost
• 1% Voltage Accuracy
• Programmable Charge Current
The charge current is user programmable with an external
resistor. When the battery voltage is lower than typically
2.55V, the charger preconditions the battery with typically
20% of the programmed charge current. An internal thermal
foldback function protects the charger from any thermal
failure.
• Charge Current Thermal Foldback for Thermal
Protection
• Trickle Charge for Fully Discharged Batteries
• 28V Maximum Voltage for the Power Input
• Power Presence Indication
AN indication pin PPR allows simple interface to a
microprocessor or LED. When no adapter is attached or
when disabled, the charger draws less than 1µA leakage
current from the battery.
• Less Than 1µA Leakage Current off the Battery When No
Input Power Attached or Charger Disabled
• Ambient Temperature Range: -40°C to +85°C
• 8 Ld 2x3 TDFN Package
Ordering Information
• Auxiliary OR-gate For System Booting Logic
• Pb-Free (RoHS Compliant)
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
Applications
• Mobile Phones
• Blue-Tooth Devices
• PDAs
ISL9222AIRTZ-T 22A
-40 to +85 8 Ld 2x3 TDFN L8.2x3A
Tape and Reel
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• MP3 Players
• Stand-Alone Chargers
• Other Handheld Devices
Pinout
ISL9222A
(8 LD TDFN)
TOP VIEW
VIN
BAT
1
2
3
4
8
7
6
5
PPR
JIGON
EN
IREF
JIGIN
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9222A
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
JIGIN, IREF, BAT, JIGON, EN, PPR . . . . . . . . . . . . . . . . -0.3V to 7V
Thermal Resistance
θ
(°C/W)
59
θ
(°C/W)
4.5
JA
JC
TDFN Package (Notes 1, 2). . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Supply Voltage (VIN Pin). . . . . . . . . . . . . . . . . . . . . . 28V
Operating Supply Voltage (VIN Pin). . . . . . . . . . . . . . . . 4.5V to 6.5V
Programmed Charge Current . . . . . . . . . . . . . . . . 100mA to 900mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Typical values are tested at V = 5V and the ambient temperature at +25°C. All maximum and minimum
IN
values are established under the recommended operating supply voltage range and ambient temperature
range, unless otherwise noted.
PARAMETER
POWER-ON RESET
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rising POR Threshold
Falling POR Threshold
VIN-BAT OFFSET VOLTAGE
Rising Edge
V
V
3.5
2.8
3.9
3.4
4.4
V
V
POR
POR
VBAT = 3.0V, use PPR to indicate the
comparator output.
3.50
V
-
90
50
150
-
mV
mV
OS
OS
Monitor output current to indicate the
comparator output. (Note 3)
Falling Edge
V
10
OVERVOLTAGE PROTECTION
Overvoltage Protection Threshold
OVP Threshold Hysteresis
STANDBY CURRENT
BAT Pin Sink Current
V
6.9
7.2
7.5
V
OVP
Use PPR to indicate the comparator output.
(Note 4)
100
240
400
mV
I
VIN floating
-
-
-
-
1.0
600
800
µA
µA
µA
STANDBY
VIN Pin Supply Current
VIN Pin Supply Current
VOLTAGE REGULATION
Output Voltage
I
I
Charger disabled
Charger enabled
350
500
VIN
VIN
V
4.3V < V < 6.5V, charge current = 20mA
IN
4.158
-
4.20
0.6
4.242
-
V
CH
PMOS ON-Resistance
CHARGE CURRENT (Note 5)
IREF Pin Output Voltage
Constant Charge Current
Trickle Charge Current
r
V
= 3.8V, charge current = 0.5A
Ω
DS(ON)
BAT
I
V
= 3.8V
1.18
440
70
1.22
500
95
1.26
550
130
V
IREF
BAT
I
R
R
= 24.3kΩ, V
= 24.3kΩ, V
= 2.8V - 4.0V
= 2.4V
mA
mA
CHG
IREF
IREF
BAT
BAT
I
TRK
PRECONDITIONING CHARGE THRESHOLD
Preconditioning Charge Threshold Voltage
V
2.45
-
2.55
250
2.65
-
V
MIN
Preconditioning Voltage Hysteresis
V
mV
MINHYS
INTERNAL TEMPERATURE MONITORING
Charge Current Foldback Threshold
T
-
115
-
°C
FOLD
FN6704.0
July 28, 2008
2
ISL9222A
Electrical Specifications Typical values are tested at V = 5V and the ambient temperature at +25°C. All maximum and minimum
IN
values are established under the recommended operating supply voltage range and ambient temperature
range, unless otherwise noted. (Continued)
PARAMETER
LOGIC INPUT AND OUTPUTS
EN Pin Logic Input High
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1.3
-
-
-
-
0.5
400
-
V
V
VIH
VIL
EN Pin Logic Input Low
EN Pin Internal Pull-Down Resistance
PPR Sink Current when LOW
PPR Leakage Current When HIGH
AUXILIARY OR GATE
100
10
-
200
20
-
kΩ
mA
µA
Pin Voltage = 1V
= 6.5V
V
1
PPR
Supply Voltage
V
2.5
-
-
5.0
-
V
V
S
JIGON High Level Output Voltage
VOH
VBAT -
0.1V
I
= -60μA, 2.5V < VBAT < 5.0V
JIGON(SOURCE)
JIGON(SOURCE)
VBAT-
0.45V
-
-
V
I
I
= -1mA, 3.0V < VBAT < 5.0V
JIGON Out Put Low Voltage
JIGIN Pin Logic Input High
VOL
VIH
= 1mA
-
-
-
-
0.1
V
V
V
JIGON(SINK)
VBAT = 2.5V
2.1
-
-
0.75 x
VBAT
3.0V < VBAT < 5.0V
VBAT = 2.5V
JIGIN Pin Logic Input Low
VIL
-
-
-
-
0.4
V
V
0.25x
VBAT
3.0V < VBAT < 5.0V
JIGIN Pin Internal Pull-Down Resistance
NOTES:
100
240
400
kΩ
3. The output is used to test the VOS threshold. The output current will toggle between 0 and the CC current when VOS crosses over the threshold.
4. For junction temperature below +100°C.
5. The charge current can be affected by the thermal foldback function if the IC under the test setup cannot dissipate the heat.
GND - System ground.
Pin Descriptions
VIN - Power input. The absolute maximum input voltage is
28V. A 1µF or larger value X5R ceramic capacitor is
recommended to be placed very close to the input pin for
decoupling purpose. Additional capacitance may be required
to provide a stable input voltage.
JIGIN - One of the inputs of the 2-input auxiliary OR gate.
There is a 240kΩ pull down resistor at this pin.
IREF - Charge-current program and monitoring pin. Connect
a resistor between this pin and the GND pin to set the
charge current limit determined by Equation 1:
PPR - Open-drain power presence indication. The
12089
(EQ. 1)
-----------------
I
=
(mA)
REF
open-drain MOSFET turns on when the input voltage is
above the POR threshold but below the OVP threshold and
off otherwise. This pin is capable to sink 10mA (minimum)
current to drive an LED. The maximum voltage rating for this
pin is 7V. This pin is independent on the EN-pin input.
R
IREF
Where R
IREF
is in kΩ. The IREF pin voltage also monitors
the actual charge current during the entire charge cycle,
including the trickle, constant-current, and constant-voltage
phases. When disabled, VIREF = 0V.
JIGON - Output pin of the auxiliary 2-input OR gate. One of
the inputs is internal and is connected to the inverted PPR
logic. The other input is from the JIGIN pin driven externally
to provide system booting enable signal.
BAT - Charger output pin. Connect this pin to the battery. A
1µF or larger X5R ceramic capacitor is recommended for
decoupling and stability purposes. When the EN pin is pulled
to logic HIGH, the BAT output is disabled.
EN - Enable input. This is a logic input pin to disable or
enable the charger. Drive to HIGH to disable the charger.
When this pin is driven to LOW or left floating, the charger is
enabled. This pin has an internal 200kΩ pull-down resistor.
EPAD - Exposed pad. Connect as much copper as possible
to this pad either on the component layer or other layers
through thermal vias to enhance the thermal performance.
FN6704.0
July 28, 2008
3
ISL9222A
Typical Applications
TO INPUT POWER
BAT
VIN
R
470
2
C
1µF
1
BATT
C
1 µF
SYSTEM
CONTROLLER
2
R1
1?
D
1
PPR
IREF
ISL9222A
GND
R
IREF
EN
GPIO
R
3
ON
JIGON
JIGIN
BOOT
OFF
C
3
TABLE 1. JIGON STATES
VBAT VOLTAGE
PRESENT, OR BATTERY
ATTACHED
POWER GOOD
JIGIN
JIGON
PPR
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low
Low
No
No
L
L
No
Yes
No
Yes
X
L
L
No
H
H
L
L
No
H
H
H
Yes
Yes
H
X
FN6704.0
July 28, 2008
4
ISL9222A
VIN
BAT
VOS
PRE
REG
BAT
POR
OVP
VREF
CHARGE
CONTROL
VREF
PPR
VCC
EN
BAT
VCC
EN
200kΩ
240kΩ
DIE
TEMP
GND
+115OC
JIGIN
JIGON
IREF
FIGURE 1. BLOCK DIAGRAM
TRICKLE
CC
CV
4.2V
IREF
CHARGE
VOLTAGE
CHARGE
CURRENT
2.55V
19% IREF
TIME
FIGURE 2. TYPICAL CHARGE PROFILE
Description
The ISL9222A charges a Li-ion battery using a CC/CV
profile. The constant current I is set with the external
threshold. Fast charge CC mode is maintained at the rate
determined by programming I until the cell voltage rises
to 4.2V. When the battery voltage reaches 4.2V, the charger
enters a CV mode and regulates the battery voltage at 4.2V
to fully charge the battery without the risk of over charge.
The charger will continue to output the 4.2V voltage until the
REF
(See Typical Applications circuit on page 4)
REF
resistor R
IREF
and the constant voltage is fixed at 4.2V. If the battery
voltage is below a typical 2.55V trickle-charge threshold, the
ISL9222A charges the battery with a trickle current of 19% of
I
until the battery voltage rises above the trickle charge
REF
FN6704.0
July 28, 2008
5
ISL9222A
input power is removed or the EN pin is pulled to HI. Figure 2
shows the typical charge waveforms after the power is on.
HIGH to disable the charger. The threshold for HIGH is given
in the Electrical Specifications table on page 2.
A thermal foldback function reduces the charge current
anytime when the die temperature reaches typically +115°C.
This function guarantees safe operation when the
printed-circuit board (PCB) is not capable of dissipating the
heat generated by the linear charger. The ISL9222A accepts
an input voltage up to 28V but disables charging when the
input voltage exceeds the OVP threshold, typically 7.2V, to
protect against unqualified or faulty AC adapters.
IREF Pin
The IREF pin has the two functions as described in “Pin
Descriptions” on page 3. When setting the fast charge
current, the charge current is guaranteed to have 10%
accuracy with the charge current set at 500mA. When
monitoring the charge current, the accuracy of the IREF pin
voltage vs. the actual charge current is the same as the gain
from the IREF pin current to the actual charge current. The
accuracy is 10% at 500mA and is expected to drop to 30% of
the actual current (not the set constant charge current) when
the current drops to 50mA.
PPR Indication
The PPR pin is an open-drain output to indicate the
presence of the ac adapter. Whenever the input voltage is
higher than the POR threshold, the PPR pin turns on the
internal open-drain MOSFET to indicate a logic LOW signal,
independent on the EN pin input. When the internal
open-drain FET is turned off, the PPR pin should leak less
than 1µA current. When turned on, the PPR pin should be
able to sink at least 10mA current under all operating
conditions.
Operation Without the Battery
The ISL9222A relies on a battery for stability and is not
guaranteed to be stable if the battery is not connected. With
a battery, the charger will be stable with an output ceramic
decoupling capacitor in the range of 1µF to 200µF. The
maximum load current is limited by the dropout voltage or
the thermal foldback.
The PPR pin can be used to drive an LED or to interface with
a microprocessor.
Dropout Voltage
The constant current may not be maintained due to the
r
limit at a low input voltage. The worst case
Power-Good Range
DS(ON)
ON-resistance of the pass FET is 1.2Ω at the maximum
operating temperature, thus if tested with 0.5A current and
3.8V battery voltage, constant current could not be
maintained when the input voltage is below 4.4V.
The power-good range is defined by the following three
conditions:
1. VIN > VPOR
2. VIN - VBAT > VOS
3. VIN < VOVP
Thermal Foldback
The thermal foldback function starts to reduce the charge
current when the internal temperature reaches a typical
value of +115°C.
where VOS is the offset voltage for the input and output
voltage comparator, discussed shortly, and VOVP is the
overvoltage protection threshold given in the Electrical
Auxiliary OR Gate
Specifications table on page 2. All V
, V , and V
POR OS OVP
have hysteresis, as given in the Electrical Specification table
on page 2. The charger will not charge the battery if the input
voltage is not in the power-good range.
The auxiliary OR gate provides a booting enable signal from
from 2 possible inputs, the VIN power good signal, which is
internal to the IC, or the external JIGIN signal. The supply
voltage of the OR gate comes from VBAT. The JIGON states
are summarized in Table 1. There is an internal pull-down
resistor at the JIGIN pin so that when left floating, the input is
a logic low.
Input and Output Comparator
The charger will not be enabled unless the input voltage is
higher than the battery voltage by an offset voltage VOS.
The purpose of this comparator is to ensure that the charger
is turned off when the input power is removed from the
charger. Without this comparator, it is possible that the
charger will fail to power-down when the input is removed
and the current can leak through the PFET pass element to
continue biasing the POR and the Pre-Regulator blocks
shown in the Block Diagram on page 5.
Applications Information
Input Capacitor Selection
The input capacitor is required to suppress the power supply
transient response during transitions. Mainly, this capacitor
is selected to avoid oscillation during the start up when the
input supply is passing the POR threshold and the VIN-BAT
comparator offset voltage. A 1µF or larger X5R ceramic
capacitor is recommended.
EN Input
EN is an active-low logic input to enable the charger. Drive
the EN pin to LOW or leave it floating to enable the charger.
This pin has a 200kΩ internal pulldown resistor so when left
floating, the input is equivalent to logic LOW. Drive this pin to
Due to the inductance of the power leads of the wall adapter
or USB source, the input capacitor type must be properly
selected to prevent high voltage transient during a hot-plug
FN6704.0
July 28, 2008
6
ISL9222A
event. A tantalum capacitor is a good choice for its high
Layout Guidance
ESR, providing damping to the voltage transient. Multi-layer
ceramic capacitors, however, have a very low ESR and
hence when chosen as input capacitors, a 1Ω series resistor
must be used (as shown in “Typical Applications” on page 4)
to provide adequate damping.
The ISL9222A uses a thermally-enhanced TDFN package
that has an exposed thermal pad at the bottom side of the
package. The layout should connect as much as possible to
copper on the exposed pad. Typically, the component layer
is more effective in dissipating heat. The thermal impedance
can be further reduced by using other layers of copper
connecting to the exposed pad through a thermal via array.
Each thermal via is recommended to have 0.3mm diameter
and 1mm distance from other thermal vias.
Output Capacitor Selection
The criteria for selecting the output capacitor is to maintain
the stability of the charger as well as to bypass any transient
load current. The minimum capacitance is a 1µF X5R
ceramic capacitor. The actual capacitance connected to the
output is dependent on the actual application requirement.
Input Power Sources
The input power source is typically a well-regulated wall
cube with 1-meter length wire or a USB port. The input
voltage ranges from 4.25V to 6.5V under full-load and
unloaded conditions. The ISL9222A can withstand up to 28V
on the input without damaging the IC. If the input voltage is
higher than typically 7.2V, the charger stops charging.
Charge Current Limit
The actual charge current in CC mode is limited by several
factors in addition to the set I
. Figure 3 shows three limits
REF
for the charge current in CC mode. The charge current is
limited by the ON-resistance of the pass element (power
P-channel MOSFET) if the input and the output voltage are
too close to each other. The solid curve shows a typical case
when the battery voltage is 4.0V and the charge current is
set to 700mA. The non-linearity on the R -limited region is
ON
due to the increased resistance at higher die temperatures. If
the battery voltage increases to higher than 4.0V, the entire
curve moves towards the right side. As the input voltage
increases, the charge current may be reduced due to the
thermal foldback function. The limit caused by the thermal
limit is dependent on the thermal impedance. As the thermal
impedance increases, the thermal-limited curve moves
towards left, as shown in Figure 3.
THERMAL
LIMITED
700
R
ON
LIMITED
R
IREF
INCREASES
θ
or T
A
JA
INCREASES
V
BAT
INCREASES
4.0
4.5
5.0
5.5
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 3. CHARGE CURRENT LIMITS IN THE CC MODE
FN6704.0
July 28, 2008
7
ISL9222A
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.2x3A
0.15
C A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.70
NOMINAL
MAX
0.80
NOTES
A
A1
A3
b
0.75
-
-
0.20
1.50
1.65
-
0.20 REF
0.25
0.05
-
E
-
6
INDEX
AREA
0.32
1.75
1.90
5,8
D
2.00 BSC
1.65
-
B
A
D2
E
7,8
TOP VIEW
3.00 BSC
1.80
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.20
0.30
-
-
SIDE VIEW
A3
C
SEATING
PLANE
L
0.40
0.50
8
N
8
2
D2
D2/2
2
7
8
Nd
4
3
(DATUM B)
Rev. 0 6/04
NOTES:
1
NX k
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
e
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10
M
C A B
(Nd-1)Xe
REF.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
(A1)
NX (b)
5
L
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6704.0
July 28, 2008
8
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