LP3907SQ-JIXI_技术文档

December 12, 2007

LP3907

Dual High-Current Step-Down DC/DC and Dual Linear

Regulator with I2C Compatible Interface

General Description

Features

The LP3907 is a multi-function, programmable Power Man-

agement Unit, optimized for low power FPGAs, microproces-

sors and DSPs. This device integrates two highly efficient 1A/

600mA step-down DC/DC converters with dynamic voltage

management (DVM), two 300mA linear regulators and a

400kHz I²C compatible interface to allow a host controller ac-

cess to the internal control registers of the LP3907. The

LP3907 additionally features programmable power-on se-

quencing. Package options include a tiny 4 x 4 x 0.8mm LLP

24–pin package and an even smaller 2.5 x 2.5mm micro SMD

25-bump package.

Compatible with advanced applications processors and

■

FPGAs

2 LDOs for powering Internal processor functions and I/Os

■

High speed serial interface for independent control of

device functions and settings

Precision internal reference

■

Thermal overload protection

Current overload protection

24-lead 4 × 4 × 0.8mm LLP or 25–bump 2.5 x 2.5mm micro

SMD package

Software Programmable Regulators

■

Key Specifications

External Power-on-reset function for Buck1 and Buck2

(i.e., Power Good with delay function)

Undervoltage lock out detector to monitor input supply

voltage

Step-Down DC/DC Converter (Buck)

■

1A/600mA output current

■

Programmable V_OUTfrom:

Buck1 : 0.8V–2.0V @ 1A

—

Applications

Buck2 : 1.0V–3.5V @ 600mA

FPGA, DSP core power

■

Up to 96% efficiency

■

Applications processors

2.1MHz PWM switching frequency

PWM - PFM automatic mode change under low loads

±3% output voltage accuracy

Automatic soft start

Peripheral I/O power

Linear Regulators (LDO)

Programmable V_OUTof 1.0V–3.5V

■

±3% output voltage accuracy

300mA output current

30mV (typ) dropout

300178

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Typical Application Circuit

30017801

FIGURE 1. Application Circuit

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30017802

FIGURE 2. Application Circuit

3

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Connection Diagrams and Package Mark Information

30017803

24-Lead LLP Package (top view

Note:

The physical placement of the package marking will vary from part to part.

(*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code. See http://www.national.com/quality/

marking_conventions.html for more information on marking information.

(**) Package received will have XXXX replaced with the specific part version ordered.

25-Bump Thin Micro SMD Package, Large Bump National Package Number TLA25AAA

30017890

30017889

Top View

Bottom View

30017888

Package Mark - Top View

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Ordering Information

Voltage Option

Order Number

Package Type

NSC Package

Drawing

Package Marking

Supplied As

Voltage “PXPP”

LP3907SQ-PXPP

24-lead LLP

SQA024AE

TLA25AAA

07-PXPP

07–PXPP

07–JXQX

07PJXQX

07–JIXI

1000 tape & reel

4500 tape & reel

1000 tape & reel

4500 tape & reel

1000 tape & reel

4500 tape & reel

1000 tape & reel

4500 tape & reel

250 tape & reel

Voltage “PXPP” LP3907SQX-PXPP

Voltage “JXQX”

LP3907SQ-JXQX

LP3907SQX-JXQX

Voltage “JXQX” LP3907SQ-JXQX**

Voltage “JXQX” LP3907SQX-JXQX** 24-lead LLP

Voltage “JIXI”

Voltage “JSXS”

LP3907SQ-JIXI

LP3907SQX-JIXI

LP3907TL-JSXS

24-lead LLP

07–JIXI

25–bump micro

SMD

V012

Voltage “JSXS”

LP3907TLX-JSXS 25–bump micro

SMD

TLA25AAA

V012

3000 tape & reel

** For Forced PWM Buck Regulators use spec # S7001874 when ordering.

Default Voltage Options

Regulator

Version “PXPP” Default Version “JXQX” Default Version “JSXS” Default Version “JIXI” Default

Voltages (V)

SW1

SW2

1.5

3.3

2.5

1.2

3.3

2.6

3.3

1.2

2.8

3.3

2.8

1.2

3.3

1.8

3.3

LDO1

LDO2

Package Type

24–lead LLP

Default I²C Address

60

61

25–bump micro SMD

5

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Pin Descriptions

micro SMD

pin no.

Description

LLP Pin No.

Name

I/O

Type

1

B4, B5

VINLDO12

I

PWR

Analog Power for Internal Functions (VREF, BIAS, I2C,

Logic)

2

3

C4

C3

EN_T

nPOR

I

D

Enable for preset power on sequence. (see page 20)

O

nPOR Power on reset pin for both Buck1 and Buck 2.

Open drain logic output 100K pullup resistor. nPOR is

pulled to ground when the voltages on these supplies are

not good. See nPOR section for more info.

4

5

6

7

C5

D5

E5

D4

GND_SW1

SW1

G

O

I

G

Buck1 NMOS Power Ground

PWR

D

Buck1 switcher output pin

VIN1

Power in from either DC source or Battery to Buck1

ENSW1

I

Enable Pin for Buck1 switcher, a logic HIGH enables

Buck1

8

E4

D3

E3

E2

D2

FB1

GND_C

AVDD

FB2

I

G

I

A

G

Buck1 input feedback terminal

Non switching core ground pin

Analog Power for Buck converters

Buck2 input feedback terminal

9

10

11

12

PWR

A

I

ENSW2

I

D

Enable Pin for Buck2 switcher, a logic HIGH enables

Buck2

13

14

15

16

17

18

19

E1

D1

C1

C2

B2

B1

A1

VIN2

SW2

I

O

G

I/O

I

PWR

G

Power in from either DC source or Battery to Buck2

Buck2 switcher output pin

Buck2 NMOS Power ground

I²C Data (bidirectional)

I²C Clock

GND_SW2

SDA

D

SCL

D

GND_L

VINLDO1

G

I

G

LDO ground

PWR

Power in from either DC source or battery to input

terminal to LDO1

20

21

22

23

24

A2

B3

A3

A4

A5

LDO1

ENLDO1

ENLDO2

LDO2

O

I

PWR

D

LDO1 Output

LDO1 enable pin, a logic HIGH enables the LDO1

LDO2 enable pin, a logic HIGH enables the LDO2

LDO2 Output

I

D

O

I

PWR

VINLDO2

Power in from either DC source or battery to input

terminal to LDO2

A: Analog Pin

D: Digital Pin

G: Ground Pin

PWR: Power Pin

I: Input Pin

I/O: Input/Output Pin

O: Output Pin.

Power Block Operation

Enabled Disabled

Note

Power Block Input

VINLDO12

AVDD

VIN1

VIN+

Always Powered

VIN+

Always Powered

VIN+ or 0V

VIN2

LDO 1

LDO 2

≤ VIN+

If Enabled, Min Vin is 1.74V

VIN+ is the largest potential voltage on the device.

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Ratings: Bucks

(Notes 1, 2, 7, 18)

V_IN

2.8V to 5.5V

V_EN

0 to (V_IN+ 0.3V)

V_IN, SDA, SCL

−0.3V to +6V

±0.3V

Junction Temperature (T_J) Range

−40°C to +125°

C

GND to GND SLUG

Power Dissipation (P_{D_MAX}

(T_A=85°C, T_MAX=125°C, )(Note 5)

)

Ambient Temperature (T_A) Range (Note 6) −40°C to +85°C

1.43W

150°C

−65°C to +150°C

260°C

Junction Temperature (T_J-MAX

Storage Temperature Range

Maximum Lead Temperature (Soldering)

)

Thermal Properties (Notes 3, 5, 6)

Junction-to-Ambient Thermal

28°C/W

Resistance (θ_JA) SQA024AE

ESD Ratings

Human Body Model (Note 4)

2kV

General Electrical Characteristics (Notes 1, 2, 7, 13, 17)

Unless otherwise noted, V_IN= 3.6V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in

boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.

Symbol

Parameter

Conditions

V_IN= 3.6V

Min

Typ

3

Max

Units

µA

V

I_Q

VINLDO12 Shutdown Current

Power-On Reset Threshold

Thermal Shutdown Threshold

Themal Shutdown Hysteresis

Under Voltage Lock Out

V_POR

T_SD

V_DDFalling Edge(Note 17)

1.9

160

20

°C

T_SDH

UVLO

°C

Rising

Falling

2.9

2.7

V

I²C Compatible Interface Electrical Specifications (Note 13)

Unless otherwise noted, V_IN= 3.6V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in

boldface type apply over the entire junction temperature range for operation, −40°C to +125°C

Symbol

F_CLK

Parameter

Clock Frequency

Bus-Free Time Between Start and Stop (Note 13)

Conditions

Min

Typ

Max

Units

kHz

µs

400

t_BF

1.3

0.6

1.3

0.6

0

t_HOLD

t_CLKLP

t_CLKHP

t_SU

Hold Time Repeated Start Condition

CLK Low Period

(Note 13)

µs

CLK High Period

µs

Set Up Time Repeated Start Condition (Note 13)

µs

t_DATAHLD

t_DATASU

T_SU

Data Hold time

(Note 13)

µs

Data Set Up Time

100

0.6

ns

Set Up Time for Start Condition

µs

T_TRANS

Maximum Pulse Width of Spikes that

Must be Suppressed by the Input Filter of

Both DATA & CLK Signals.

50

ns

7

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Low Drop Out Regulators, LDO1 and LDO2

Unless otherwise noted, V_IN= 3.6, C_IN= 1.0µF, C_OUT= 0.47µF. Typical values and limits appearing in normal type apply for T_J=

25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes

2, 7, 8, 9, 10, 11, 12)

Symbol

Parameter

Conditions

Min

1.74

−3

Typ

Max

5.5

3

Units

V_IN

Operational Voltage Range

VINLDO1 and VINLDO2 PMOS

pins (Note 15)

V

V_OUTAccuracy Output Voltage Accuracy (Default V_OUT

)

Load current = 1 mA

%

Line Regulation

V_IN= (V_OUT+ 0.3V) to 5.0V,

(Note 12), Load Current = mA

V_IN= 3.6V,

ΔV_OUT

0.15

%/V

Load Regulation

0.011

200

%/mA

mA

Load Current = 1mA to I_MAX

I_SC

Short Circuit Current Limit

Dropout Voltage

LDO1-2, V_OUT= 0V

500

30

V_IN– V_OUT

Load Current = 50mA

(Note 10)

mV

PSRR

Power Supply Ripple Rejection

Supply Output Noise

Quiescent Current “On”

Quiescent Current “Off”

Turn On Time

F = 10kHz, Load Current = I_MAX

10Hz < F < 100KHz

I_OUT= 0mA

45

80

dB

µVrms

µA

θn

I_Q(Notes 11,

14)

40

I_OUT= I_MAX

60

µA

EN is de-asserted(Note 16)

Start up from shut-down

Capacitance for stability

0°C ≤ T_J≤ 125°C

0.03

300

µA

T_ON

µs

C_OUT

Output Capacitor

0.33

0.47

1.0

µF

0.68

5

µF

−40°C ≤ T_J≤ 125°C

ESR

500

mΩ

Buck Converters SW1, SW2

Unless otherwise noted, V_IN= 3.6, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2 µH ceramic. Typical values and limits appearing in normal

type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°

C to +125°C. (Notes 2, 7, 8, 9, 11, 18)

Symbol

V_FB

Parameter

Feedback Voltage

Conditions

Min

Typ

Max

Units

%

−3

+3

V_OUT

Line Regulation

2.8< V_IN< 5.5

0.089

%/V

I_O=10mA

Load Regulation

100mA < I_O< I_MAX

Load Current = 250mA

EN is de-asserted

0.0013

96

%/mA

%

Eff

Efficiency

I_SHDN

f_OSC

I_PEAK

Shutdown Supply Current

Internal Oscillator Frequency

Buck1 Peak Switching Current Limit

Buck2 Peak Switching Current Limit

Quiescent Current “On”

Pin-Pin Resistance PFET

Pin-Pin Resistance NFET

Turn On Time

0.01

2.1

µA

1.7

MHz

A

1.5

1.0

I_Q(Note 14)

R_DSON(P)

R_DSON(N)

T_ON

No load PFM Mode

33

µA

200

180

500

mΩ

µs

Start up from shut-down

Capacitance for stability

C_IN

Input Capacitor

10

µF

C_O

Output Capacitor

µF

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I/O Electrical Characteristics

Unless otherwise noted: Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in boldface

type apply over the entire junction temperature range for operation, T_J= 0°C to +125°C. (Note 13)

Limit

Symbol

Parameter

Conditions

Units

Min

1.2

Max

0.4

V_IL

V_IH

Input Low Level

Input High Level

V

Power On Reset Threshold/Function (POR)

Symbol

nPOR

Parameter

Conditions

Min

Typ

Max

Units

nPOR = Power on reset forBuck1 and

Buck2

Default

50

ms

nPOR

threshold

Percentage of Target voltage Buck1 or V_BUCK1AND V_BUCK2rising

94

85

%

V

Buck2

V_BUCK1OR V_BUCK2falling

VOL

Output Level Low

Load = IoL = 500mA

0.23

0.5

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 160°C (typ.) and disengages at T_J

= 140°C (typ.)

Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MILSTD - 883 3015.7)

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power

dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θ_JA), as given by the

following equation: T_A-MAX= T_J-MAX-OP− (θ_JA× P_D-MAX). See Applications section.

Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 8: C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 9: The device maintains a stable, regulated output voltage without a load.

Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal value.

Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

Note 12: V_INminimum for line regulation values is 1.8V.

Note 13: This specification is guaranteed by design.

Note 14: The I_Qcan be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled via the I²C

bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two values can be used by the system

designer when the LP3907 is powered using a battery.

Note 15: Pins 24, 19 can operate from V_INmin of 1.74 to a V_INmax of 5.5V. This rating is only for the series pass PMOS power FET. It allows the system design

to use a lower voltage rating if the input voltage comes from a buck output.

Note 16: The I_Qexhibits a higher current draw when the EN pin is de-asserted because the I²2 buffer pins draw an additional 2µA.

Note 17: VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and

is also different from the nPOR function, which signals if the regulators are in a specified range.

Note 18: Buck V_IN≥ V_OUT+ 1V.

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Typical Performance Characteristics — LDO T_A= 25°C unless otherwise noted

Output Voltage Change vs Temperature (LDO1)

V_IN= 3.6V, V_OUT= 2.6V, 100mA load

Output Voltage Change vs Temperature (LDO2)

V_IN= 3.6V, V_OUT= 3.3V, 100mA load

30017835

30017836

Load Transient (LDO1)

3.6 V_IN, 2.6V_OUT, 0 – 150 mA load

Load Transient (LDO2)

3.6 V_IN, 3.3 V_OUT, 0 – 150mA load

30017837

30017838

Line Transient (LDO1)

3.6 - 4.2 V_IN, 2.6 V_OUT, 300mA load

Line Transient (LDO2)

3 – 4.2 V_IN, 3.3V_OUT, 300 mA load

30017839

30017840

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Enable Start-up time (LDO1) )

0-3.6 V_IN, 2.6 V_OUT, 1mA load

Enable Start-up time (LDO2)

0 – 3.6 V_IN, 3.3 V_OUT, 1 mA load

30017841

30017842

LDO Maximum Load

V_IN= 1.74V

30017867

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Typical Performance Characteristics — Bucks

V_IN= 2.8V to 5.5V, T_A= 25°C

Shutdown Current vs. Temp

Output Voltage vs. Supply Voltage

(V_OUT= 1.0 V)

30017843

30017844

Output Voltage vs. Supply Voltage

(V_OUT= 1.8V)

Output Voltage vs. Supply Voltage

(V_OUT= 3.5V)

30017845

30017846

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Typical Performance Characteristics — Buck1

V_IN= 2.8V to 5.5V, T_A= 25°C, V_OUT= 1.2V, 2.0V

Efficiency vs Output Current

(V_OUT=1.2V, L= 2.2µH —(Forced PWM mode)

Efficiency vs Output Current

(V_OUT=2.0V, L= 2.2µH — Forced PWM mode)

30017847

30017848

Efficiency vs Output Current

(V_OUT=1.2V, L= 2.2µH — PWM mode to PFM mode)

Efficiency vs Output Current

(V_OUT=2.0V, L= 2.2µH — PWM mode to PFM mode)

30017850

30017849

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Typical Performance Characteristics — Buck2

V_IN= 4.5V to 5.5V, T_A= 25°C, V_OUT= 1.8V, 3.3V

Efficiency vs Output Current

( V_OUT=1.8V, L= 2.2µH —Forced PWM mode)

Efficiency vs Output Current

(V_OUT=3.3V, L= 2.2µH — Forced PWM mode)

30017851

30017852

Typical Performance Characteristics — Buck2

V_IN= 4.3V to 5.5V, T_A= 25°C, V_OUT= 1.8V, 3.3V

Efficiency vs Output Current

(V_OUT=1.2V, L= 2.2µH — PWM mode to PFM mode)

Efficiency vs Output Current

(V_OUT=2.0V, L= 2.2µH — PWM mode to PFM mode)

30017853

30017854

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Typical Performance Characteristics — Bucks

V_IN= 3.6V, T_A= 25°C, V_OUT= 1.2V unless otherwise noted

Load Transient Response

V_OUT= 1.2V, I_LOAD= 300–500mA (PWM Mode)

Mode Change by Load Transient

V_OUT= 1.2V, I_LOAD= 50–150mA (PFM to PWM Mode)

30017856

30017857

Line Transient Response

V_IN= 3.6 – 4.2V, V_OUT= 1.2V, 250mA load

Line Transient Response

V_IN= 3.6 – 4.2V, V_OUT= 3.3V, 250 mA load

30017858

30017859

Start up into PWM Mode

V_OUT= 1.2V, 1.0A load

Start up into PWM Mode

V_OUT= 3.3 V, 600mA load

30017860

30017861

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Start up into PFM Mode

V_OUT= 1.2V, 30mA load

Start up into PFM Mode

V_OUT= 3.3V, 30mA load

30017880

30017862

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DC/DC Converters

OVERVIEW

The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2)

and two Buck converters (SW1 and SW2). The table hereunder lists the output characteristics of the various regulators.

Supply Specification

Output

I_MAX

Supply

Load

V_OUTRange(V)

Resolution (mV)

Maximum Output

Current (mA)

LDO1

LDO2

SW1

analog

digital

1.0 to 3.5

0.8 to 2.0

1.0 to 3.5

100

50

300

1000

600

SW2

100

*For default values of the regulators, please consult page 3 of this datasheet.

LINEAR LOW DROPOUT REGULATORS (LDOS)

voltages of both LDOs are register programmable. The de-

fault output voltages are factory programmed during Final

Test, which can be tailored to the specific needs of the system

designer.

LDO1 and LDO2 are identical linear regulators targeting ana-

log loads characterized by low noise requirements. LDO1 and

LDO2 are enabled through the ENLDO pin or through the

corresponding LDO1 or LDO2 control register. The output

30017822

NO-LOAD STABILITY

grammable in steps of 100mV from 1.0V to 3.5V by program-

ming bits D4-0 in the LDO Control registers. Both LDO1 and

LDO2 are enabled by applying a logic 1 to the ENLDO1 and

ENLDO2 pin. Enable/disable control is also provided through

enable bit of the LDO1 and LDO2 control registers. The value

of the enable LDO bit in the register is logic 1 by default. The

output voltage can be altered while the LDO is enabled.

The LDOs will remain stable and in regulation with no external

load. This is an important consideration in some circuits, for

example, CMOS RAM keep-alive applications.

LDO1 AND LDO2 CONTROL REGISTERS

LDO1 and LDO2 can be configured by means of the LDO1

and LDO2 control registers. The output voltage is pro-

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INTERNAL SYNCHRONOUS RECTIFICATION

SW1, SW2: Synchronous Step-

Down Magnetic DC/DC Converters

While in PWM mode, the buck uses an internal NFET as a

synchronous rectifier to reduce rectifier forward voltage drop

and associated power loss. Synchronous rectification pro-

vides a significant improvement in efficiency whenever the

output voltage is relatively low compared to the voltage drop

across an ordinary rectifier diode.

FUNCTIONAL DESCRIPTION

The LP3907 incorporates two high-efficiency synchronous

switching buck regulators, SW1 and SW2, that deliver a con-

stant voltage from a single Li-Ion battery to the portable

system processors. Using a voltage mode architecture with

synchronous rectification, both bucks have the ability to de-

liver up to 1000mA and 600mA, respectively, depending on

the input voltage and output voltage (voltage head room), and

the inductor chosen (maximum current capability).

CURRENT LIMITING

A current limit feature allows the converter to protect itself and

external components during overload conditions. PWM mode

implements current limiting using an internal comparator that

trips at 1.5A for Buck1 and at 1.0A for Buck2 (typ). If the output

is shorted to ground the device enters a timed current limit

mode where the NFET is turned on for a longer duration until

the inductor current falls below a low threshold, ensuring in-

ductor current has more time to decay, thereby preventing

runaway.

There are three modes of operation depending on the current

required - PWM, PFM, and shutdown. PWM mode handles

current loads of approximately 70mA or higher, delivering

voltage precision of +/-3% with 90% efficiency or better.

Lighter output current loads cause the device to automatically

switch into PFM for reduced current consumption (I_Q= 15µA

typ.) and a longer battery life. The Standby operating mode

turns off the device, offering the lowest current consumption.

PWM or PFM mode is selected automatically or PWM mode

can be forced through the setting of the buck control register.

PFM OPERATION

At very light loads, the converter enters PFM mode and op-

erates with reduced switching frequency and supply current

to maintain high efficiency.

The part will automatically transition into PFM mode when ei-

ther of two conditions occurs for a duration of 32 or more clock

cycles:

Both SW1 and SW2 can operate up to a 100% duty cycle

(PMOS switch always on) for low drop out control of the output

voltage. In this way the output voltage will be controlled down

to the lowest possible input voltage.

A. The inductor current becomes discontinuous

or

Additional features include soft-start, under-voltage lock-out,

current overload protection, and thermal overload protection.

B. The peak PMOS switch current drops below the I_MODE

level

CIRCUIT OPERATION DESCRIPTION

A buck converter contains a control block, a switching PFET

connected between input and output, a synchronous rectify-

ing NFET connected between the output and ground

(BCKGND pin) and a feedback path. During the first portion

of each switching cycle, the control block turns on the internal

PFET switch. This allows current to flow from the input

through the inductor to the output filter capacitor and load. The

inductor limits the current to a ramp with a slope of

During PFM operation, the converter positions the output volt-

age slightly higher than the nominal output voltage during

PWM operation, allowing additional headroom for voltage

drop during a load transient from light to heavy load. The PFM

comparators sense the output voltage via the feedback pin

and control the switching of the output FETs such that the

output voltage ramps between 0.8% and 1.6% (typical) above

the nominal PWM output voltage. If the output voltage is be-

low the ‘high’ PFM comparator threshold, the PMOS power

switch is turned on. It remains on until the output voltage ex-

ceeds the ‘high’ PFM threshold or the peak current exceeds

the I_PFMlevel set for PFM mode. The typical peak current in

PFM mode is:

by storing energy in a magnetic field. During the second por-

tion of each cycle, the control block turns the PFET switch off,

blocking current flow from the input, and then turns the NFET

synchronous rectifier on. The inductor draws current from

ground through the NFET to the output filter capacitor and

load, which ramps the inductor current down with a slope of

Once the PMOS power switch is turned off, the NMOS power

switch is turned on until the inductor current ramps to zero.

When the NMOS zero-current condition is detected, the

NMOS power switch is turned off. If the output voltage is be-

low the ‘high’ PFM comparator threshold (see figure below),

the PMOS switch is again turned on and the cycle is repeated

until the output reaches the desired level. Once the output

reaches the ‘high’ PFM threshold, the NMOS switch is turned

on briefly to ramp the inductor current to zero and then both

output switches are turned off and the part enters an ex-

tremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30µA, which allows the part to

achieve high efficiencies under extremely light load condi-

The output filter stores charge when the inductor current is

high, and releases it when low, smoothing the voltage across

the load.

PWM OPERATION

During PWM operation the converter operates as a voltage-

mode controller with input voltage feed forward. This allows

the converter to achieve excellent load and line regulation.

The DC gain of the power stage is proportional to the input

voltage. To eliminate this dependence, feed forward voltage

inversely proportional to the input voltage is introduced.

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18

tions. When the output drops below the ‘low’ PFM threshold,

the cycle repeats to restore the output voltage to ~1.6% above

the nominal PWM output voltage.

Power On Sequence). The SW1 and SW2 output voltages

revert to default values when the power on sequence has

been completed. The default output voltage for each buck

converter is factory programmable. (See Application Notes).

If the load current should increase during PFM mode (see

figure below) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into

fixed-frequency PWM mode.

SW1, SW2 CONTROL REGISTERS

SW1, SW2 can be enabled/disabled through the correspond-

ing control register.

SW1, SW2 OPERATION

The Modulation mode PWM/PFM is by default automatic and

depends on the load as described above in the functional de-

scription. The modulation mode can be overridden by setting

I²C bit to a logic 1 in the corresponding buck control register,

forcing the buck to operate in PWM mode regardless of the

load condition.

SW1 and SW2 have selectable output voltages ranging from

0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3907 are

I²C register controlled and are enabled by default through the

internal state machine of the LP3907 following a Power-On

event that moves the operating mode to the Active state. (see

30017814

SHUTDOWN MODE

down to the lowest possible input voltage. When the device

operates near 100% duty cycle, output voltage ripple is ap-

proximately 25mV. The minimum input voltage needed to

support the output voltage is

During shutdown the PFET switch, reference, control and

bias circuitry of the converters are turned off. The NFET

switch will be on in shutdown to discharge the output. When

the converter is enabled, soft start is activated. It is recom-

mended to disable the converter during the system power up

and under voltage conditions when the supply is less than

2.8V.

V_{IN, MIN}= I_LOAD* (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT

I_LOAD

Load current

—

R_{DSON, PFET}

Drain to source resistance of

PFET switch in the triode region

Inductor resistance

SOFT START

R_INDUCTOR

—

The soft-start feature allows the power converter to gradually

reach the initial steady state operating point, thus reducing

start-up stresses and surges. The two LP3907 buck convert-

ers have a soft-start circuit that limits in-rush current during

start-up. During start-up the switch current limit is increased

in steps. Soft start is activated only if EN goes from logic low

to logic high after V_INreaches 2.8V. Soft start is implemented

by increasing switch current limit in steps of 180mA, 300mA,

and 720mA for Buck1; 161mA, 300mA and 536mA for Buck2

(typ. Switch current limit). The start-up time thereby depends

on the output capacitor and load current demanded at start-

up.

LOW DROPOUT OPERATION

The LP3907 can operate at 100% duty cycle (no switching;

PMOS switch completely on) for low drop out support of the

output voltage. In this way the output voltage will be controlled

19

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FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER

SUPPLIES

user wishes to use the preset timing sequence to power on

the regulators, transition the EN_T pin from Low to High. Oth-

erwise, simply tie the enables of each specific regulator HIGH

to turn on automatically.

The LP3907 provides several options for power on sequenc-

ing. The two bucks can be individually controlled with ENSW1

and ENSW2. The two LDOs can also be individually con-

trolled with ENLDO1 and ENLDO2.

EN_T is edge triggered with rising edge signaling the chip to

power on. The EN_T input is deglitched and the default is set

at 1ms. As shown in the next 2 diagrams, a rising EN_T edge

will start a power on sequence, while a falling EN_T edge will

start a shutdown sequence. If EN_T is high, toggling the ex-

ternal enables of the regulators will have no effect on the chip.

If the user desires a set power on sequence, he can program

the chip through I²C and raise EN_T from LOW to HIGH to

activate the power on sequencing.

POWER UP SEQUENCING USING THE EN_T FUNCTION

The regulators can also be programmed through I²C to turn

on and off. By default, I²C enables for the regulators on ON.

EN_T assertion causes the LP3907 to emerge from Standby

mode to Full Operation mode at a preset timing sequence. By

default, the enables for the LDOs and Bucks (ENLDO1, ENL-

DO2, EN_T, ENSW1, ENSW2) are 500K internally pulled

down, which causes the part to stay OFF until enabled. If the

The regulators are on following the pattern below:

Regulators on = (I²C enable) AND (External pin enable OR

EN_T high).

30017809

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20

LP3907 Default Power-Up Sequence

30017810

Power-On Timing Specification

Symbol

t₁

Description

Min

Typ

1.5

2

Max

Units

Programmable Delay from EN_T assertion to V_CC_Buck1 On

Programmable Delay from EN_T assertion to V_CC_Buck2 On

Programmable Delay from EN_T assertion to V_CC_LDO1 On

Programmable Delay from EN_T assertion to V_CC_LDO2 On

ms

t₂

t₃

t₄

3

6

The LP3907 default Power on delays can be reprogrammed at final test or I²C to 1, 1.5, 2, 3, 6, or 11ms.

Note:

21

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LP3907 Default Power-Off Sequence

30017811

Symbol

Description

Min

Typ

1.5

2

Max

Units

ms

t₁

t₂

t₃

t₄

Programmable Delay from EN_T deassertion to V_CC_Buck1 Off

Programmable Delay from EN_T deassertion to V_CC_Buck2 Off

Programmable Delay from EN_T deassertion to V_CC_LDO1 Off

Programmable Delay from EN_T deassertion to V_CC_LDO2 Off

ms

3

ms

6

ms

Note:

The LP3907 default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10ms. Default setting is the same as the on sequence.

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22

is logic LOW when either of the buck outputs are below 91%

of the rising value , or when one or both outputs fall below

82% of the desired value. The time delay between output

voltage level and nPOR is enabled is (50µs, 50ms, 100ms,

200ms) 50ms by default. The system designer can choose

the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.

Flexible Power-On Reset (i.e., Power

Good with delay)

The LP3907 is equipped with an internal Power-On-Reset

(“POR”) circuit which monitors the output voltage levels on

bucks 1 and 2. The nPOR is an open drain logic output which

NPOR With Counter Delay

30017821

The above diagram shows the simplest application of the

Power On Reset, where both switcher enables are tied to-

gether. In Case 1, EN1 causes nPOR to transition LOW and

triggers the nPOR delay counter. If the power supply for

Buck2 does not come on within that period, nPOR will stay

LOW, indicating a power fail mode. Case 2 indicates the vice

versa scenario if Buck1 supply did not come on. In both cases

the nPOR remains LOW.

Case 3 shows a typical application of the Power On Reset,

where both switcher enables are tied together. Even if RDY1

ramps up slightly faster than RDY2 (or vice versa), then nPOR

signal will trigger a programmable delay before going HIGH,

as explained below.

23

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Faults Occurring in Counter Delay After Startup

30017881

The above timing diagram details the Power good with delay

with respect to the enable signals EN1, and EN2. The RDY1,

RDY2 are internal signals derived from the output of two com-

parators. Each comparator has been trimmed as follows:

If EN1 and RDY1 signals are High at time t1, then the RDY1

signal rising edge triggers the programmable delay counter

(50μs, 50ms, 100ms, 200ms). This delay forces nPOR LOW

between time interval t1 and t2. nPOR is then pulled high after

the programmable delay is completed. Now if EN2 and RDY2

are initiated during this interval the nPOR signal ignores this

event.

Comparator Level

Buck Supply Level

Greater than 94%

Less than 85%

HIGH

LOW

If either RDY1or RDY2 were to go LOW at t3 then the pro-

grammable delay is triggered again.

The circuits for EN1 and RDY1 is symmetrical to EN2 and

RDY2, so each reference to EN1 and RDY1 will also work for

EN2 and RDY2 and vice versa.

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24

NPOR Mask Window

30017813

If the EN1 and RDY1 are initiated in normal operation, then

nPOR is asserted and deasserted as explained above.

In Case 2, we see the case where EN2 is initiated after the

RDY1 triggered programmable delay, but RDY2 never goes

HIGH (Buck2 never turns on). Normal operation operation of

nPOR occurs wilth respect to EN1 and RDY1, and the nPOR

signal is held HIGH for the duration of the mask window. We

see that nPOR goes LOW after the masking window has

timed out because it is now dependent on RDY1 and RDY2,

where RDY2 is LOW.

In Case 1, we see that case where EN2 and RDY2 are initi-

ated after triggered programmable delay. To prevent the

nPOR being asserted again, a masked window ( 5ms )

counter delay is triggered off the EN2 rising edge. nPOR is

still held HIGH for the duration of the mask, whereupon the

nPOR status afterwards will depend on the status of both

RDY1 and RDY2 lines.

25

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Design Implementation of the Flexible Power-On Reset

30017812

An internal Power-on reset of the IC is used with EN1, and

EN2 to produce a reset signal (LOW) to the delay timer nPOR.

EN1 and RDY1 or EN2 and RDY2 are used to generate the

set signal (HIGH) to the delay timer. S=R=1 never occurs. The

mask timers are triggered off EN1 and EN2 which are gated

with RDY1, and RDY2 to generate outputs to the final AND

gate to generate the nPOR.

four voltage regulators whenever this supply voltage is less

than 2.8VDC.

The circuit incorporates a bandgap based circuit that estab-

lishes the reference used to determine the 2.8VDC trip point

for a V_INOK – Not OK detector. This V_INOK signal is then

used to gate the enable signals to the four regulators of the

LP3907. When VINLDO12 is greater than 2.8VDC the four

enables control the four regulators, when VINLDO12 is less

than 2.8VDC the four regulators are disabled by the V_INde-

tector being in the “Not OK” state. The circuit has built in

hysteresis to prevent chattering occurring.

Under Voltage Lock Out

The LP3907 features an “under voltage lock out circuit”. The

function of this circuit is to continuously monitor the raw input

supply voltage (VINLDO12) and automatically disables the

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26

Signal timing specifications are according to the I²C bus spec-

ification. The maximum bit rate is 400kbit/s. See I²C specifi-

cation from Philips for further details.

I²C Compatible Serial Interface

I²C SIGNALS

The LP3907 features an I²C compatible serial interface, using

two dedicated pins: SCL and SDA for I²C clock and data re-

spectively. Both signals need a pull-up resistor according to

the I²C specification. The LP3907 interface is an I²C slave that

is clocked by the incoming SCL clock.

I²C DATA VALIDITY

The data on the SDA line must be stable during the HIGH

period of the clock signal (SCL), e.g.- the state of the data line

can only be changed when CLK is LOW.

30017816

I²C Signals: Data Validity

to HIGH while the SCL is HIGH. The ²C master always gen-

erates START and STOP bits. The I2C bus is considered to

be busy after START condition and free after STOP condition.

During data transmission, I²C master can generate repeated

START conditions. First START and repeated START condi-

tions are equivalent, function-wise.

I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of

the I²C session. START condition is defined as the SDA signal

transitioning from HIGH to LOW while the SCL line is HIGH.

STOP condition is defined as the SDA transitioning from LOW

30017817

START and STOP Conditions

27

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TRANSFERRING DATA

After the START condition, the I²C master sends a chip ad-

dress. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). Please note that ac-

cording to industry I²C standards for 7-bit addresses, the MSB

of an 8-bit address is removed, and communication actually

starts with the 7th most significant bit. For the eighth bit (LSB),

a “0” indicates a WRITE and a “1” indicates a READ. The

second byte selects the register to which the data will be writ-

ten. The third byte contains data to write to the selected

register.

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. Each

byte of data has to be followed by an acknowledge bit. The

acknowledged related clock pulse is generated by the master.

The transmitter releases the SDA line (HIGH) during the ac-

knowledge clock pulse. The receiver must pull down the SDA

line during the 9th clock pulse, signifying acknowledgement.

A receiver which has been addressed must generate an ac-

knowledgement (“ACK”) after each byte has been received.

The LP3907 has factory-programmed I²C addresses. The

LLP chip has a chip address of 60'h, while the micro SMD chip

has a chip address of 61'h.

30017818

I²C Chip Address (see note above)

30017819

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3907 LLP chip address: 0x60; micro SMD chip address: 0x61

I²C Write Cycle

When a READ function is to be accomplished, a WRITE func-

tion must precede the READ function, as shown in the Read

Cycle waveform.

30017824

I²C Read Cycle

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28

LP3907 Control Registers

Register

Address

Register

Name

Read/

Write

Register Description

0x02

0x07

0x10

0x11

0x20

0x23

0x24

0x25

0x29

0x2A

0x2B

0x38

0x39

0x3A

ICRA

SCR1

R

Interrupt Status Register A

System Control 1 Register

R/W

R

BKLDOEN

BKLDOSR

VCCR

Buck and LDO Output Voltage Enable Register

Buck and LDO Output Voltage Status Register

Voltage Change Control Register 1

Buck1 Target Voltage 1 Register

Buck1 Target Voltage 2 Register

Buck1 Ramp Control

R/W

B1TV1

B1TV2

B1RC

B2TV1

Buck2 Target Voltage 1 Register

Buck2 Target Voltage 2 Register

Buck2 Ramp Control

B2TV2

B2RC

BFCR

Buck Function Register

LDO1VCR

LDO2VCR

LDO1 Voltage control Registers

LDO2 Voltage control Registers

INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the System Engineer of the temperature status of the chip.

D7-2

—

D1

D0

Name

Access

Data

Temp 125°C

R

—

Reserved

Status bit for thermal warning

PMIC T>125°C

Reserved

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reset

0

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode for

the bucks, and also to select between an internal and external clock for the bucks.

D7

—

D6-4

D3

—

D2

D1

D0

Name

Access

Data

EN_DLY

R/W

FPWM2

R/W

FPWM1

R/W

ECEN

R/W

Reserved Selects the preset

delay sequence

Reserved Buck2 PWM /PFM

Mode select

Buck 1 PWM /PFM

Mode select

Reserved

from EN_T assertion

(shown below)

0 – Auto Switch PFM - 0 – Auto Switch PFM -

PWM operation PWM operation

1 – PWM Mode Only 1 – PWM Mode Only

Reset

0

010

1

0

29

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EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0>

Buck1

Buck2

LDO1

LDO2

000

001

010

011

100

101

110

111

1

1.5

2

1

2

3

1

3

2

1

6

1

2

1.5

3

6

2

1

2

6

1.5

2

1.5

11

2

3

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

D7

D6

D5

D4

D3

D2

D1

D0

Name

Access

Data

LDO2EN

R/W

LDO1EN

R/W

BK2EN

R/W

BK1EN

R/W

—

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

0

1

0

1

0

1

BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7

D6

D5

D4

D3

—

D2

D1

—

D0

Name

Access

Data

BKS_OK

R

LDOS_OK

R

LDO2_OK

R

LDO1_OK

R

BK2_OK

R

BK1_OK

R

0 – Buck 1-2

Not Valid

1 – Bucks

Valid

0 – LDO 1-2

Not Valid

1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid

0 – LDO2 Not 0 – LDO1 Not Reserve 0 – Buck2 Not Reserve 0 – Buck1 Not

Valid

d

Valid

d

Valid

1 – Buck2

Valid

1 – Buck1

Valid

Reset

0

BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20

This register selects and controls the output target voltages for the buck regulators.

D7-6

—

D5

D4

D3-2

—

D1

D0

Name

Access

Data

B2VS

R/W

B2GO

R/W

B1VS

R/W

B1GO

R/W

—

Reserved

Buck2 Target Voltage Buck2 Voltage Ramp Reserved

Buck1 Target Voltage Buck1 Voltage Ramp

Select

CTRL

Select

CTRL

0 – B2VT1

1 – B2VT2

0 – Hold

1 – Ramp to B2VS

selection

0 – B1VT1

1 – B1VT2

0 – Hold

1 – Ramp to B1VS

selection

Reset

00

0

00

0

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30

BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23

BUCK1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24

This register allows the user to program the output target volt-

age of Buck1.

This register allows the user to program the output target volt-

age of Buck1.

D7-5

—

D4-0

BK1_VOUT1

D7-5

—

D4-0

BK1_VOUT2

Name

Access

Data

Name

Access

Data

R/W

—

Reserved

Buck1 Output Voltage (V)

Reserved

Buck1 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

01001

Reset

000

01001

* If using Ext Ctrl, contact National Sales for support.

31

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BUCK1 RAMP CONTROL REGISTER (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

D7

- - - -

D6-4

- - - -

D3-0

B1RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

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32

BUCK2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29

BUCK2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A

This register allows the user to program the output target volt-

age of Buck2.

This register allows the user to program the output target volt-

age of Buck2.

D7-5

—

D4-0

BK2_VOUT1

D7-5

—

D4-0

BK2_VOUT2

Name

Access

Data

Name

Access

Data

R/W

—

Reserved

Buck2 Output Voltage (V)

Reserved

Buck2 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

01001

Reset

000

01001

*If using Ext Ctrl, contact National Sales for support.

33

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BUCK2 RAMP CONTROL REGISTER (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

D7

- - - -

D6-4

- - - -

D3-0

B2RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

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34

BUCK FUNCTION REGISTER (BFCR) – 0x38

netic Interference (EMI). The spread spectrum modulation

frequency refers to the rate at which the frequency ramps up

and down, centered at 2MHz.

This register allows the Buck switcher clock frequency to be

spread across a wider range, allowing for less Electro-mag-

30017825

This register also allows dynamic scaling of the nPOR Delay

Timing. The LP3907 is equipped with an internal Power-On-

Reset (“POR”) circuit which monitors the output voltage levels

on the buck regulators, allowing the user to more actively

monitor the power status of the chip.

is less than 2.8VDC. This prevents the user from damaging

the power source (i.e. battery), but can be disabled if the user

wishes.

Note that if the supply to VDD_M is close to 2.8V with a heavy

load current on the regulators, the chip is in danger of pow-

ering down due to UVLO. If the user wishes to keep the chip

active under those conditions, enable the “Bypass UVLO”

feature.

The Under Voltage Lock-Out feature continuously monitor the

raw input supply voltage (VINLDO12) and automatically dis-

ables the four voltage regulators whenever this supply voltage

D7-2

—

D4

BP_UVLO

D3

D1

BK_SLOMOD

R/W

D0

Name

Access

Data

TPOR

R/w

BK_SSEN

R/W

—

Reserved

Bypass UVLO

monitoring

nPOR Delay Timing Buck Spread Spectrum

00 - 50µs

Spread Spectrum

Function Output

Modulation

0 - Allow UVLO

1 - Disable UVLO

01 - 50ms

10 - 100ms

11 - 200ms

0 – 10 kHz triangular wave 0 – Disabled

1 – 2 kHz triangular wave 1 – Enabled

Reset

000

0

01

1

0

35

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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39

LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A

This register allows the user to program the output target volt-

age of LDO 1.

This register allows the user to program the output target volt-

age of LDO 2.

D7-5

—

D4-0

LDO1_OUT

D7-5

—

D4-0

LDO2_OUT

Name

Access

Data

Name

Access

Data

R/W

—

Reserved

LDO1 Output voltage (V)

Reserved

LDO2 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

01111

Reset

000

10111

www.national.com

36

External Capacitors

Application Notes

The regulators on the LP3907 require external capacitors for

regulator stability. These are specifically designed for

portable applications requiring minimum board space and

smallest components. These capacitors must be correctly se-

lected for good performance.

ANALOG POWER SIGNAL ROUTING

All power inputs should be tied to the main VDD source (i.e.

battery), unless the user wishes to power it from another

source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error am-

plifiers, so they should be tied to the main VDD. The analog

VDD inputs must have an input voltage between 2.8 and 5.5V,

as specified in the Electrical Characteristics Section in the

front of the datasheet.

LDO CAPACITOR SELECTION

Input Capacitor

An input capacitor is required for stability. It is recommended

that a 1.0μF capacitor be connected between the LDO input

pin and ground (this capacitance value may be increased

without limit).

The other V_INs (V_INLDO1, V_INLDO2, V_IN1, V_IN2) can actually

have inputs lower than 2.8V, as long as it's higher than the

programmed output (+0.3V, to be safe).

This capacitor must be located a distance of not more than

1cm from the input pin and returned to a clean analog ground.

Any good quality ceramic, tantalum, or film capacitor may be

used at the input.

The analog and digital grounds should be tied together out-

side of the chip to reduce noise coupling.

COMPONENT SELECTION

Inductors for SW1 and SW2

Important: Tantalum capacitors can suffer catastrophic fail-

ures due to surge currents when connected to a low

impedance source of power (like a battery or a very large ca-

pacitor). If a tantalum capacitor is used at the input, it must be

guaranteed by the manufacturer to have a surge current rat-

ing sufficient for the application.

There are two main considerations when choosing an induc-

tor; the inductor should not saturate and the inductor current

ripple is small enough to achieve the desired output voltage

ripple. Care should be taken when reviewing the different sat-

uration current ratings that are specified by different manu-

facturers. Saturation current ratings are typically specified at

25ºC, so ratings at maximum ambient temperature of the ap-

plication should be requested from the manufacturer.

There are no requirements for the ESR (Equivalent Series

Resistance) on the input capacitor, but tolerance and tem-

perature coefficient must be considered when selecting the

capacitor to ensure the capacitance will remain approximately

1.0μF over the entire operating temperature range.

There are two methods to choose the inductor saturation cur-

rent rating:

Output Capacitor

The LDOs on the LP3907 are designed specifically to work

with very small ceramic output capacitors. A 0.47µF ceramic

capacitor (temperature types Z5U, Y5V or X7R) with ESR be-

tween 5 mΩ to 500 mΩ, is suitable in the application circuit.

It is also possible to use tantalum or film capacitors at the

device output, C_OUT(or V_OUT), but these are not as attractive

for reasons of size and cost.

Method 1:

The saturation current is greater than the sum of the maxi-

mum load current and the worst case average to peak induc-

tor current. This can be written as follows:

The output capacitor must meet the requirement for the min-

imum value of capacitance and also have an ESR value that

is within the range 5 mΩ to 500 mΩ for stability.

Capacitor Characteristics

I_RIPPLE

I_OUTMAX

V_IN:

:

Average to peak inductor current

Maximum load current

The LDOs are designed to work with ceramic capacitors on

the output to take advantage of the benefits they offer. For

capacitance values in the range of 0.47µF to 4.7µF, ceramic

capacitors are the smallest, least expensive and have the

lowest ESR values, thus making them best for eliminating

high frequency noise. The ESR of a typical 1.0µF ceramic

capacitor is in the range of 20mΩ to 40mΩ, which easily

meets the ESR requirement for stability for the LDOs.

:

Maximum input voltage to the buck

L:

Min inductor value including worse case tolerances

(30% drop can be considered for method 1)

f:

Minimum switching frequency (1.6 MHz)

Buck Output voltage

V_OUT

:

For both input and output capacitors, careful interpretation of

the capacitor specification is required to ensure correct device

operation. The capacitor value can change greatly, depend-

ing on the operating conditions and capacitor type.

Method 2:

A more conservative and recommended approach is to

choose an inductor that has saturation current rating greater

than the maximum current limit of 1250mA for Buck1 and

1750mA for Buck2.

In particular, the output capacitor selection should take ac-

count of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance

can vary with DC bias conditions as well as temperature and

frequency of operation. Capacitor values will also show some

decrease over time due to aging. The capacitor parameters

are also dependent on the particular case size, with smaller

sizes giving poorer performance figures in general. As an ex-

ample, below is typical graph comparing different capacitor

case sizes in a Capacitance vs. DC Bias plot.

Given a peak-to-peak current ripple (I_PP) the inductor needs

to be at least

Inductor Value Unit Description

L_SW1,2 2.2 µH SW1,2 inductor

Notes

D.C.R. 70mΩ

37

www.national.com

switch of the dc/dc converter in the first half of each cycle and

reduces voltage ripple imposed on the input power source. A

ceramic capacitor’s low ESR (Equivalent Series Resistance)

provides the best noise filtering of the input voltage spikes due

to fast current transients. A capacitor with sufficient ripple

current rating should be selected. The Input current ripple can

be calculated as:

The worse case is when V_IN= 2V_OUT

.

30017828

Graph Showing a Typical Variation in Capacitance vs. DC

Bias

Output Capacitor Selection for SW1, SW2

A 10μF, 6.3V ceramic capacitor should be used on the output

of the sw1 and sw2 magnetic dc/dc converters. The output

capacitor needs to be mounted as close as possible to the

output of the device. A large value may be used for improved

input voltage filtering. The recommended capacitor types are

X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered

when selecting case sizes like 0805 and 0603. DC bias char-

acteristics vary from manufacturer to manufacturer and DC

bias curves should be requested from them and analyzed as

part of the capacitor selection process.

As shown in the graph, increasing the DC Bias condition can

result in the capacitance value that falls below the minimum

value given in the recommended capacitor specifications ta-

ble. Note that the graph shows the capacitance out of spec

for the 0402 case size capacitor at higher bias voltages. It is

therefore recommended that the capacitor manufacturers'

specifications for the nominal value capacitor are consulted

for all conditions, as some capacitor sizes (e.g. 0402) may not

be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with tempera-

ture. The capacitor type X7R, which operates over a temper-

ature range of −55°C to +125°C, will only vary the capacitance

to within ±15%. The capacitor type X5R has a similar toler-

ance over a reduced temperature range of −55°C to +85°C.

Many large value ceramic capacitors, larger than 1µF are

manufactured with Z5U or Y5V temperature characteristics.

Their capacitance can drop by more than 50% as the tem-

perature varies from 25°C to 85°C. Therefore X7R is recom-

mended over Z5U and Y5V in applications where the ambient

temperature will change significantly above or below 25°C.

The output filter capacitor of the magnetic dc/dc converter

smooths out current flow from the inductor to the load, helps

maintain a steady output voltage during transient load

changes and reduces output voltage ripple. These capacitors

must be selected with sufficient capacitance and sufficiently

low ESD to perform these functions.

The output voltage ripple is caused by the charging and dis-

charging of the output capacitor and also due to its ESR and

can be calculated as follows:

Tantalum capacitors are less desirable than ceramic for use

as output capacitors because they are more expensive when

comparing equivalent capacitance and voltage ratings in the

0.47µF to 4.7µF range.

Another important consideration is that tantalum capacitors

have higher ESR values than equivalent size ceramics. This

means that while it may be possible to find a tantalum capac-

itor with an ESR value within the stable range, it would have

to be larger in capacitance (which means bigger and more

costly) than a ceramic capacitor with the same ESR value. It

should also be noted that the ESR of a typical tantalum will

increase about 2:1 as the temperature goes from 25°C down

to −40°C, so some guard band must be allowed.

Voltage peak-to-peak ripple due to ESR can be expressed as

follows:

V_PP–ESR= 2 × I_RIPPLE× R_ESR

Because the V_PP-Cand V_PP-ESRare out of phase, the rms val-

ue can be used to get an approximate value of the peak-to-

peak ripple:

Input Capacitor Selection for SW1 and SW2

A ceramic input capacitor of 10µF, 6.3V is sufficient for the

magnetic dc/dc converters. Place the input capacitor as close

as possible to the input of the device. A large value may be

used for improved input voltage filtering. The recommended

capacitor types are X7R or X5R. Y5V type capacitors should

not be used. DC bias characteristics of ceramic capacitors

must be considered when selecting case sizes like 0805 and

0603. The input filter capacitor supplies current to the PFET

Note that the output voltage ripple is dependent on the induc-

tor current ripple and the equivalent series resistance of the

output capacitor (R_ESR). The R_ESRis frequency dependent as

well as temperature dependent. The R_ESRshould be calcu-

lated with the applicable switching frequency and ambient

temperature.

www.national.com

38

Capacitor

Min Value

0.47

Unit

µF

Description

LDO1 output capacitor

LDO2 output capacitor

SW1 output capacitor

SW2 output capacitor

Recommended Type

Ceramic, 6.3V, X5R

C_LDO1

C_LDO2

C_SW1

C_SW2

0.47

µF

Ceramic, 6.3V, X5R

10.0

µF

10.0

µF

I²C Pullup Resistor

JUNCTION TEMPERATURE

Both SDA and SCL terminals need to have pullup resistors

connected to VINLDO12 or to the power supply of the I²C

master. The values of the pull-up resistors (typ. ∼1.8kΩ) are

determined by the capacitance of the bus. Too large of a re-

sistor combined with a given bus capacitance will result in a

rise time that would violate the max. rise time specification. A

too small resistor will result in a contention with the pull-down

transistor on either slave(s) or master.

The maximum junction temperature T_J-MAX-OPof 125ºC of the

IC package.

The following equations demonstrate junction temperature

determination, ambient temperature T_A-MAXand Total chip

power must be controlled to keep T_Jbelow this maximum:

T

^J-MAX-OP= T_A-MAX+ (θ_JA) [ °C/ Watt] * (P_D-MAX) [Watts]

Total IC power dissipation P_D-MAXis the sum of the individual

power dissipation of the four regulators plus a minor amount

for chip overhead. Chip overhead is Bias, TSD & LDO analog.

Operation without I²C Interface

P

^D-MAX= P_LDO1+ P_LD02+ P_BUCK1+ P_BUCK2+ (0.0001A * V_IN)

Operation of the LP3907 without the I²C interface is possible

if the system can operate with default values for the LDO and

Buck regulators. (Read below: Factory programmable op-

tions). The I²C-less system must rely on the correct default

output values of the LDO and Buck converters.

[Watts].

Power dissipation of LDO1

P_LDO1= (V_INLDO1- V_OUTLDO1) * Iout_LDO1[V*A]

Power dissipation of LDO2

P_LDO2= (V_INLDO2- Vout_LDO2) * Iout_LDO2[V*A]

Power dissipation of Buck1

Factory Programmable Options

The following options are EPROM programmed during final

test of the LP3907. The system designer that needs specific

options is advised to contact the local National Semiconduc-

tor sales office.

P_Buck1= P_IN– P_OUT

=

Vout_Buck1* Iout_Buck1* (1 -η₁) / η₁[V*A]

η₁= efficiency of buck 1

Power dissipation of Buck2

Factory programmable

options

Current value

P_Buck2= P_IN– P_OUT

=

Enable delay for power on

code 010 (see Control 1

register section)

Vout_Buck2* Iout_Buck2* (1 - η₂) / η₂[V*A]

η₂= efficiency of Buck2

SW1 ramp speed

SW2 ramp speed

8 mV/µs

Where η is the efficiency for the specific condition taken from

efficiency graphs.

The I²C Chip ID address is offered as a metal mask option.

The current address for the LLP chip equals 0x60, while the

address for the micro SMD chip is 0x61.

HIGH V_INHIGH-LOAD OPERATION

Additional information is provided when the IC is operated at

extremes of V_INand regulator loads. These are described in

terms of the Junction temperature and, Buck output ripple

management.

39

www.national.com

derneath the thermal land. Based on thermal analysis of the

LLP package, the junction-to-ambient thermal resistance

(θJA) can be improved by a factor of two when the die attach

pad of the LLP package is soldered directly onto the PCB with

thermal land and thermal vias, as opposed to an alternative

with no direct soldering to a thermal land. Typical pitch and

outer diameter for thermal vias are 1.27mm and 0.33mm re-

spectively. Typical copper via barrel plating is 1oz, although

thicker copper may be used to further improve thermal per-

formance. The LP3907 die attach pad is connected to the

substrate of the IC and therefore, the thermal land and vias

on the PCB board need to be connected to ground (GND pin).

Thermal Performance of the LLP

Package

The LP3907 is a monolithic device with integrated power

FETs. For that reason, it is important to pay special attention

to the thermal impedance of the LLP package and to the PCB

layout rules in order to maximize power dissipation of the LLP

package.

The LLP package is designed for enhanced thermal perfor-

mance and features an exposed die attach pad at the bottom

center of the package that creates a direct path to the PCB

for maximum power dissipation. Compared to the traditional

leaded packages where the die attach pad is embedded in-

side the molding compound, the LLP reduces one layer in the

thermal path.

For more information on board layout techniques, refer to Ap-

plication Note AN–1187 “Leadless Lead frame Package

(LLP).” on http://www.national.com This application note also

discusses package handling, solder stencil and the assembly

process.

The thermal advantage of the LLP package is fully realized

only when the exposed die attach pad is soldered down to a

thermal land on the PCB board with thermal vias planted un-

www.national.com

40

Physical Dimensions inches (millimeters) unless otherwise noted

4 X 4 X 0.8 mm 24-Pin LLP Package

NS Package SQA24A

For ordering, refer to Ordering Information table

41

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2.5 X 2.5 mm 25-Bump micro SMD Package

NS Package TLA25AAA

For ordering, refer to Ordering Information table

X1 = 2492 ± 30 µm

X2 = 2492 ± 30 µm

X3 = 600 ± 75 µm

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42

Notes

43

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Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products

www.national.com/amplifiers

Design Support

Amplifiers

WEBENCH

www.national.com/webench

www.national.com/AU

Audio

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www.national.com/timing

www.national.com/adc

Analog University

App Notes

Clock Conditioners

Data Converters

Displays

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www.national.com/quality/green

www.national.com/packaging

Distributors

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www.national.com/ethernet

www.national.com/interface

www.national.com/lvds

Green Compliance

Packaging

Ethernet

Interface

Quality and Reliability www.national.com/quality

LVDS

Reference Designs

Feedback

www.national.com/refdesigns

www.national.com/feedback

Power Management

Switching Regulators

LDOs

www.national.com/power

www.national.com/switchers

www.national.com/ldo

LED Lighting

PowerWise

www.national.com/led

www.national.com/powerwise

Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors

Wireless (PLL/VCO)

www.national.com/tempsensors

www.national.com/wireless

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型号：	LP3907SQ-JIXI
厂家：	Intersil
描述：	Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface 双路高电流降压型DC / DC和双路线性稳压器，具有I2C兼容接口稳压器
文件：	总44页 (文件大小：3041K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP3907SQ-JIXI [INTERSIL]

相关型号：

LP3907SQ-JXQX

LP3907SQ-JXQX

LP3907SQ-JXQX/NOPB

LP3907SQ-PFX6W/NOPB

LP3907SQ-PJXIX/NOPB

LP3907SQ-PXPP

LP3907SQ-PXPP/NOPB

LP3907SQ-TJXIP/NOPB

LP3907SQX-JIXI

LP3907SQX-JXQX

LP3907SQX-JXQX

LP3907SQX-PXPP