X9241AYVI [INTERSIL]
Low Powr/2-Wire Serial Bus; 低POWR / 2线串行总线
| 型号： | X9241AYVI |
| 厂家： | 
Intersil |
| 描述： | Low Powr/2-Wire Serial Bus |
| 文件： | 总16页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9241A
®
Low Power/2-Wire Serial Bus
Data Sheet
September 15, 2005
FN8164.1
Quad Digitally Controlled Potentiometer
(XDCP™)
Features
• Four potentiometers in one package
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
• 2-wire serial interface
• Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per
potentiometer
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
• High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
• 16-bytes of nonvolatile memory
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 3 resistor array values
- 2kΩ to 50kΩ mask programmable
- Cascadable for values of 500Ω to 200kΩ
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
• Pb-free plus anneal available (RoHS compliant)
Block Diagram
V
V
CC
SS
V
R
/
H2
R0
R2
V
/R
H0 H0
R0
R2
R1
R3
R1
R3
Wiper
Counter
Register
H2
Wiper
Counter
Register
(WCR)
Register
Array
Pot 2
(WCR)
V
/R
L0 L0
V
V
/R
L2 L2
/R
V
/R
W2 W2
W0 W0
SCL
SDA
Interface
and
Control
Circuitry
A0
A1
A2
A3
8
Data
V
/R
H1 H1
V
/R
H3 H3
R0
R2
R1
R3
R0
R2
R1
R3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Register
Array
Pot 3
Register
Array
Pot 1
V
V
/R
L1 L1
V
V
/R
L3 L3
/R
W1 W1
/R
W3 W3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9241A
Ordering Information
POTENTIOMETER
ORGANIZATION
(K)
V
LIMITS
(V)
TEMP RANGE
(°C)
CC
PART NUMBER
X9241AMP
PART MARKING
PACKAGE
20 Ld PDIP
X9241AMP
X9241AMPZ
X9241AMPI
X9241AMPIZ
X9241AMS
X9241AMS Z
X9241AMSI
X9241AMSI Z
X9241AMV
X9241AMV Z
X9241AMVI
X9241AMVI Z
X9241AWP
5 ±10%
2/10/50
0 to 70
0 to 70
X9241AMPZ (Note)
X9241AMPI
20 Ld PDIP (Pb-free)
20 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X9241AMPIZ (Note)
X9241AMS*
20 Ld PDIP (Pb-free)
20 Ld SOIC
X9241AMSZ* (Note)
X9241AMSI*
0 to 70
20 Ld SOIC (Pb-free)
20 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X9241AMSIZ* (Note)
X9241AMV*
20 Ld SOIC (Pb-free)
20 Ld TSSOP
X9241AMVZ* (Note)
X9241AMVI*
0 to 70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
-40 to 85
-40 to 85
0 to 70
X9241AMVIZ* (Note)
X9241AWP
20 Ld TSSOP (Pb-free)
20 Ld PDIP
10
X9241AWPZ (Note)
X9241AWPI
0 to 70
20 Ld PDIP (Pb-free)
20 Ld PDIP
X9241AWPI
X9241AWPI Z
X9241AWS
X9241AWS Z
X9241AWSI
X9241AWSI Z
X9241AWV
X9241AWVZ
X9241AWVI
X9241AWVI Z
X9241AYP
-40 to 85
-40 to 85
0 to 70
X9241AWPIZ (Note)
X9241AWS*
20 Ld PDIP (Pb-free)
20 Ld SOIC
X9241AWSZ* (Note)
X9241AWSI*
0 to 70
20 Ld SOIC (Pb-free)
20 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X9241AWSIZ* (Note)
X9241AWV*
20 Ld SOIC (Pb-free)
20 Ld TSSOP
X9241AWVZ* (Note)
X9241AWVI*
0 to 70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
-40 to 85
-40 to 85
0 to 70
X9241AWVIZ* (Note)
X9241AYP
20 Ld TSSOP (Pb-free)
20 Ld PDIP
2
X9241AYPZ (Note)
X9241AYPI
X9241AYP Z
X9241AYPI
X9241AYPI Z
X9241AYS
0 to 70
20 Ld PDIP (Pb-free)
20 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X9241AYPIZ (Note)
X9241AYS*
20 Ld PDIP (Pb-free)
20 Ld SOIC
X9241AYSZ* (Note)
X9241AYSI*
X9241AYS Z
X9241AYSI
0 to 70
20 Ld SOIC (Pb-free)
20 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X9241AYSIZ* (Note)
X9241AYV*
20 Ld SOIC (Pb-free)
20 Ld TSSOP
X9241AYV
X9241AYVZ* (Note)
X9241AYVI*
X9241AYV Z
X9241AYVI
X9241AYVI Z
0 to 70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
-40 to 85
-40 to 85
X9241AYVIZ* (Note)
20 Ld TSSOP (Pb-free)
FN8164.1
September 15, 2005
2
X9241A
Ordering Information (Continued)
POTENTIOMETER
ORGANIZATION
(K)
V
LIMITS
(V)
TEMP RANGE
(°C)
CC
PART NUMBER
X9241AUP
PART MARKING
X9241AUP
PACKAGE
20 Ld PDIP
5 ±10%
50
0 to 70
0 to 70
X9241AUPZ (Note)
X9241AUPI
X9241AUP Z
X9241AUPI
X9241AUPI Z
X9241AUS
20 Ld PDIP (Pb-free)
20 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X9241AUPIZ (Note)
X9241AUS*
20 Ld PDIP (Pb-free)
20 Ld SOIC
X9241AUSZ* (Note)
X9241AUSI*
X9241AUS Z
X9241AUSI
X9241AUSI Z
X9241AUV
0 to 70
20 Ld SOIC (Pb-free)
20 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X9241AUSIZ* (Note)
X9241AUV*
20 Ld SOIC (Pb-free)
20 Ld TSSOP
X9241AUVZ* (Note)
X9241AUVI*
X9241AUV Z
X9241AUVI
X9241AUVI Z
0 to 70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP
-40 to 85
-40 to 85
X9241AUVIZ* (Note)
20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Descriptions
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9241A.
Pin Configuration
DIP/SOIC/TSSOP
V
/R
W0 W0
1
2
20
19
V
CC
/R
V
/R
L0 L0
V
W3 W3
V
/R
H0 H0
3
18
17
16
15
14
13
12
11
V
/R
L3 L3
A0
4
V
/R
Serial Data (SDA)
H3 H3
A2
5
A1
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
X9241A
V
/R
W1 W1
6
A3
V
/R
L1 L1
7
SCL
V
/R
8
V
/R
W2 W2
H1 H1
SDA
9
V
/R
L2 L2
V
/R
V
10
H2 H2
SS
Address
Pin Names
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9241A.
SYMBOL
SCL
DESCRIPTION
Serial Clock
Serial Data
Address
SDA
A0–A3
Potentiometer Pins
V
V
/R –V /R
,
Potentiometer Pins (terminal equivalent)
H0 H0 H3 H3
V /R (V /R —V /R ), V /R (V /R —V /R
)
/R –V /R
H
H
H0 H0 H3 H3 L0 L0 L3 L3
L
L
L0 L0 L3 L3
V
/R –V /R
Potentiometer Pins (wiper equivalent)
The R and R inputs are equivalent to the terminal
W0 W0 W3 W3
H
L
connections on either end of a mechanical potentiometer.
V
/R (V /R —V /R
)
W
W
W0 W0 W3 W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
FN8164.1
3
September 15, 2005
X9241A
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V /R )
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The six least significant bits
of the WCR are decoded to select, and enable, one of sixty-
four switches.
Principles of Operation
W
W
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9241A will be
considered a slave device in all applications.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1 below). For the X9241A this is fixed as 0101[B].
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
). SDA state changes during SCL HIGH
LOW
Device Type
Identifier
are reserved for indicating start and stop conditions.
Start Condition
0
1
0
1
A3
A2
A1
A0
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
). The X9241A continuously monitors the
Device Address
FIGURE 1. SLAVE ADDRESS
HIGH
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
The next four bits of the slave address are the device
address. The physical device address is defined by the state
of the A0-A3 inputs. The X9241A compares the serial data
stream with the address input state; a successful compare of
all four address bits is required for the X9241A to respond
with an acknowledge.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data. See Figure 7.
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9241A initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation no ACK will be
returned. If the X9241A has completed the write operation
an ACK will be returned and the master can then proceed
with the next operation.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9241A will
respond with a final acknowledge.
Array Description
The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V /R
H
H
and V /R inputs).
L
L
FN8164.1
4
September 15, 2005
X9241A
The four high order bits define the instruction. The next two
Flow 1. ACK Polling Sequence
bits (P1 and P0) select which one of the four potentiometers
is to be affected by the instruction. The last two bits (R1 and
R0) select one of the four registers that is to be acted upon
when a register oriented instruction is issued.
Nonvolatile Write
Command Completed
Enter ACK Polling
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure
3. These two-byte instructions exchange data between the
WCR and one of the data registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM. The
Issue
START
response of the wiper to this action will be delayed t
.
STPWV
Issue Slave
Address
A transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
Issue STOP
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all four of the potentiometers and
one of their associated registers.
No
ACK
Returned?
Yes
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
FurTher
OperaTion?
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
Instruction Structure
The next byte sent to the X9241A contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of four
pots and when applicable they point to one of four
For each SCL clock pulse (t
) while SDA is HIGH, the
HIGH
selected wiper will move one resistor segment towards the
V /R terminal. Similarly, for each SCL clock pulse while
H
H
SDA is LOW, the selected wiper will move one resistor
segment towards the V /R terminal. A detailed illustration
associated registers. The format is shown below in Figure 2.
L
L
of the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Potentiometer
Select
I3
I2
I1
I0
P1
P0
R1
R0
Instructions
Register
Select
FIGURE 2. INSTRUCTION BYTE FORMAT
FN8164.1
September 15, 2005
5
X9241A
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
S
T
O
P
A
C
K
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0 P1 P0 R1 R0
DW D5 D4 D3 D2
S
T
O
P
A
C
K
A
C
K
CM
D1 D0
A
C
K
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
X
X
A
C
K
S
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0 P1 P0 R1 R0
A
C
K
I
I
I
D
E
C
1
D
S
T
A
R
T
N
C
1
N
C
2
N
C
n
E
C
n
T
O
P
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
INC/DEC
CMD
ISSUED
t
CLWV
SCL
SDA
Voltage Out
V
/R
W
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
FN8164.1
September 15, 2005
6
X9241A
TABLE 1. INSTRUCTION SET
INSTRUCTION FORMAT
INSTRUCTION
Read WCR
I
I
I
I
P
P
R
R
0
OPERATION
Read the contents of the Wiper Counter Register pointed to by P - P
3
2
1
0
1
0
1
(10)
(11)
1
1
1
0
0
0
0
1
1
1
0
1
1/0
1/0
1/0
1/0
X
X
1
0
Write WCR
1/0
X
X
Write new value to the Wiper Counter Register pointed to by P - P
1 0
Read Data
Register
1/0
1/0
1/0
1/0
X
1/0
1/0
1/0
1/0
1/0
1/0 Read the contents of the Register pointed to by P - P and R - R
1 0 1 0
Write Data
Register
1
1
1
0
1
1
1
0
0
0
1
0
0
1
0
1
1/0
1/0
1/0
X
1/0 Write new value to the Register pointed to by P - P and R - R
1 0 1 0
XFR Data
Register to WCR
1/0 Transfer the contents of the Register pointed to by P - P and R - R
1 0 1
0
to its associated WCR
XFR WCR to
Data Register
1/0 Transfer the contents of the WCR pointed to by P - P to the Register
1
0
pointed to by R - R
1
0
Global XFR
Data Register to
WCR
1/0 Transfer the contents of the Data Registers pointed to by R - R of all
1 0
four pots to their respective WCR
Global XFR
WCR to Data
Register
1
0
0
0
0
1
0
0
X
X
1/0
X
1/0 Transfer the contents of all WCRs to their respective data Registers
pointed to by R - R of all four pots
1
0
Increment/
Decrement
Wiper
1/0
1/0
X
Enable Increment/decrement of the WCR pointed to by P - P
1 0
Notes: (10) 1/0 = data is one or zero
(11) X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical)
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8164.1
September 15, 2005
7
X9241A
The WCR is a volatile register; that is, its contents are lost
Detailed Operation
when the X9241A is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, it
should be noted this may be different from the value present
at power-down.
All four XDCP potentiometers share the serial interface and
share a common architecture. Each potentiometer is
comprised of a resistor array, a Wiper Counter Register and
four Data Registers. A detailed discussion of the register
organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile Data Registers.
These can be read or written directly by the host and data
can be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of these registers is a nonvolatile operation and
will take a maximum of 10ms.
Wiper Counter Register
The X9241A contains four volatile Wiper Counter Registers
(WCR), one for each XDCP potentiometer. The WCR can be
envisioned as a 6-bit parallel and serial load counter with its
outputs decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
WCR instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
If the application does not require storage of multiple
settings for the potentiometer, these registers can be used
as regular memory locations that could possibly store
system parameters or user preference data.
increment/decrement instruction; finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
Serial Data Path
Serial
Bus
Input
V /R
H
H
From Interface
Circuitry
Register 0
Register 2
Register 1
Register 3
Parallel
Bus
Input
8
6
C
o
u
n
t
e
r
Wiper
Counter
Register
D
e
c
o
d
e
2
INC/DEC
Logic
UP/DN
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
If WCR = 3F[H] then V /R = V /R
V /R
W
W
H
H
Modified SCL
L
L
CLK
DW
Cascade
Control
Logic
V
/R
W
W
CM
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
FN8164.1
September 15, 2005
8
X9241A
set to “1” the wiper is disabled. If the wiper is disabled, the
wiper terminal will be electrically isolated and float.
Cascade Mode
The X9241A provides a mechanism for cascading the
arrays. That is, the sixty-three resistor elements of one array
may be cascaded (linked) with the resistor elements of an
When operating in cascade mode V /R , V /R and the
H
H
L
L
wiper terminals of the cascaded arrays must be electrically
connected externally. All but one of the wipers must be
disabled. The user can alter the wiper position by writing
directly to the WCR or indirectly by transferring the contents
of the Data Registers to the WCR or by using the
Increment/Decrement command.
adjacent array. The V /R of the higher order array must be
L
H
L
connected to the V /R of the lower order array (See
H
Figure 9).
Cascade Control Bits
The data byte, for the three-byte commands, contains 6 bits
(LSBs) for defining the wiper position plus two high order
bits, CM (Cascade Mode) and DW (Disable Wiper, normal
operation).
When using the Increment/Decrement command the wiper
position will automatically transition between arrays. The
current position of the wiper can be determined by reading
the WCR registers; if the DW bit is “0”, the wiper in that array
is active. If the current wiper position is to be maintained on
power-down a global XFR WCR to Data Register command
must be issued to store the position in NV memory before
power-down.
The state of the CM bit (bit 7 of WCR) enables or disables
cascade mode. When the CM bit of the WCR is set to “0” the
potentiometer is in the normal operation mode. When the
CM bit of the WCR is set to “1” the potentiometer is
cascaded with its adjacent higher order potentiometer. For
example; if bit 7 of WCR2 is set to “1”, pot 2 will be cascaded
to pot 3.
It is possible to connect three or all four potentiometers in
cascade mode. It is also possible to connect POT 3 to POT 0
as a cascade. The requirements for external connections of
The state of DW enables or disables the wiper. When the
DW bit of the WCR is set to “0” the wiper is enabled; when
V /R , V /R and the wipers are the same in these cases.
L
L
H
H
V
/R
L0 L0
Pot 0
WCR0
V
/R
H0 H0
V
V
/R
W0 W0
/R
L1 L1
Pot 1
WCR1
V
/R
H1 H1
V
V
/R
W1 W1
/R
L2 L2
Pot 2
WCR2
V
/R
H2 H2
V
V
/R
W2 W2
/R
L3 L3
Pot 3
WCR3
V
V
/R
H3 H3
External
=
/R
W3 W3
Connection
FIGURE 9. CASCADING ARRAYS
FN8164.1
9
September 15, 2005
X9241A
Absolute Maximum Ratings
Temperature under bias. . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Voltage on SCK, SCL or any address
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V ) Limits
CC
input with respect to V
. . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
X9241A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
SS
Voltage on any V /R , V /R or V /R
L
H
H
W
W
L
referenced to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V/-4V
SS
∆V = |V /R - V /R |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
H
H
L
L
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Analog Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
End to end resistance
TEST CONDITION
MIN
TYP
MAX
+20
50
UNIT
%
R
-20
TOTAL
Power rating
25°C, each pot
mW
mA
Ω
I
Wiper current
Wiper resistance
See Note 7, 8
W
R
Wiper Current = ± 1mA (Note 7)
40
130
+5
W
V
Voltage on any V /R , V /R or V /R Pin
-3.0
V
TERM
H
H
W
W
L
L
Noise
Ref: 1kHz See Note 5
See Note 5
≤120
dBV
(4)
Resolution
1.6
0.4
±1
%
(3)
MI
(1)
Absolute linearity
R
- R
w(n)(expected)
w(n)(actual)
- [R
(2)
(3)
Relative linearity
R
]
w(n) + MI
±0.2
MI
w(n + 1)
Temperature Coefficient of R
See Note 5
See Note 5
±300
ppm/°C
ppm/C
pF
TOTAL
Ratiometric temperature coefficient
Potentiometer capacitances
±20
1
C /C /C
See Circuit #3 and Note 5
= V . Device is in stand-by
15/15/25
0.1
H
L
W
l
R , R , R leakage current
V
µA
AL
H
I
W
IN
mode.
TERM
DC Electrical Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
UNIT
MIN
TYP
MAX
l
Supply current (active)
f
= 100kHz, SDA = Open, Other
SCL
3
mA
CC
Inputs = V
SS
SCL = SDA = V , Addr. = V
SS
I
V
current (standby)
200
500
10
µA
µA
µA
V
SB
CC
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
10
LO
OUT
V
2
V
+ 1
CC
IH
V
-1
0.8
0.4
V
IL
V
I
= 3mA
OL
V
OL
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R –R )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
FN8164.1
10
September 15, 2005
X9241A
Endurance and Data Retention
PARAMETER
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Minimum endurance
Data retention
Capacitance
SYMBOL
PARAMETER
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
MAX
19
UNIT
pF
(5)
C
V
= 0V
= 0V
I/O
I/O
(5)
C
V
12
pF
IN
IN
Power-up Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
ms
ms
PUR
(6)
t
PUW
t V
V Power up ramp rate
CC
0.2
50
V/msec
R
CC
potentiometer pins. The Vcc ramp rate specification should
be met, and any glitches or slope changes in the Vcc line
should be held to <100mV if possible. Also, Vcc should not
reverse polarity by more than 0.5V.
Power-up Requirements (Power Up sequencing can affect
correct recall of the wiper registers)
The preferred power-on sequence is as follows: First Vcc,
then the potentiometer pins. It is suggested that Vcc reach
90% of its final value before power is applied to the
Notes: (5) This parameter is guaranteed by characterization or sample testing.
(6) t
and t
are the delays required from the time V
is stable until the specified operation can be initiated. These parameters are
CC
PUR
PUW
guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to
the device.
Symbol Table
AC Conditions of Test
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
WAVEFORM
INPUTS
OUTPUTS
CC
10ns
Input rise and fall times
Input and output timing levels
Must be
steady
Will be
steady
V
CC
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8164.1
11
September 15, 2005
X9241A
Equivalent AC Test Circuit
Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors
5V
120
V
I
CC MAX
1533Ω
R
R
=
=1.8kΩ
MIN
100
80
OL MIN
t
SDA Output
R
=
MAX
C
BUS
100pF
Max.
Resistance
60
40
20
0
Min.
Resistance
Circuit #3 SPICE Macro Model
20 40 60 80
120
100
0
Bus Capacitance (pF)
Macro Model
R
H
TOTAL
DCP Wiper Current De-rating Curve
R
R
H
L
C
L
C
7
6
5
4
3
10pF
C
W
10pF
25pF
R
W
2
1
0
0
10
20
30
40 50
60 70
80 90
Ambient Temperature (°C)
AC Electrical Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
REFERENCE
FIGURE
SYMBOL
PARAMETER
MIN
0
MAX
UNIT
kHz
ns
(5)
f
SCL clock frequency
Clock LOW period
100
10
10
SCL
(5)
(5)
t
4700
4000
LOW
t
Clock HIGH period
ns
10
HIGH
(5)
t
SCL and SDA rise time
SCL and SDA fall time
1000
300
20
ns
10
R
(5)
t
ns
10
F
(5)(9)
T
Noise suppression time constant (glitch filter)
Start condition setup time (for a repeated start condition)
Start condition hold time
ns
10
i
(5)
(5)
(5)
(5)
t
4700
4000
250
0
ns
10 & 12
10 & 12
10
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
ns
Data in setup time
ns
t
Data in hold time
ns
10
(5)
t
SCL LOW to SDA data out valid
Data out hold time
3500
10
ns
11
AA
(5)
t
50
ns
11
DH
(5)
t
Stop condition setup time
4700
4700
ns
10 & 12
10
SU:STO
(5)
BUF
t
Bus free time prior to new transmission
Write cycle time (nonvolatile write operation)
ns
(5)
t
ms
13
WR
FN8164.1
September 15, 2005
12
X9241A
AC Electrical Specifications (Over recommended operating conditions unless otherwise stated.) (Continued)
LIMITS
REFERENCE
FIGURE
SYMBOL
PARAMETER
Wiper response time from stop generation
Wiper response from SCL LOW
MIN
MAX
500
1000
50
UNIT
µs
(5)
t
13
6
STPWV
(5)
t
µs
CLWV
t
V
V
power-up rate
CC
0.2
mV/µs
R
CC
t
t
t
t
LOW
F
R
HIGH
SCL
SDA
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
(Data in)
t
BUF
FIGURE 10. INPUT BUS TIMING
SCL
t
t
AA
DH
SDA
(ACK)
SDA
SDA
SDA
OUT
OUT
OUT
FIGURE 11. OUTPUT BUS TIMING
Start Condition
Stop Condition
SCL
SDA
t
t
t
HD:STA
SU:STO
SU:STA
(Data in)
FIGURE 12. START STOP TIMING
SCL
Clock 8
Clock 9
STOP
START
t
WR
t
STPWV
SDA
SDA
ACK
IN
Wiper
Output
FIGURE 13. WRITE CYCLE AND WIPER RESPONSE TIMING
FN8164.1
September 15, 2005
13
X9241A
Packaging Information
20-Lead Plastic Dual In-Line Package Type P
1.060 (26.92)
0.980 (24.89)
0.280 (7.11)
0.240 (6.096)
Pin 1 Index
Pin 1
—
0.900 (23.66)
Ref.
0.005 (0.127)
0.195 (4.95)
0.115 (2.92)
Seating
Plane
––
(3.81) 0.150
0.015 (0.38)
(2.92) 0.1150
0.10 (BSC)
(2.54)
0.022 (0.559)
0.014 (0.356)
0.070 (1.778)
0.045 (1.143)
0.300
(7.62) (BSC)
0°
15°
0.014 (0.356)
0.008 (0.2032)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
FN8164.1
14
September 15, 2005
X9241A
Packaging Information
20-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.420 (10.65)
0.290 (7.37)
0.299 (7.60)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.496 (12.60)
0.508 (12.90)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0.420"
0°–8°
0.007 (0.18)
0.011 (0.28)
0.015 (0.40)
0.050 (1.27)
0.030" Typical
20 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8164.1
September 15, 2005
15
X9241A
Packaging Information
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.260 (6.6)
.252 (6.4)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8164.1
16
September 15, 2005
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