IR2107STR [INFINEON]
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| 型号： | IR2107STR |
| 厂家： | 
Infineon |
| 描述： | 暂无描述 驱动器 MOSFET驱动器 驱动程序和接口 接口集成电路 光电二极管 |
| 文件： | 总10页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Data Sheet No. PD60162J
IR2106/IR21064
IR2107/IR21074
HIGH AND LOW SIDE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +600V
Product Summary
•
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
5V Schmitt triggered input logic
V
600V max.
120 mA / 250 mA
10 - 20V
OFFSET
•
•
•
•
•
•
•
•
I +/-
O
V
OUT
Matched propagation delay for both channels
Logic and power ground +/- 5V offset.
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs (IR2106/IR21064)
Outputs out of phase with inputs (IR2107/IR21074)
t
(typ.)
180 ns
on/off
Delay matching
50 ns
Description
Packages
The IR2106/IR21064/IR2107/IR21074 are high volt-
age, high speed power MOSFET and IGBT drivers
with independent high and low side referenced out-
put channels. Proprietary HVIC and latch immune
CMOS technologies enable ruggedized monolithic
construction.The logic input is compatible with stan-
dard CMOS or LSTTL output. The output drivers
feature a high pulse current buffer stage designed
for minimum driver cross-conduction. The floating
channel can be used to drive an N-channel power
MOSFET or IGBT in the high side configuration
which operates up to 600 volts.
14 Lead SOIC
8 Lead SOIC
8 Lead PDIP
14 Lead PDIP
Typical Connection
up to 600V
VCC
VCC
VB
HIN
HIN
HIN/HIN HO
LIN
LIN
TO
LOAD
LIN/LIN
COM
VS
LO
up to 600V
IR21064/IR21074
HO
VB
VS
IR2106/IR2107
VCC
HIN
HIN
LIN
VCC
HIN/HIN
LIN/LIN
TO
LOAD
LIN
VSS
COM
LO
VSS
IR2106/IR21064/IR2107/IR21074
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Min.
-0.3
Max.
625
Units
V
B
S
V
V
B
- 25
V
+ 0.3
+ 0.3
25
B
V
HO
V
CC
V
S
- 0.3
V
B
Low side and logic fixed supply voltage
Low side output voltage
-0.3
-0.3
V
V
LO
V
+ 0.3
CC
V
IN
Logic input voltage (HIN & LIN - IR2106/IR21064)
(HIN & LIN - IR2107/IR21074)
V
SS
- 0.3
V
+ 0.3
CC
V
Logic ground (IR21064/IR21074 only)
Allowable offset supply voltage transient
V
- 25
V
+ 0.3
CC
SS
CC
dV /dt
—
50
V/ns
W
S
P
Package power dissipation @ T ≤ +25°C
(8 lead PDIP)
—
1.0
D
A
(8 lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
(8 lead PDIP)
(8 lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
—
—
—
—
—
—
—
—
-50
—
0.625
1.6
1.0
Rth
Thermal resistance, junction to ambient
125
200
75
JA
°C/W
°C
120
150
150
300
T
T
Junction temperature
J
Storage temperature
S
T
Lead temperature (soldering, 10 seconds)
L
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V and V offset rating are tested with all supplies biased at 15V differential.
S
SS
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
V
+ 10
V + 20
S
S
V
Note 1
600
S
V
HO
V
V
B
S
V
CC
10
0
20
V
V
LO
V
CC
V
Logic input voltage (HIN & LIN - IR2106/IR21064)
(HIN & LIN - IR2107/IR21074)
IN
V
SS
V
CC
V
Logic ground (IR21064/IR21074 only)
Ambient temperature
-5
-40
5
SS
°C
T
125
A
Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V .
BS
S
S
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2
IR2106/IR21064/IR2107/IR21074
Dynamic Electrical Characteristics
V
(V , V ) = 15V, V = COM, C = 1000 pF, T = 25°C.
L A
SS
BIAS CC BS
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
—
—
—
—
—
180
170
0
270
250
50
V = 0V
S
on
off
t
V
S
= 0V or 600V
MT
nsec
t
t
150
50
220
80
V
V
= 0V
= 0V
r
S
Turn-off fall time
f
S
Static Electrical Characteristics
V
(V , V ) = 15V, V = COM and T = 25°C unless otherwise specified. The V , V and I parameters are
CC BS SS A IL IH IN
BIAS
referenced to V /COM and are applicable to the respective input leads: HIN and LIN (IR2106/IR21064) and HIN and LIN
SS
(IR2107/IR21074). The V , I and Ron parameters are referenced to COM and are applicable to the respective output
O
O
leads: HO and LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “1” input voltage (IR2106/IR21064)
Logic “0” input voltage (IR2107/IR21074)
Logic “0” input voltage (IR2106/IR21064)
Logic “1”input voltage (IR2107/IR21074)
IH
2.7
VCC = 10V to 20V
—
—
V
IL
V
VCC = 10V to 20V
—
—
0.8
V
High level output voltage, V
- V
O
—
—
—
20
50
0.8
0.3
—
1.4
0.6
50
I
I
= 20 mA
= 20 mA
OH
BIAS
O
V
Low level output voltage, V
O
OL
O
I
LK
Offset supply leakage current
Quiescent V supply current
V
= V = 600V
B
S
I
60
150
240
V
= 0V or 5V
= 0V or 5V
QBS
QCC
BS
IN
IN
I
Quiescent V
supply current
120
µA
V
CC
I
Logic “1” input bias current
VIN = 5V (IR2106(4))
VIN = 0V (IR2107(4))
VIN = 0V (IR2106(4))
IN+
—
5
20
I
Logic “0” input bias current
IN-
—
1
2
V
IN = 5V (IR2107(4))
V
V
CC
and V supply undervoltage positive going
8.0
8.9
9.8
CCUV+
BS
V
threshold
and V supply undervoltage negative going
BSUV+
V
V
CC
7.4
0.3
8.2
0.7
9.0
—
CCUV-
BS
V
V
threshold
BSUV-
V
Hysteresis
CCUVH
V
BSUVH
I
Output high short circuit pulsed current
Output low short circuit pulsed current
120
250
200
350
—
—
V = 0V,
O
O+
PW ≤ 10 µs
= 15V,
mA
I
V
O
O-
PW ≤ 10 µs
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3
IR2106/IR21064/IR2107/IR21074
Functional Block Diagram
V B
UV
DETECT
2106
H O
R
R
S
Q
PULSE
FILTER
HV
LEVEL
SHIFTER
VSS/COM
V S
HIN
LEVEL
SHIFT
PULSE
GENERATOR
V C C
L O
UV
DETECT
VSS/COM
LEVEL
SHIFT
LIN
DELAY
C O M
V B
UV
DETECT
21064
H O
R
Q
R
S
PULSE
FILTER
HV
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFT
V S
HIN
PULSE
GENERATOR
V C C
L O
UV
DETECT
VSS/COM
LEVEL
SHIFT
LIN
DELAY
C O M
V S S
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4
IR2106/IR21064/IR2107/IR21074
V B
U V
D E T E C T
2107
H O
R
+5V
Q
R
S
P U L S E
F I L T E R
H V
L E V E L
S H I F T E R
V S S / C O M
L E V E L
S H I F T
V S
HIN
P U L S E
G E N E R A T O R
V C C
L O
U V
D E T E C T
+5V
V S S / C O M
L E V E L
S H I F T
LIN
D E L A Y
C O M
V B
UV
DETECT
21074
H O
R
R
+5V
Q
PULSE
FILTER
HV
LEVEL
SHIFTER
S
VSS/COM
LEVEL
SHIFT
V S
HIN
PULSE
GENERATOR
V C C
L O
UV
DETECT
+5V
VSS/COM
LEVEL
SHIFT
LIN
DELAY
C O M
V S S
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5
IR2106/IR21064/IR2107/IR21074
Lead Definitions
Symbol Description
HIN
HIN
LIN
LIN
VSS
Logic input for high side gate driver output (HO), in phase (IR2106/IR21064)
Logic input for high side gate driver output (HO), out of phase (IR2107/IR21074)
Logic input for low side gate driver output (LO), in phase (IR2106/IR21064)
Logic input for low side gate driver output (LO), out of phase (IR2107/IR21074)
Logic Ground (IR21064 and IR21074 only)
High side floating supply
V
B
HO
High side gate drive output
V
V
High side floating supply return
S
Low side and logic fixed supply
CC
LO
Low side gate drive output
COM
Low side return
Lead Assignments
V
V
1
2
3
4
V
CC
B
8
7
1
2
3
4
V
CC
B
8
7
HO
HO
HIN
LIN
HIN
LIN
V
S
V
S
6
5
6
5
LO
LO
COM
COM
8 Lead PDIP
8 Lead SOIC
IR2106
IR2106S
14
13
12
11
10
9
14
13
12
11
10
9
1
V
CC
1
2
3
4
5
6
7
V
CC
V
V
2
3
4
5
6
7
HIN
LIN
B
HIN
LIN
B
HO
HO
V
S
V
S
VSS
VSS
COM
LO
COM
LO
8
8
14 Lead PDIP
14 Lead SOIC
IR21064
IR21064S
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IR2106/IR21064/IR2107/IR21074
V
V
1
2
3
4
V
CC
B
8
1
2
3
4
V
CC
B
8
HO
HO
HIN
LIN
7
6
5
HIN
LIN
7
6
5
V
S
V
S
LO
LO
COM
COM
8 Lead PDIP
8 Lead SOIC
IR2107
IR2107S
14
13
12
11
10
9
14
1
V
CC
1
2
3
4
5
6
7
V
CC
V
V
13
12
11
10
9
2
3
4
5
6
7
HIN
LIN
HIN
LIN
B
B
HO
HO
V
S
V
S
VSS
COM
LO
VSS
COM
LO
8
8
14 Lead PDIP
14 Lead SOIC
IR21074
IR21074S
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7
IR2106/IR21064/IR2107/IR21074
8 Lead PDIP
01-3003 01
8 Lead SOIC
01-0021 08
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8
IR2106/IR21064/IR2107/IR21074
14 Lead PDIP
01-3002 03
14 Lead SOIC (narrow body)
01-3063 00
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IR2106/IR21064/IR2107/IR21074
HIN
LIN
HIN
LIN
50%
50%
50%
HIN
LIN
50%
t
HIN
LIN
t
t
t
f
on
off
r
HO
LO
90%
90%
HO
LO
Figure 1. Input/Output Timing Diagram
10%
10%
Figure 2. Switching Time Waveform Definitions
HIN
LIN
50%
50%
50%
50%
HIN
LIN
LO
HO
10%
MT
MT
90%
LO
HO
Figure 3. Delay Matching Waveform Definitions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd., Whyteleafe, Surrey CR3 0BL, United Kingdom
Tel: ++ 44 (0) 20 8645 8000
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086
IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon
Hong Kong Tel: (852) 2803-7380
Data and specifications subject to change without notice. 3/18/2000
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10
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INFINEON
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