AS7C33512NTD16A-166HTQC [ISSI]
ZBT SRAM, 512KX16, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100;
| 型号： | AS7C33512NTD16A-166HTQC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | ZBT SRAM, 512KX16, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100 静态存储器 |
| 文件： | 总12页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2002
AS7C33512NTD16A
AS7C33512NTD18A
®
TM
3.3V 512K × 16/18 ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋ
Features
• Available in100-pin TQFP and 119-ball BGA package
• Byte write enables
• Organization: 524,288 words × 16 or 18 bits
™
• NTD 1 architecture for efficient bus operation
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• Self-timed WRITE cycles
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” or “Pipeline” modes
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
• Asynchronous output enable control
™
1. NTD is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
19
19
Q
D
A[18:0]
Address
register
Burst logic
CLK
D
Q
Write delay
addr. registers
CLK
CE0
CE1
CE2
19
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
FT
512K x 16/18
SRAM
LBO
ZZ
Array
CLK
18/16
18/16
Data
DQ [a:b]
Q
D
Input
Register
18/16 18/16
CLK
18/16
CLK
CLK
CEN
Output
Register
OE
18/16
DQ[a:b]
OE
Selection Guide
-166
6
–150
6.6
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.0/3.51
150
3.8
100
5
MHz
ns
475
425
110
30
400
100
30
300
90
mA
mA
mA
Maximum standby current
130
Maximum CMOS standby current (DC)
30
30
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.
3/11/02; v.1.8H
Alliance Semiconductor
1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTD16A
AS7C33512NTD18A
®
Ball and pin assignment
Pin Configuration for 512 x 18 for 119-ball BGA
1
1
2
3
4
ADSP
ADV/LD
VDD
NC
5
6
7
A
B
C
D
E
VDDQ
NC
A
A
A
A
VDDQ
NC
CE1
A
A
A
CE2
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
FT
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CE0
OE
DQa
VDDQ
DQa
NC
F
VDDQ
NC
G
H
J
A
DQb
VDDQ
NC
R/W
VDD
CLK
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
CEN
A12
A02
VDD
NC
VDDQ
NC
DQa
NC
R
T
U
NC
NC
A
A
A
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
1 Note pins 6D and 2P are NC for x16.
2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
Pin arrangement for TQFP
A10
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
DQpa/NC
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
DQb
DQb
VSSQ 10
VDDQ 11
DQb 12
DQb 13
FT 14
TQFP 14 × 20mm*
VSS
VDD
ZZ
VDD 15
VDD 16
VSS 17
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
DQb 18
DQb 19
VDDQ 20
VSSQ 21
DQb 22
DQb 23
DQpb/NC 24
NC 25
NC
VSSQ
VDDQ
NC
VSSQ 26
VDDQ
27
NC 28
NC 29
NC 30
NC
NC
* Pins 24 and 74 are NC in x16
3/11/02; v.1.8H
Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
Functional description
The AS7C33512NTD16A/18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 16 or 18 bits and incorporates a LATE LATE Write.
™
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the
device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
™
NTD devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough)
™
read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD , write and
read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16/18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and AS7C33512NTD18A operate with a 3.3V 5ꢀ power supply for the device core (V ). DQ circuits use a sepa-
DD
rate power supply (V
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP and a 119-ball
DDQ
14×20 mm BGA package.
Capacitance
Parameter
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
Input capacitance
I/O capacitance
CI/O
VIN = VOUT = 0V
7
pF
Burst Order
Interleaved Burst Order
LBO=1
Linear Burst Order
LBO=0
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
01
11
10
01
00
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
10
11
00
01
11
00
01
10
00
11
10
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AS7C33512NTD16A
AS7C33512NTD18A
®
Signal descriptions
Signal
CLK
I/O Properties
Description
I
CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
I
I
SYNC
SYNC
SYNC
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b]
I/O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is HIGH.
I
I
I
SYNC
Advance or Load. When sampled HIGH, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
ADV/LD
R/W
SYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is HIGH.
SYNC
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b]
OE
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
Count mode. When driven High, count sequence follows Intel XOR convention. When
STATIC driven Low, count sequence follows linear convention. This input should be static when the
device is in operation.
LBO
I
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
FT
I
STATIC
ZZ
I
ASYNC Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
NC
-
-
No connects. Note that pin 84 will be used for future address expansion to 18Mb density.
Absolute maximum ratings
Parameter
Symbol
VDD, VDDQ
VIN
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
PD
W
mA
°C
°C
DC output current
IOUT
–
50
Storage temperature (plastic)
Temperature under bias
Tstg
–65
–65
+150
Tbias
+135
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
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Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
Synchronous truth table
CE0
H
X
CE1
X
CE2
X
ADV/LD
R/W BW[a,b] OE
CEN Address source
CLK
Operation
L
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
L
L
NA
NA
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Begin read
L
X
X
X
H
L
L
X
L
NA
L
H
H
X
L
X
L
External
External
Burst counter
Stall
L
L
L
L
L
L to H Begin write
L to H Burst2
X
X
H
X
X
X
X1
L
X
X
X
X
H
L to H Inhibit the CLK
1 Should be low for Burst write, unless a specific byte/s need/s to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = Low, H = High.
State Diagram for NTD SRAM
Burst
Read
Burst
Read
Read
Burst
Read
Dsel
Dsel
Burst
Burst
Burst
Write
Write
Burst
Write
Write
Recommended operating conditions
Parameter
Symbol
VDD
VSS
Min
3.135
0.0
Nominal
Max
3.6
Unit
3.3
0.0
3.3
0.0
2.5
0.0
–
Supply voltage
V
0.0
VDDQ
VSSQ
VDDQ
VSSQ
VIH
3.135
0.0
3.6
3.3V I/O supply
voltage
V
V
V
0.0
2.35
0.0
2.65
0.0
2.5V I/O supply
voltage
2.0
–0.52
VDD + 0.3
0.8
Address and
control pins
VIL
–
Input voltages1
VIH
2.0
–
VDDQ + 0.3
0.8
I/O pins
V
VIL
–0.52
0
–
Ambient operating temperature
TA
–
70
°C
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
.
IL
RC
3/11/02; v.1.8H
Alliance Semiconductor
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AS7C33512NTD16A
AS7C33512NTD18A
®
TQFP thermal resistance
Description
Conditions
Symbol
Typ i c a l
40
Units
°C/W
°C/W
1–layer
4–layer
θ
Thermal resistance
JA
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
θ
22
JA
JC
Thermal resistance
θ
8
°C/W
(junction to top of case)1
1 This parameter is sampled.
DC electrical characteristics
–166
–150
–133
–100
Parameter
Symbol
Test conditions
VDD = Max, VIN = GND to VDD
OE ≥ VIH, VDD = Max,
Min Max Min Max Min Max Min Max Unit
Input leakage
current
|ILI|1
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
µA
µA
Output leakage
current
|ILO
|
VOUT = GND to VDD
Operating power
supply current
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
2
ICC
ISB
ISB1
ISB2
–
–
–
475
130
30
–
–
–
425
110
30
–
–
–
400
100
30
–
–
–
300 mA
90
Deselected, f = fMax, ZZ ≤ VIL
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Standby power
supply current
30
mA
Deselected, f = f , ZZ
≥
V
– 0.2V
Max
DD
–
30
–
30
–
30
–
30
All VIN ≤ VIL or ≥ VIH
VOL
IOL = 8 mA, VDDQ = 3.465V
IOH = –4 mA, VDDQ = 3.135V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
V
Output voltage
VOH
2.4
2.4
2.4
2.4
–
1 LBO pin has an internal pull-up and input leakage = 10 µA.
2 I give with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
DC electrical characteristics for 2.5V I/O operation
–166
–150
–133
–100
Parameter
Symbol
|ILO
Test conditions
Min Max Min Max Min Max Min Max Unit
Output leakage
current
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
|
–1
1
–1
1
–1
1
–1
1
µA
V
VOL
IOL = 2 mA, VDDQ = 2.65V
IOH = –2 mA, VDDQ = 2.35V
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
Output voltage
VOH
1.7
1.7
1.7
1.7
3/11/02; v.1.8H
Alliance Semiconductor
6 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Timing characteristics over operating range
-166 H
–166
–150
–133
–100
Parameter
Symbol
fMax
tCYC
tCYCF
tCD 3.3V
tCD 2.5V
tCDF
Unit Notes1
Min Max Min Max Min Max Min Max Min Max
Clock frequency
–
6
166
–
–
6
166
–
–
150
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
6.6
10
–
7.5
12
–
10
12
–
–
–
ns
ns
Cycle time (flow-through mode)
Clock access time (pipelined mode)- 3.3V V
Clock access time (pipelined mode)- 2.5V V
Clock access time (flow-through mode)
Output enable LOW to data valid
Clock HIGH to output Low Z
10
–
–
10
–
–
–
–
3.0
4.0
9
3.5
4.0
9
3.8
4.3
10
3.8
–
4.0
4.5
10
4.0
–
5.0 ns
5.0 ns
12 ns
5.0 ns
DDQ
DDQ
–
–
–
–
–
–
–
–
–
–
tOE
–
3.5
–
–
3.5
–
–
–
–
tLZC
0
0
0
0
0
–
–
–
ns
ns
ns
2,3,4
2
Data output invalid from clock HIGH
Output enable LOW to output Low Z
Output enable HIGH to output High Z
Clock HIGH to output High Z
Output enable HIGH to invalid output
Clock HIGH pulse width
tOH
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
–
1.5
0
tLZOE
tHZOE
tHZC
tOHOE
tCH
–
–
–
–
2,3,4
2,3,4
2,3,4
–
3.0
3.0
–
–
3.5
3.5
–
–
3.8
3.8
–
–
4.0
4.0
–
–
4.5 ns
5.0 ns
–
–
–
–
–
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.4
2.4
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
–
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
–
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
5
5
Clock LOW pulse width
tCL
–
–
–
–
Address setup to clock HIGH
tAS
–
–
–
–
6
Data setup to clock HIGH
tDS
–
–
–
–
6
Write setup to clock HIGH
tWS
–
–
–
–
6,7
6,8
6
Chip select setup to clock HIGH
ADV/LD setup to clock HIGH
tCSS
–
–
–
–
tADVS
tCENS
tAH
–
–
–
–
Clock enable
ꢀ
setup to clock HIGH
–
–
–
–
6
Address hold from clock HIGH
Data hold from clock HIGH
–
–
–
–
6
tDH
–
–
–
–
6
Write hold from clock HIGH
Chip select hold from clock HIGH
ADV/LD hold from clock HIGH
tWH
–
–
–
–
6,7
6,8
6
tCSH
–
–
–
–
tADVH 0.5
tCENH 0.5
–
–
–
–
Clock enable hold from clock HIGH
–
–
–
–
6
1 Refer to “notes” on page 10.
3/11/02; v.1.8H
Alliance Semiconductor
7 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Timing waveform of read/write cycle
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ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢈꢄ
ꢆꢁꢂꢉꢄ
ꢆꢁꢂꢊꢄ
ꢀꢁꢂꢃÝꢆꢄꢅ
ꢀꢁꢂꢈꢋꢌꢃꢄ
&%ꢕ'ꢂ()ꢕ*+(
BURST
READ
Q(A4Ý01)
WRITE
D(A1)
WRITE
D(A5)
READ
Q(A6) D(A7)
WRITE
READ
Q(A3)
DSEL
BURST
WRITE
D(A2Ý01)
WRITE
D(A2)
ꢁꢕꢖꢖꢗꢘꢙ
READ
Q(A4)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:b] is don’t care.
3/11/02; v.1.8H
Alliance Semiconductor
8 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
NOP, stall and deselect cycles
ꢁꢅꢉ
ꢁꢆꢀ
ꢁꢆꢜ
ꢁꢆꢊꢋꢌꢁꢆꢍ
ꢎꢏꢐꢑꢅꢏ
ꢒꢑꢓ
ꢛꢓꢘ
ꢎꢜ
ꢎꢍ
ꢎꢝ
ꢎꢏꢏꢒꢆꢇꢇ
ꢆꢁꢂꢃꢄ
ꢇꢁꢂꢅÝꢄꢅꢆ
ꢇꢁꢂꢅÝꢅꢄꢆ
ꢀꢁꢂꢈꢄ
ꢏꢔ
"#"$%#ꢘ$
ꢆꢁꢂꢃꢄ
ꢀꢁꢂꢈꢄ
ꢏꢔ
ꢇꢁꢂꢅÝꢄꢅꢆ
ꢇꢁꢂꢅÝ10ꢆ
&%ꢕ'ꢂ(ꢕ*+(
BURST
DSEL
WRITE BURST
BURST
D(A2Ý10) NOP
D(A3)
WRITE
BURST
Q(A1Ý10)
STALL
DSEL
READ
Q(A1)
BURST
Q(A1Ý01)
ꢁꢕꢖꢖꢗꢘꢙ
D(A2)
NOP
D(A2Ý01)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
3/11/02; v.1.8H
Alliance Semiconductor
9 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω/1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
L
D
OUT
90ꢀ
10ꢀ
90ꢀ
10ꢀ
5 pF*
for 3.3V I/O;
353Ω/1538Ω
30 pF*
= V
/2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100ꢀ tested.
4) t
is less than t
and t
is less than t at any given temperature and voltage.
HZOE
LZOE
HZC
LZC
5) t measured HIGH above V and t measured as LOW below V
CH IH CL
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W, BW[a:d].
8) Chip select refers to CE0, CE1, CE2.
3/11/02; v.1.8H
Alliance Semiconductor
10 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Package Dimensions
100-pin quad flat pack (TQFP)
Hd
D
TQFP
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
0.22
0.38
c
0.09
0.20
D
13.90
19.90
14.10
20.10
E
e
0.65 nominal
Hd
He
L
15.90
21.90
0.45
16.10
22.10
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
α
L1
L
A1 A2
119-ball Ball Grid Array (BGA)
All measurements are in mm in
the table. The diagram has
meaurements in inches in
parentheses
Min
-
Typical Max
1.27
A
B
-
13.80 14.00 14.20
7.82
21.80 22.00 22.20
B1
C
-
-
C1
D
-
20.23
0.76
-
-
0.81
2.40
-
0.71
E
-
E1
E2
F
-
0.56
0.60
12.00
0.70
0.50
0.70
-
-
-
F1
-
3/11/02; v.1.8H
Alliance Semiconductor
11 of 12
AS7C33512NTD16A
AS7C33512NTD18A
®
Ordering information
Package
&Width
-166 H MHz
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33512NTD16A
-
-
-
-
-
-
-
-
AS7C33512NTD16A-
166TQC
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150TQC 133TQC 100TQC
TQFP x16
166HTQC
AS7C33512NTD16A
166HTQI
AS7C33512NTD16A-
166TQI
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150TQI 133TQI 100TQI
TQFP x16
TQFP x18
TQFP x18
BGA x16
BGA x16
BGA x18
BGA x18
AS7C33512NTD18A
166HTQC
AS7C33512NTD18A-
166TQC
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
150TQC 133TQC 100TQC
AS7C33512NTD18A
166HTQI
AS7C33512NTD18A-
166TQI
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
150TQI 133TQI 100TQI
AS7C33512NTD16A
166HBC
AS7C33512NTD16A-
166BC
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150BC 133BC 100BC
AS7C33512NTD16A
166HBI
AS7C33512NTD16A-
166BI
AS7C33512NTD16A- AS7C33512NTD16A- AS7C33512NTD16A-
150BI 133BI 100BI
AS7C33512NTD18A
166HBC
AS7C33512NTD18A-
166BC
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
150BC 133BC 100BC
AS7C33512NTD18A
166HBI
AS7C33512NTD18A-
166BI
AS7C33512NTD18A- AS7C33512NTD18A- AS7C33512NTD18A-
150BI
133BI
100BI
Part numbering guide
AS7C
33
512
NTD
16/18
A
–XXX (H)
TQ or B
C/I
1
2
3
4
5
6
7
8
9
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33=3.3V
3. Organization: 512=512K
4. NTD™ = No-Turn Around Delay. Pipeline-Flowthrough (each device works in both modes)
5. Organization: 16=x16; 18=x18
6. Production version: A=first production version
7. Clock speed (MHz); “H” indicates faster clock access time.
8. Package type: TQ=TQFP; B=BGA
9. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
3/11/02; v.1.8H
Alliance Semiconductor
12 of 12
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of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
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相关型号：
AS7C33512NTD18A-100TQIN
ZBT SRAM, 512KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
ALSC
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