IS61C256AL-12TLI-TR [ISSI]
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, LEAD FREE, PLASTIC, TSOP1-28;
| 型号： | IS61C256AL-12TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, LEAD FREE, PLASTIC, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61C256AL
32K x 8 HIGH-SPEED CMOS STATIC RAM
MAY 2012
DESCRIPTION
FEATURES
The ISSI IS61C256AL is a very high-speed, low power,
32,768 word by 8-bit static RAMs. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques,yieldsaccesstimesasfastas10nsmaximum.
• High-speed access time: 10, 12 ns
• CMOS Low Power Operation
— 1 mW (typical) CMOS standby
— 125 mW (typical) operating
• Fully static operation: no clock or refresh
required
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) with CMOS input levels.
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
Easy memory expansion is provided by using an active
LOW Chip Enable (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
TheIS61C256ALispincompatiblewithother32Kx8SRAMs
and are available in 28-pin SOJ and TSOP (Type I)
packages.
FUNCTIONAL BLOCK DIAGRAM
32K X 8
MEMORY ARRAY
A0-A14
DECODER
VDD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
1
IS61C256AL
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
28-Pin TSOP
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
A8
A6
4
A13
WE
VDD
A14
A12
A7
A5
5
A9
A4
6
A11
OE
A3
7
2
A2
8
A10
CE
3
A1
9
A6
4
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A5
5
A4
6
A1
I/O0
I/O1
I/O2
GND
A3
7
8
A2
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE
CE OE I/O Operation VDD Current
A0-A14
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
OE
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
Read
Write
H
L
I/O0-I/O7
VDD
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
Parameter
Value
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
–0.5 to +7.0
–65 to +150
1.5
°C
Power Dissipation
W
IOUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
IS61C256AL
OPERATING RANGE
Range
AmbientTemperature
Speed(ns)
VDD (V)
5V 5%
5V 10%
5V 10%
Commercial
Commercial
Industrial
0°Cto+70°C
0°Cto+70°C
–40°Cto+85°C
-10
-12
-12
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
—
0.4
V
2.2
VDD + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–2
1
2
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD,
OutputsDisabled
Com.
Ind.
–1
–2
1
2
µA
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10
-12
Symbol
Parameter
TestConditions
Min. Max.
Min. Max.
Unit
ICC1
VDDOperating
SupplyCurrent
VDD =Max.,CE=VIL
Com.
Ind.
—
—
20
—
—
—
20
25
mA
IOUT =0mA,f=0
ICC2
ISB1
ISB2
VDD DynamicOperating
SupplyCurrent
VDD =Max.,CE=VIL
Com.
Ind.
—
—
45
—
—
—
35
40
mA
IOUT =0mA,f=fMAX
typ.(2)
25
TTLStandbyCurrent
(TTLInputs)
VDD =Max.,
Com.
Ind.
—
—
1
—
—
1
2
mA
µA
VIN =VIH orVIL
—
CE
≥
VIH,f=0
CMOSStandby
VDD =Max.,
Com.
Ind.
typ.(2)
—
—
350
—
—
—
350
450
Current(CMOSInputs)
CE
VIN
VIN
≥
≥
VDD –0.2V,
VDD –0.2V,or
200
≤
0.2V, f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25oC and not 100% tested.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
3
IS61C256AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min. Max
-12 ns
Min. Max.
Symbol
tRC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE toPower-Up
10
—
2
—
10
—
10
6
12
—
2
—
12
—
12
6
tAA
tOHA
tACS
—
—
0
—
—
0
tDOE
(2)
tLZOE
—
5
—
6
(2)
tHZOE
—
2
—
3
(2)
tLZCS
—
5
—
7
(2)
tHZCS
—
0
—
0
(3)
tPU
—
10
—
12
(3)
tPD
CEtoPower-Down
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevels
1.5V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
5 pF
255 Ω
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
IS61C256AL
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
OE
tAA
tOHA
tHZOE
tDOE
tLZOE
tACS
CE
tHZCS
tLZCS
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
5
IS61C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10ns
Min.
-12 ns
Min. Max.
Symbol
tWC
Parameter
Max
—
Unit
ns
Write Cycle Time
CE to Write End
10
9
12
10
10
—
—
—
tSCS
—
ns
tAW
Address Setup Time
to Write End
9
—
ns
tHA
AddressHold
from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
9
—
—
—
—
—
6
0
9
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width (OE LOW)
WE Pulse Width (OE HIGH)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
8
7
7
tHD
0
0
(2)
tHZWE
—
0
—
0
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
tWC
VALID ADDRESS
ADDRESS
tSA
tSCS
tHA
CE
tAW
tPWE1
tPWE2
WE
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
DOUT
tSD
tHD
DATAIN VALID
DIN
CE_WR1.eps
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
IS61C256AL
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
tWC
ADDRESS
VALID ADDRESS
tHA
OE
LOW
CE
tAW
tPWE1
WE
DOUT
DIN
tSA
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
tHD
DATAIN VALID
CE_WR2.eps
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
tWC
VALID ADDRESS
ADDRESS
tHA
LOW
LOW
OE
CE
tAW
tPWE2
WE
tSA
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
DOUT
tSD
tHD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
≥ VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
7
IS61C256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
TestCondition
Min. Typ.(1)
Max. Unit
VDR
VDD forDataRetention
SeeDataRetentionWaveform
VDD =2.0V,CE≥VDD –0.2V
2.0
5.5
V
IDR
DataRetentionCurrent
Com.
Ind.
—
—
50
90
µA
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
100
tSDR
tRDR
DataRetentionSetupTime
RecoveryTime
SeeDataRetentionWaveform
SeeDataRetentionWaveform
0
—
—
ns
ns
tRC
Note:
1. Typical Values are measured at VDD = 5V, TA
= 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE ≥ VDD - 0.2V
CE
GND
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
IS61C256AL
ORDERING INFORMATION: IS61C256AL
Commercial Range: 0°C to +70°C
Speed(ns)
OrderPartNumber
Package
10
IS61C256AL-10JL
IS61C256AL-10T
IS61C256AL-10TL
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
12
IS61C256AL-12JL
IS61C256AL-12T
IS61C256AL-12TL
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
Industrial Range: –40°C to +85°C
Speed(ns)
OrderPartNumber
Package
12
IS61C256AL-12JLI
IS61C256AL-12TI
IS61C256AL-12TLI
300-mil Plastic SOJ, Lead-free
TSOP (Type 1)
TSOP (Type 1), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
9
IS61C256AL
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
IS61C256AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
05/09/12
11
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