IS61WV3216BLL [ISSI]
32K x 16 HIGH-SPEED CMOS STATIC RAM; 32K ×16高速CMOS静态RAM
| 型号： | IS61WV3216BLL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 32K x 16 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总16页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS64WV3216BLL
IS61WV3216BLL
ISSI
32K x 16 HIGH-SPEED CMOS STATIC RAM
NOVEMBER 2005
FEATURES
DESCRIPTION
TheISSIIS61/64WV3216BLLisahigh-speed,524,288-bit
static RAM organized as 32,768 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology.Thishighlyreliableprocesscoupledwithinno-
vative circuit design techniques, yields access times as
fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low
powerconsumption.
• High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
• CMOS low power operation:
50 mW (typical) operating
25 µW (typical) standby
• TTL compatible interface levels
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
• Three state outputs
EasymemoryexpansionisprovidedbyusingChipEnable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Data control for upper and lower bytes
• Automotive Temperature Available
• Lead-free available
The IS61/64WV3216BLL is packaged in the JEDEC stan-
dard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
32K x 16
MEMORY ARRAY
A0-A14
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
1
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
PIN CONFIGURATIONS
44-Pin TSOP-II
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
NC
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
A0
A3
A1
A4
A2
LB
OE
UB
NC
I/O
A
B
C
D
E
F
6
7
I/O
CE
8
0
8
9
I/O
I/O
I/O
A5
A6
I/O
I/O
I/O
2
9
10
1
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
NC
NC
A14
A12
A7
V
DD
11
3
4
5
VDD
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
I/O
I/O
GND
VDD
I/O
I/O
NC
NC
A13
A10
12
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
A8
A7
NC
NC
PIN DESCRIPTIONS
A0-A14
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
UB
NC
VDD
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
ICC
OutputDisabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
Parameter
Value
Unit
V
Terminal Voltage with Respect to GND
StorageTemperature
–0.5 to VDD+0.5
–65 to +150
1.5
°C
W
PowerDissipation
VDD
VDD Related to GND
-0.2 to +3.9
V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE (VDD)
Range
AmbientTemperature
0°C to +70°C
VDD (15ns)
2.5V-3.6V
2.5V-3.6V
2.5V-3.6V
VDD (12ns)
3.3V + 10%
3.3V + 10%
3.3V + 10%
Commercial
Industrial
Automotive
–40°Cto+85°C
–40°Cto+125°C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
3
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.5V-3.6V
Symbol Parameter
TestConditions
Min.
2.3
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 1.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2.0
–0.3
–2
VDD + 0.3
V
0.8
2
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–2
2
Note:
1.
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 10%
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–2
0.8
2
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–2
2
Note:
1.
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Options
Min.
Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating VDD = Max.,
COM.
IND.
AUTO
typ.(2)
—
—
—
—
35
45
60
20
—
—
—
—
30
40
50
20
mA
Supply Current
IOUT = 0 mA, f = fMAX
ICC1
Operating Supply
Current
VDD = Max.,
COM.
—
5
—
5
mA
uA
Iout = 0mA, f = 0
IND.
AUTO
—
—
5
5
—
—
5
5
ISB2
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VDD = Max.,
COM.
IND.
AUTO
typ.(2)
—
—
—
—
20
50
75
6
—
—
—
—
20
50
75
6
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
5
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
AC TEST CONDITIONS
Parameter
Unit
Unit
(2.5V-3.6V)
(3.3V + 10%)
Input Pulse Level
0V to VDD V
1.5ns
0V to VDD V
1.5ns
Input Rise and Fall Times
Input and Output Timing
VDD/2
VDD/2 + 0.05
andReferenceLevel(VRef)
OutputLoad
See Figures 1a and 1b
See Figures 1a and 1b
AC TEST LOADS
319 Ω
2.5V
Zo=50Ω
50Ω
VRef
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1a.
Figure 1b.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-12 ns
-15 ns
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
12
—
3
—
12
—
12
6
15
—
3
—
15
—
15
7
tAA
Address Access Time
Output Hold Time
tOHA
tACE
CE Access Time
—
—
—
0
—
—
0
tDOE
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
6
6
(2)
tLZOE
—
6
0
—
6
(2
tHZCE
0
0
(2)
tLZCE
3
—
6
3
—
7
tBA
—
0
—
0
tHZB
6
6
tLZB
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0V to
VDD V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
7
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-12 ns
-15 ns
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
12
9
—
—
—
15
10
10
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
9
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
6
0
0
—
—
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWB
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
9
10
10
12
9
9
11
9
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
0
(3)
tHZWE
—
3
—
3
(3)
tLZWE
—
—
Notes:
1. Test conditions for IS61WV3216BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0V to VDD V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
9
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
t
PWE1
PWE2
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
LOW
CE
t
AW
t
PWE1
WE
UB, LB
DOUT
t
SA
t
PBW
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
UB, LB
DOUT
t
SA
t
PBW
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
See Data Retention Waveform
VDD = 1.8V, ≥ VDD – 0.2V
Operations
Min.
1.8
—
Typ.(1)
Max.
3.6
Unit
V
VDD for Data Retention
Data Retention Current
—
6
IDR
COM.
20
µA
CE
IND.
AUTO
—
—
6
6
50
75
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
Note:
1. Typical values are measured at VDD = 2.5V, T
O
A
= 25 C. Not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
t
RDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
13
09/26/05
IS64WV3216BLL
IS61WV3216BLL
®
ISSI
ORDERING INFORMATION
Industrial Temperature Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
12
12
12
12
IS61WV3216BLL-12TI
IS61WV3216BLL-12TLI
IS61WV3216BLL-12BI
IS61WV3216BLL-12BLI
Plastic TSOP
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Temperature Range (A3): –40°C to +125°C
Speed(ns)
Order Part No.
Package
15(12*)
15(12*)
15(12*)
15(12*)
IS64WV3216BLL-15TA3
IS64WV3216BLL-15TLA3
IS64WV3216BLL-15BA3
IS64WV3216BLL-15BLA3
Plastic TSOP
Plastic TSOP, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Note:
1. Speed = 12ns for VDD = 3.3V + 10%. Speed = 15ns for VDD = 2.5V- 3.6V.
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
09/26/05
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
7.90
0.009
0.024
0.311
A1
A2
D
0.24
0.60
9.90
0.009
0.024
0.390
8.10
0.319
10.10
0.398
D1
E
5.25 BSC
—
0.207 BSC
D1
E
5.25 BSC
—
0.207 BSC
5.90
6.10
0.232
—
0.240
7.90
8.10
0.311
—
0.319
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
0.030 BSC
0.030 BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
相关型号：
©2020 ICPDF网 联系我们和版权申明