IS62VV51216LL-70BI [ISSI]
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 8 X 10 MM, MINI, BGA-48;
| 型号： | IS62VV51216LL-70BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 8 X 10 MM, MINI, BGA-48 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62VV51216LL
512K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
ISSI
PRELIMINARY INFORMATION
JULY 2000
FEATURES
DESCRIPTION
The ISSI IS62VV51216LL is a high-speed, 8M bit static
RAMs organized as 512K words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
designtechniques,yieldshigh-performanceandlowpower
consumption devices.
• High-speed access time: 70, 85 ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 1.65V-1.95V VCC power supply
For the IS62VV51216LL, when CS1 is HIGH (deselected)
or when CS2 is LOW (deselected) or when CS1 is LOW,
CS2 is HIGH and both LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• Three state outputs
• Data control for upper and lower bytes
• Industrialtemperatureavailable
• Available in 48-pin mini BGA (8mm x 10mm)
The IS62VV51216LL is packaged in the JEDEC standard
48-pin mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
512K x 16
MEMORY ARRAY
A0-A18
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1
OE
CONTROL
CIRCUIT
WE
UB
LB
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
PIN CONFIGURATIONS
48-Pin mini BGA
PIN DESCRIPTIONS
1
2
3
4
5
6
A0-A18
I/O0-I/O15
CS1, CS2
OE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A0
A3
A1
A4
A2
LB
OE
UB
I/O
CS2
A
B
C
D
E
F
WE
I/O
8
CS1
I/O
0
I/O
9
A5
A6
I/O
1
I/O
2
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
10
GND
Vcc
A17
A7
I/O
I/O
I/O
3
Vcc
11
UB
I/O
4
GND
VSS
A16
A15
A13
A10
12
NC
I/O
14
A14
A12
A9
I/O
5
I/O
13
I/O
6
Vcc
Power
I/O
15
NC
A8
WE
I/O
7
G
H
GND
Ground
A18
A11
NC
TRUTHTABLE
I/O PIN
Mode
WE CS1 CS2
OE
LB
UB
I/O0-I/O7
I/O8-I/O15 Vcc Current
Not Selected
X
X
X
H
X
X
X
L
X
X
X
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
ICC
ICC
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
Write
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
1.65V - 1.95V
1.65V - 1.95V
–40°C to +85°C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
VCC
Parameter
Value
–0.2 to Vcc+0.3
–40 to +85
–0.2 to +2.6
–65 to +150
1.0
Unit
V
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
°C
V
TSTG
PT
Storage Temperature
°C
W
Power Dissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectreliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
Min.
1.4
—
Max.
Unit
V
VOH
VOL
VIH
Output HIGH Voltage
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
0.2
V
1.4
–0.3
–1
VCC + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
Input Capacitance
Input/Output Capacitance
pF
pF
COUT
VOUT = 0V
10
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
AC TEST CONDITIONS
Parameter
Unit
0.4V to VCC - 0.2V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
0.9V
Output Load
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
1.8V
1.8V
OUTPUT
OUTPUT
3150 Ω
3150 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
IS62VV51216LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70
-85
-100
Min. Max.
Symbol Parameter
TestConditions
CC = Max.,
OUT = 0 mA, f = fMAX
CC = Max.,
OUT = 0 mA, f = 0
Min. Max.
Min. Max.
Unit
mA
ICC
VccDynamicOperating
SupplyCurrent
V
I
V
I
Com.
Ind.
Com.
Ind.
Com.
Ind.
—
—
—
—
—
—
20
25
3
3
0.3
0.3
—
—
—
—
—
—
15
20
3
3
0.3
0.3
—
—
10
15
I
CC
1
OperatingSupply
Current
—
—
3
3
mA
mA
I
SB
1
TTLStandbyCurrent
(TTLInputs)
VCC = Max.,
—
—
0.3
0.3
V
IN = VIH or VIL
CS1 = VIH , CS2 = VIL
,
f = 1 MH
Z
OR
ULB Control
VCC = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
I
SB
2
CMOSStandby
Current (CMOS Inputs)
V
CC = Max.,
Com.
Ind.
—
—
10
10
—
—
10
10
—
—
10
10
µA
CS1 CC – 0.2V,
CS2 ≤ 0.2V,
V
≥ V
IN
≥
≤
V
CC – 0.2V, or
V
IN
0.2V, f = 0
OR
ULB Control
VCC = Max., CS1 = VIL
IN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V
V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-70
Min.
-85
Min.
-100
Min.
Symbol
tRC
Parameter
Max.
—
Max.
—
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
—
10
—
—
—
5
85
—
10
—
—
—
5
100
—
10
—
—
—
5
—
100
—
tAA
Address Access Time
Output Hold Time
70
—
85
—
tOHA
tACS1
tDOE
CS1 Access Time
OE Access Time
70
35
25
—
85
40
25
—
100
50
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CS1 to High-Z Output
CS1 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
30
(2)
tLZOE
—
(2)
tHZCS1
0
25
—
0
25
—
0
30
(2)
tLZCS1
tBA
10
—
0
10
—
0
10
—
0
—
70
25
—
85
25
—
100
35
tHZB
tLZB
0
0
0
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA
tOHA
DATA VALID
tOHA
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, OE, AND UB/LB Controlled)
tRC
ADDRESS
OE
tAA
tOHA
t
HZOE
tDOE
tLZOE
CS1
tACS1/tACS2
CS2
tLZCS1/
tLZCS2
t
HZCS1
LB, UB
tBA
tHZB
tLZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL.
3. Address is valid prior to or coincident with CS1 LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-70
Min. Max.
-85
Min. Max.
-100
Min. Max.
Symbol
tWC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
70
60
60
0
—
—
—
—
—
—
—
—
—
20
—
85
70
70
0
—
—
—
—
—
—
—
—
—
25
—
100
80
80
0
—
—
—
—
—
—
—
—
—
30
—
tSCS1
tAW
CS1 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tHA
tSA
0
0
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
60
50
30
0
70
60
35
0
80
80
40
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
outputloadingspecifiedinFigure1.
2. The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
(4)
t
PWE
WE
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
DOUT
DIN
DATA UNDEFINED
tSD
t
HD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and at least one
of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE1, 2
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE1, 2
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
UB, LB
DOUT
t
PBW
t
PBW
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
DATA RETENTION SWITCHING CHARACTERISTICS (LL)
Symbol
VDR
Parameter
TestCondition
Min.
1.0
—
Max.
2.2
5
Unit
V
Vcc for Data Retention
DataRetentionCurrent
Data Retention Setup Time
RecoveryTime
SeeDataRetentionWaveform
Vcc = 1.0V, CS1 ≥ Vcc – 0.2V
SeeDataRetentionWaveform
SeeDataRetentionWaveform
IDR
µA
ns
tSDR
0
—
tRDR
tRC
—
ns
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR
Data Retention Mode
tRDR
VCC
1.65V
1.4V
VDR
CS1 ≥ VCC - 0.2V
CS1
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
PRELIMINARY INFORMATION Rev. 00A
09/29/00
®
IS62VV51216LL
ISSI
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
IS62VV51216LL-70B Mini BGA
IS62VV51216LL-85B Mini BGA
Speed (ns) Order Part No.
Package
70
85
IS62VV51216LL-70BI Mini BGA
IS62VV51216LL-85BI Mini BGA
70
85
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/29/00
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