IS63LV1024-8K-TR [ISSI]
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| 型号： | IS63LV1024-8K-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 暂无描述 存储 内存集成电路 静态存储器 光电二极管 |
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®
IS63LV1024
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
ISSI
SEPTEMBER 2000
FEATURES
DESCRIPTION
The ISSI IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
• High-speed access times:
8, 10, 12 and 15 ns
• High-performance, low-powerCMOSprocess
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
• CE power-down
• Fully static operation: no clock or refresh
required
The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
FUNCTIONAL BLOCK DIAGRAM
128K X 8
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. H
10/02/00
®
IS63LV1024
ISSI
PIN CONFIGURATION
32-Pin SOJ
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
A0
A1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
2
A2
3
A3
4
CE
5
I/o7
I/O6
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
6
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
7
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
8
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A5
A6
A7
A8
A5
A6
A7
A8
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE
CE OE I/O Operation Vcc Current
A0-A16
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
OE
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
Read
Write
H
L
I/O0-I/O7
Vcc
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
°C
°C
W
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
1.0
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
®
IS63LV1024
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
–40°C to +85°C
3.3V 0.3V
3.3V 0.15V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.2
VCC + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled Com.
–1
–5
1
5
µA
Ind.
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10ns
Min. Max.
-12ns
Min. Max.
-15ns
Min. Max.
Symbol Parameter
TestConditions
Unit
ICC1
VccOperating
SupplyCurrent
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
160
170
—
—
150
160
—
—
130
140
—
—
120
130
mA
ISB
TTL Standby
Current
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = Max
Com.
Ind.
—
—
55
55
—
—
45
45
—
—
40
40
—
—
35
35
mA
mA
mA
ISB1
ISB2
TTL Standby
Current
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
25
30
—
—
25
30
—
—
25
30
—
—
25
30
CMOSStandby
Current
VCC = Max.,
CE ≤ VCC – 0.2V,
Com.
Ind.
—
—
5
10
—
—
5
10
—
—
5
10
—
—
5
10
(CMOSInputs)
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. H
10/02/00
®
IS63LV1024
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min.
-10ns
Min.
-12ns
Min.
-15ns
Min.
Symbol Parameter
Max.
—
8
Max.
—
10
—
10
5
Max.
—
12
—
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
—
2
10
—
2
12
—
3
15
—
3
—
15
—
15
7
tAA
Address Access Time
Output Hold Time
tOHA
tACE
tDOE
tLZOE
—
8
CE Access Time
—
—
0
—
—
0
—
—
0
—
—
0
OE Access Time
4
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power Up Time
CE to Power Down Time
—
4
—
5
—
6
—
7
tHZOE
0
0
0
0
(2)
tLZCE
tHZCE
tPU
3
—
4
3
—
5
3
—
6
3
—
7
(2)
0
0
0
0
0
—
8
0
—
10
0
—
12
0
—
15
tPD
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
outputloadingspecifiedinFigure1.
2. Tested with the C2 load in Figure 1. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
317 Ω
Z
OUT = 50 Ω
3.3V
OUTPUT
OUTPUT
50 Ω
351 Ω
5 pF
Including
jig and
scope
VT = 1.5V
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
®
IS63LV1024
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. H
10/02/00
®
IS63LV1024
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
Min.
-10ns
-12ns
-15ns
Min. Max.
Symbol
tWC
Parameter
Max.
—
Min.
Max.
Min.
Max.
Unit
ns
Write Cycle Time
CE to Write End
8
7
8
10
7
—
12
8
—
15
10
10
—
—
—
tSCE
—
—
—
ns
tAW
Address Setup Time to
WriteEnd
—
8
—
8
—
ns
tHA
tSA
(1)
tPWE
1
(2)
tPWE
2
Address Hold from
WriteEnd
0
—
0
—
0
—
0
—
ns
Address Setup Time
0
7
—
—
—
—
—
4
0
7
—
—
—
—
—
5
0
8
—
—
—
—
—
6
0
10
15
7
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
10
5
12
6
tSD
tHD
5
0
0
0
0
(2)
tHZWE
—
3
—
3
—
3
—
3
(2)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
®
IS63LV1024
ISSI
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. H
10/02/00
®
IS63LV1024
ISSI
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS63LV1024-8T
IS63LV1024-8J
IS63LV1024-8K
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
8
IS63LV1024-8TI
IS63LV1024-8JI
IS63LV1024-8KI
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
10
12
15
IS63LV1024-10T
IS63LV1024-10J
IS63LV1024-10K
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
10
12
15
IS63LV1024-10TI
IS63LV1024-10JI
IS63LV1024-10KI
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
IS63LV1024-12T
IS63LV1024-12J
IS63LV1024-12K
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
IS63LV1024-12TI
IS63LV1024-12JI
IS63LV1024-12KI
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
IS63LV1024-15T
IS63LV1024-15J
IS63LV1024-15K
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
IS63LV1024-15TI
IS63LV1024-15JI
IS63LV1024-15KI
TSOP (Type II)
300-milPlasticSOJ
400-milPlasticSOJ
®
ISSI
IntegratedSiliconSolution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
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