IXDD409PI [IXYS]
9 Amp Low-Side Ultrafast MOSFET Driver; 9安培低端超快MOSFET驱动器
| 型号： | IXDD409PI |
| 厂家： | 
IXYS CORPORATION |
| 描述： | 9 Amp Low-Side Ultrafast MOSFET Driver |
| 文件： | 总10页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
9 Amp Low-Side Ultrafast MOSFET Driver
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes.
• Latch Up Protected
• High Peak Output Current: 9A Peak
• Operates from 4.5V to 25V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 2500pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• LowOutputImpedance
TheIXDD409/IXDI409/IXDN409arehighspeedhighcurrent
gate drivers specifically designed to drive the largest
MOSFETs and IGBTs to their minimum switching time and
maximumpracticalfrequencylimits.TheIXDD409/IXDI409/
IXDN409 can source and sink 9A of peak current while
producing voltage rise and fall times of less than 30ns. The
input of the drivers are compatible with TTL or CMOS and are
fully immune to latch up over the entire operating range.
Designed with small internal delays, cross conduction/
currentshoot-throughisvirtuallyeliminatedintheIXDD409/
IXDI409/IXDN409.Theirfeaturesand widesafetymarginin
operatingvoltageandpowermakethedriversunmatchedin
performanceandvalue.
• LowSupplyCurrent
Applications
The IXDD409 incorporates a unique ability to disable the
output under fault conditions. When a logical low is forced
into the Enable input, both final output stage MOSFETs
(NMOS and PMOS) are turned off. As a result, the output of
the IXDD409 enters a tristate mode and achieves a Soft Turn-
Off of the MOSFET/IGBT when a short circuit is detected.
This helps prevent damage that could occur to the MOSFET/
IGBT if it were to be switched off abruptly due to a dv/dt over-
voltagetransient.
• DrivingMOSFETsandIGBTs
• MotorControls
• LineDrivers
• PulseGenerators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DCtoDCConverters
• PulseTransformerDriver
• Limiting di/dt under Short Circuit
• Class D Switching Amplifiers
TheIXDN409isconfiguredasanon-invertinggatedriver,and
theIXDI409isaninvertinggatedriver.
TheIXDD409/IXDI409/IXDN409areavailableinthestandard8-
pinP-DIP(PI),SOP-8(SI),5-pinTO-220(CI)andintheTO-263
(YI)surface-mountpackages.
Figure 1A - IXDD409 Functional Diagram
Figure 1B - IXDN409 Functional Diagram
Ordering Information
Part Number Package Type Temp. Range
Configuration
IXDD409PI
IXDD409SI
IXDD409YI
IXDD409CI
IXDI409PI
IXDI409SI
IXDI409YI
IXDI409CI
IXDN409PI
IXDN409SI
IXDN409YI
IXDN409CI
8-Pin PDIP
8-Pin SOIC
5-Pin TO-263
5-Pin TO-220
8-Pin PDIP
8-Pin SOIC
5-Pin TO-263
5-Pin TO-220
8-Pin PDIP
Non Inverting
With Enable Line
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Inverting
8-Pin SOIC
5-Pin TO-263
5-Pin TO-220
Non Inverting
Figure 1C - IXDI409 Functional Diagram
Copyright © IXYS CORPORATION 2002 Patent Pending
First Release
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Absolute Maximum Ratings (Note 1)
Operating Ratings
Parameter
Value
Parameter
Value
Supply Voltage
All Other Pins
25 V
-0.3 V to V
Maximum Junction Temperature
o
150
C
+ 0.3 V
CC
Operating Temperature Range
o
o
-40 C to 85 C
o
Power Dissipation, TAMBIENT ≤25
8 Pin PDIP (PI)
C
Thermal Impedance (Junction To Case)
975mW
1055mW
17W
o
TO220 (CI), TO263 (YI) (θJC
)
0.95 C/W
8 Pin SOIC (SI)
TO220 (CI), TO263 (YI)
Derating Factors (to Ambient)
8 Pin PDIP (PI)
o
7.6mW/ C
8 Pin SOIC (SI)
o
8.2mW/ C
TO220 (CI), TO263 (YI)
Storage Temperature
Lead Temperature (10 sec)
o
0.14W/ C
o
o
C
-65 C to 150
o
300
C
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD409 configured as described in Test Conditions.
Symbol
VIH
Parameter
Test Conditions
Min
Typ
Max
Units
V
High input voltage
Low input voltage
Input voltage range
Input current
3.5
VIL
0.8
V
VIN
-5
VCC + 0.3
10
V
IIN
-10
0V ≤ VIN ≤ VCC
µA
VOH
VOL
ROH
High output voltage
Low output voltage
VCC - 0.025
V
V
Ω
0.025
1.5
Output resistance
@ Output high
Output resistance
@ Output Low
IOUT = 10mA, VCC = 18V
IOUT = 10mA, VCC = 18V
VCC is 18V
0.8
0.8
9
ROL
IPEAK
IDC
1.5
Ω
A
A
Peak output current
Continuous output
current
Limited by package power
dissipation
2
VEN
VENH
VENL
tR
Enable voltage range
IXDD409 Only
- .3
Vcc + 0.3
V
V
High En Input Voltage
Low En Input Voltage
Rise time
IXDD409 Only
2/3 Vcc
IXDD409 Only
1/3 Vcc
15
V
CL=2500pF Vcc=18V
CL=2500pF Vcc=18V
CL=2500pF Vcc=18V
8
8
10
10
36
ns
ns
ns
tF
Fall time
15
tONDLY
On-time propagation
delay
33
40
tOFFDLY
tENOH
tDOLD
Off-time propagation
delay
Enable to output high
delay time
Disable to output low
Disable delay time
Power supply voltage
CL=2500pF Vcc=18V
IXDD409 Only, Vcc=18V
IXDD409 Only, Vcc=18V
31
33
36
52
30
25
ns
ns
ns
V
VCC
ICC
4.5
18
Power supply current
VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
mA
µA
µA
Specifications Subject To Change Without Notice
2
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Pin Configurations
1 VCC
2 IN
VCC 8
Vcc
OUT
GND
IN
1
2
3
4
5
OUT 7
OUT 6
GND 5
3
EN *
EN *
4 GND
TO220(CI)
TO263(YI)
8 PIN DIP (PI)
SO8 (SI)
Pin Description
SYMBOL
VCC
FUNCTION
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 25V.
Input signal-TTL or CMOS compatible.
Supply Voltage
Input
IN
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output (IXDD409 Only).
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
EN *
Enable
OUT
GND
Output
Ground
* This pin is used only on the IXDD409, and is N/C on the IXDI409 and IXDN409.
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
Figure 2 - Characteristics Test Diagram
V
IN
3
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Typical Performance Characteristics
Fig. 4
30
Fall Timesvs. SupplyVoltage
Fig. 3
40
Rise Times vs. SupplyVoltage
35
30
25
20
15
10
5
25
20
15
10
5
11900 pF
11900 pF
8900 pF
5860 pF
8900 pF
5860 pF
2950 pF
1500 pF
2950 pF
1500 pF
0
0
8
8
9
10
11
12
13
14
15
16
17
18
9
10
11
12
13
14
15
16
17
18
Supply Voltage (V)
Supply Voltage (V)
Fig. 5
Rise And Fall Times vs. Temperature
CL=2500pF, Vcc=18V
Rise Time vs. Load Capacitance
Fig. 6
35
12
8V
10
8
30
25
20
15
10
10V
12V
14V
16V
18V
Risetime
Falltime
6
4
2
0
5
-40
-20
0
25
40
60
85
1.35
2.7
5.4
8.1
10.8
Temperature
Load Capacitance
Fall Time vs. Load Capacitance
Fig. 8
Max/ MinInput vs. Temperature
Fig. 7
25
23
21
19
17
15
13
11
9
3.5
3
8V
10V
Maximum Input High
12V
14V
2.5
2
16V
18V
1.5
1
Minimum Input Low
0.5
7
0
5
-40
-20
0
25
40
60
85
1.35
2.7
5.4
8.1
10.8
Temperature
Load Capacitance (nF)
4
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Supply Current vs. Load Capacitance
Fig. 9
Fig. 10
Supply Current vs. Frequency
Vcc = 18V
Vcc = 18V
1000
100
10
1000
10800 pF
8100 pF
5400 pF
2700 pF
1350 pF
100
10
1
2MHz
1MHz
500kHz
100kHz
50kHz
1
10kHz
0.1
0.1
1000
10000
1
10
100
1000
Frequency (kHz)
Load Capacitance (pF)
Fig. 11
SupplyCurrent vs. Frequency
Vcc =12V
SupplyCurrent vs. Load Capacitance
Vcc =12V
Fig. 12
1000
100
10
1000
100
10
10800 pF
8100 pF
5400 pF
2700 pF
1350 pF
2MHz
1MHz
500kHz
1
100kHz
50kHz
1
0.1
0.01
10kHz
0.1
1
10
100
1000
10000
1000
10000
Frequency (kHz)
Load Capacitance (pF)
Fig. 14
Supply Current vs. Frequency
Vcc =8V
Fig. 13
SupplyCurrent vs. Load Capacitance
Vcc = 8V
1000
1000
100
10
10800 pF
8100 pF
5400 pF
100
10
1
2700 pF
1350 pF
2MHz
1MHz
500kHz
1
100kHz
50kHz
0.1
0.01
10kHz
0.1
1000
10000
1
10
100
1000
10000
Load Capacitance (pF)
Frequency (kHz)
5
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
PropagationDelayvs. SupplyVoltage
Fig. 15
PropagationDelayvs. Input Voltage
Fig. 16
50
48
46
44
42
40
38
36
34
32
30
50
48
46
44
42
40
38
36
34
32
Tondly (DD409, DN409)
Toffdly (DI409)
Tondly (DD409, DN409)
Toffdly (DI409)
Toffdly (DD409, DN409)
Tondly (DI409)
Toffdly(DD409, DN409)
Tondly (DI409)
30
3
8
9
10
11
12
13
14
15
16
17
18
4
5
6
7
8
9
10
11
12
Supply Voltage (V)
Input Voltage (V)
PropagationDelayTimes vs. JunctionTemperature
Fig. 17
Quiescent SupplyCurrent vs. JunctionTemperature
Vcc=18v Vin=5v@1kHz
Fig. 18
45
40
35
30
25
20
15
10
5
0.6
0.5
0.4
0.3
0.2
0.1
0
Tondly (DD409, DN409)
Toffdly (DI409)
Toffdly (DD409, DN409)
Tondly (DI409)
0
-40
-20
0
25
40
60
85
-40
-20
0
25
40
60
85
Temperature (C)
Temperature (C)
Fig. 20
Fig. 19
Vcc vs. P Channel Peak Output Current
CL = 10 nF
Vcc vs. NChannel Peak Output Current
CL=10 nF
0
-2
20
18
16
14
12
10
8
-4
-6
-8
-10
-12
6
4
2
-14
5
0
7.5
10
12.5
15
17.5
20
22.5
25
5
7.5
10
12.5
15
17.5
20
22.5
25
Vcc (V)
Vcc (V)
6
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
NChannel Peak Ouput Current vs. Temperature
Vcc = 18V CL = 10 nF
Fig. 22
Fig. 21
PChannel Output Current vs. Temperature
Vcc =18VCL =10 nF
15
14.5
14
10
9.8
9.6
9.4
9.2
9
13.5
13
12.5
12
8.8
8.6
8.4
8.2
11.5
11
10.5
10
8
-60
-40
-20
0
20
40
60
80
100
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Temperature (C)
HighState Output Resistance vs. SupplyVoltage
Fig. 23
LowState Output Resistance vs. SupplyVoltage
Fig. 24
1.6
1.4
1.2
1
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
5
7.5
10
12.5
15
17.5
20
22.5
25
5
7.5
10
12.5
15
17.5
20
22.5
25
Supply Voltage (V)
Supply Voltage (V)
Figure 25 - Typical Application Short Circuit di/dt Limit
7
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 25, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
andthelowpowerMOSFETgate. PleasenotethatCMOS4000-
series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
theVMO580-02F.
TheIXDD409hastheuniquecapabilitytosoftlyswitchoffthe
high-power MOSFET module, significantly reducing these
Ldi/dttransients.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD409 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD409 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD409 input, and this
pulse will reset the SRFF outputs to normal operation.
Thus, the IXDD409 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD409 is designed to not only provide ±9A under normal
conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD409 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 26.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD409 output. The
SRFF also turns on the low power MOSFET, (2N7000).
Referring to Figure 26, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
In this way, the high-power MOSFET module is softly turned off
by the IXDD409, preventing its destruction.
Figure 26 - Application Test Diagram
+
VB
Ld
10uH
-
Rd
IXDD409
0.1ohm
VCC
VCCA
Rg
High_Power
VMO580-02F
OUT
IN
EN
1ohm
Rsh
1600ohm
+
-
+
-
VCC
VIN
GND
SUB
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
20nH
One ShotCircuit
Rcomp
0
Comp
LM339
5kohm
+
V+
NAND
CD4011A
NOT2
CD4049A
C+
NOT1
CD4049A
V-
-
100pF
Ccomp
1pF
Ros
+
-
R
1Mohm
REF
Cos
1pF
Q
NOT3
CD4049A
NOR1
CD4001A
S
EN
NOR2
CD4001A
SR Flip-Flop
8
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Supply Bypassing and Grounding Practices,
Output Lead inductance
TTL to High Voltage CMOS Level Translation
(IXDD409 Only)
The enable (EN) input to the IXDD409 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD409 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, VCC =15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD409 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD409/IXDI409/IXDN409, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
toSupplyBypassing, Grounding, andminimizingthe Output
Lead Inductance.
Say, for example, we are using the IXDD409 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns…
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns we can determine that to charge 5000pF to 25 volts
in25nswilltakeaconstantcurrentof5A. (Inreality,thecharging
current won’t be constant, and will peak somewhere around
8A).
The circuit in Figure 27 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD409 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is
positioned at the midpoint of the expected TTL logic transition
levels.
SUPPLYBYPASSING
In order for our design to turn the load on properly, the IXDD409
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse current-
servicecapacitors). Leadlengthsmayradiateathighfrequency
due to inductance, so care should be taken to keep the lengths
oftheleadsbetweenthesebypasscapacitorsandtheIXDD409
to an absolute minimum.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1
+
VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD409 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 27 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD409 EN input will enable
it, allowing the gate driver to fully function as an 8 Amp output
driver.
GROUNDING
In order for the design to turn the load off properly, the IXDD409
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD409
and it’s load. Path #2 is between the IXDD409 and it’s power
supply. Path #3 is between the IXDD409 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. Inaddition, everyeffortshouldbemadetokeepthese
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD409.
The total component cost of the circuit in Figure 27 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 27 - TTL to High Voltage CMOS Level Translator
CC
(From Gate Driver
Power Supply)
R3
10K
OUTPUTLEADINDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
High Voltage
EN
V
DD
(From Logic
Power Supply)
CMOS
Output
3.3K
R1
Q1
2N3904
(To IXDD409
EN Input)
3.3K R2
or TTL
Input)
9
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
Package Information
NOTE: Mounting or solder tabs on all packages are connected to ground
IXYS Corporation
IXYS Semiconductor GmbH
Directed Energy, Inc.
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
www.ixys.com
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
An IXYS Company
2401 Research Blvd. Ste. 108
Ft. Collins, CO 80526
e-mail: sales@ixys.net
Tel: 970-493-1901; Fax: 970-493-1903
www.directedenergy.com
e-mail: deiinfo@directedenergy.com
Doc #9200-0252 R1
10
相关型号：
IXDD504
4 Ampere Dual Low-Side Ultrafast MOSFET Drivers with Enable for fast, controlled shutdown
IXYS
©2020 ICPDF网 联系我们和版权申明