KK74ACT175 [KODENSHI]
Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS; 四D触发器与普通时钟和复位高速硅栅CMOS型号: | KK74ACT175 |
厂家: | KODENSHI KOREA CORP. |
描述: | Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS |
文件: | 总6页 (文件大小:332K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74ACT175
Quad D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The KK74ACT175 is identical in pinout to the LS/ALS175,
HC/HCT175. The KK74ACT175 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is asynchronous
and occurs when a low level is applied to the Reset input. Information at a
D input is transferred to the corresponding Q output on the next positive-
going edge of the Clock input.
ORDERING INFORMATION
KK74ACT175N Plastic
KK74ACT175D SOIC
TA = -40° to 85° C for all packages
•
•
•
•
•
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
X
Outputs
Reset
L
D
X
H
L
Q
L
H
L
Q
H
L
PIN 16=VCC
PIN 8 = GND
H
H
H
H
L
X
no change
X = Don’t care
1
KK74ACT175
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
±50
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Min
4.5
0
Max
Unit
V
5.5
VCC
140
+85
-24
24
VIN, VOUT
TJ
V
°C
TA
Operating Temperature, All Package Types
Output Current - High
-40
°C
IOH
mA
mA
ns/V
IOL
Output Current - Low
tr, tf
Input Rise and Fall Time *
(except Schmitt Inputs)
VCC =4.5 V
VCC =5.5 V
0
0
10
8.0
* VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74ACT175
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limits
Symbol
VIH
Parameter
Test Conditions
VOUT=0.1 V or VCC-0.1 V
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ -50 µA
Unit
V
25 °C
-40°C to
85°C
Minimum High-
Level Input Voltage
4.5
5.5
2.0
2.0
2.0
2.0
VIL
Maximum Low -
Level Input Voltage
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum High-
Level Output Voltage
4.5
5.5
4.4
5.4
4.4
5.4
V
*VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
4.5
5.5
3.86
4.86
3.76
4.76
VOL
Maximum Low-
Level Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
V
IOUT ≤ 50 µA
*VIN=VIH or VIL
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
IIN
∆ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
VIN=VCC or GND
VIN=VCC - 2.1 V
5.5
5.5
5.5
5.5
5.5
±0.1
±1.0
1.5
75
µA
mA
mA
mA
µA
Additional Max.
ICC/Input
+Minimum Dynamic VOLD=1.65 V Max
Output Current
+Minimum Dynamic VOHD=3.85 V Min
Output Current
-75
80
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
8.0
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
KK74ACT175
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
25 °C -40°C to 85°C
Symbol
Parameter
Unit
Min Max
175
Min
145
1.5
Max
fmax
tPLH
tPHL
Maximum Clock Frequency (Figure 1)
MHz
ns
Propagation Delay, Clock to Q or Q (Figure 1)
Propagation Delay, Clock to Q or Q (Figure 1)
2.0
2.0
2.0
10.0
11.0
9.5
11.0
12.0
10.5
1.5
ns
tPHL, tPLH Propagation Delay, Reset to Q or Q (Figure 2)
1.5
ns
CIN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
45
pF
TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
25 °C -40°C to 85°C
Symbol
Parameter
Unit
ns
tsu (H) Minimum Setup Time, Data to Clock (Figure 3)
(L)
2.0
2.5
2.0
2.5
th
tw
Minimum Hold Time, Clock to Data (Figure 3)
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
1.0
3.0
3.0
0
1.0
4.0
3.5
0
ns
ns
ns
ns
tw
trec
Minimum Recovery Time, Reset to Clock
(Figure 2)
4
KK74ACT175
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
KK74ACT175
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
6
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