KK74HC174A [KODENSHI]
Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS; 六路D触发器与普通时钟和复位高性能硅栅CMOS
| 型号： | KK74HC174A |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS |
| 文件： | 总6页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC174A
Hex D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The KK74HC174A is identical in pinout to the LS/ALS174. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
This device consists of six D flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-to-high transition of the Clock
input. Reset is asynchronous and active-low.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HC174AN Plastic
KK74HC174AD SOIC
TA = -55° to 125° C for all packages
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
X
Output
Reset
L
D
X
H
L
Q
L
H
PIN 16=VCC
PIN 8 = GND
H
H
L
H
L
X
X
no change
no change
H
X = Don’t care
L = LOW voltage level
H = HIGH voltage level
1
KK74HC174A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1,5 mm from Case for 4 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC174A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
-55°C ≤85 ≤125
to
°C
°C
25°C
Minimum High-
Level Input Voltage
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VOUT≥ VCC-0.1 V
or ≤0.1 V
⎢IOUT⎢≤ 20 µA
VIL
Maximum Low -
Level Input Voltage
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOUT≤0.1 V
or ≥VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
ICC
Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
6.0
4.0
40 160
I
OUT=0µA
3
KK74HC174A
AC ELECTRICAL CHARACTERISTICS (CL=50pF, Input tr=tf=6.0 ns, VIL= 0 V, VIH=Vcc)
VCC
V
Guaranteed Limit
≤85°C ≤125°C
Symbol
fmax
Parameter
Unit
MHz
ns
-55°C
to
25°C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
tPLH, tPHL Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
4.5
6.0
110
22
140
28
165
33
19
24
28
tPHL
Maximum Propagation Delay , Reset to Q
(Figures 2 and 4)
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
62
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns, VIL= 0 V, VIH=Vcc)
VCC
V
Guaranteed Limit
Symbol
tSU
Parameter
Unit
-55 °C to
25°C
≤85°C
≤125°C
Minimum Setup Time, Data to
Clock (Figure 3)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
ns
ns
ns
ns
ns
th
trec
tw
Minimum Hold Time, Clock
to Data (Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Minimum Recovery Time,
Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
4
KK74HC174A
tw
VCC
t
t
f
r
RESET
Q
50%
VCC
GND
90%
50%
10%
CLOCK
tPHL
GND
tw
50%
1/f
max
tPLH
tPHL
trec
90%
Q
50%
10%
VCC
CLOCK
50%
GND
tTLH
tTHL
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
TEST POINT
VALID
VCC
DATA
50%
GND
DEVICE
UNDER
TEST
OUTPUT
tsu
th
*
L
VCC
C
CLOCK
50%
GND
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
5
KK74HC174A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
6
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