KK74HC533ADW [KODENSHI]
FF/Latch;
| 型号： | KK74HC533ADW |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | FF/Latch 锁存器 |
| 文件： | 总7页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC533A
Octal 3-State Inverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The KK74HC533A is identical in pinout to the LS/ALS533. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
ORDERING INFORMATION
KK74HC533AN Plastic
KK74HC533ADW SOIC
TA = -55° to 125° C for all packages
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Latch
Enable Enable
Output
Q
Output
D
L
L
L
H
H
L
H
L
L
PIN 20=VCC
PIN 10 = GND
H
X
no
change
H
X
X
Z
X = don’t care
Z = high impedance
1
KK74HC533A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±35
DC Supply Current, VCC and GND Pins
±75
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
VIN, VOUT
TA
VCC
+125
V
-55
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC533A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN= VIL or VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
IOZ
Maximum Three-
State Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10
ICC
Maximum Quiescent VIN=VCC or GND
6.0
8.0
80
160
µA
Supply Current
(per Package)
I
OUT=0µA
3
KK74HC533A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
Unit
ns
25 °C
to
≤85°C ≤125°C
-55°C
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
175
35
220
44
265
53
30
37
45
tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL, tPZH Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
37
pF
PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
Unit
ns
25 °C to -55°C
≤85°C
≤125°C
Minimum Setup Time, Input D to
Latch Enable (Figure 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
th
Minimum Hold Time, Latch Enable
to Input D(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
4
KK74HC533A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
5
KK74HC533A
EXPANDED LOGIC DIAGRAM
6
KK74HC533A
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
10
20
1
Symbol MIN
MAX
26.92
7.11
B
24.89
6.1
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
2.54
7.62
G
H
J
C
SEATING
PLANE
-T-
K
N
0
10
°
°
M
J
G
H
D
K
L
M
N
2.92
7.62
0.2
3.81
8.26
0.36
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
Dimension, mm
Symbol MIN
MAX
13
H
B
P
12.6
7.4
A
B
C
D
F
7.6
2.35
0.33
0.4
2.65
0.51
1.27
1
10
G
R x 45
C
-T-
SEATING
PLANE
1.27
9.53
G
H
J
K
M
D
J
F
M
0.25 (0.010) M T C
0
°
8
°
NOTES:
0.1
0.23
10
0.3
0.32
10.65
0.75
K
M
P
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B 0.25 mm (0.010) per side.
‑
0.25
R
7
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