ML145040RP [LANSDALE]
8-Bit A/D Converters With Serial Interface; 具有串行接口的8位A / D转换器
| 型号： | ML145040RP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 8-Bit A/D Converters With Serial Interface |
| 文件： | 总12页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145040
ML145041
8-Bit A/D Converters With
Serial Interface
Silicon-Gate CMOS
SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC145040, MC145041
The ML145040 and ML145041 are low-cost 8-bit A/D Converters with
serial interface ports to provide communication with microprocessors and
microcomputers. The converters operate from a single power supply with a
maximum nonlinearity of 1/2 LSB over the full temperature range. No
external trimming is required.
P DIP 20 = RP
ERAMIC PLASTIC
ASE 732 CASE 738
The ML145040 allows an external clock input (A/D CLK) to operate the
dynamic A/D conversion sequence. The ML145041 has an internal clock
and an end–of–conversion signal (EOC) is provided.
SO 20W = -6P
SOG
CASE 751D
• Operating Voltage Range: V
DD
= 4.5 to 5.5 Volts
• Successive Approximation Conversion Time:
ML145040 – 10 µs (with 2 MHz A/D CLK)
ML145041 – 20 µs Maximum (Internal Clock)
• 11 Analog Input Channels with Internal Sample and Hold
• 0- to 5-Volt Analog Input Range with Single 5-Volt Supply
• Ratiometric Conversion
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145040P
MC145040DW
MC145041P
ML145040RP
ML145040-6P
ML145041RP
ML145041-6P
MC145041DW
• Separate V and V
Pins for Noise Immunity
ref AG
• Wide V Range
ref
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• No External Trimming Required
• Direct Interface to Motorola SPI and National
MICROWIRE Serial Data Ports
• TTL/NMOS–Compatible Inputs May be Driven with CMOS
• Outputs are CMOS, NMOS or TTL Compatible
• Very Low Reference Current Requirements
• Low Power Consumption: 11 mW
• Internal Test Mode for Self Test
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Page 2 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Page 3 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Page 4 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Page 5 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUTS
CS (Pin 15)
from the MPU system clock. Deviations from a 50% duty
cycle can be tolerated if each half period is > 238 ns.
Active–low chip select input. CS provides three–state control
of D . CS at a high logic level forces D
to a high–imped-
out out
EOC (Pin 19, ML145041 only)
ance state. IN addition, the device recognizes the falling edge
of CS as a serial interface reset to provide synchronization
between the MPU and the A/D converter’s serial data stream.
To prevent a spurious reset from occurring due to noise on the
CS input, a delay circuit has been included such that a CS sig-
nal of duration ≤1 A/D CLK period (ML145040) or ≤500 ns
(ML145041) is ignored. A valid CS signal is acknowledged
when the duration is ≥3 A/D CLK periods (ML145040) or ≥3
µs (ML145041)
End–of–conversion output. EOC goes low on the negative
edge of the eighth SCLK. The low–to–high transition of EOC
indicates the A/D conversion is complete and the data is ready
for transfer.
ANALOG INPUTS AND TEST MODE
AN0 through AN10 (Pins 1-9, 11, 12)
Analog multiplexer inputs. The input AN0 is addressed by
loading $0 into the serial data input, D . AN1 is addressed by
$1, AN2 by $2…AN10 via $A. The mux features a
in
CAUTION
A reset aborts a conversion sequence, therefore
high–to–low transitions on CS must be avoided dur-
ing the conversion sequence.
break–before–make switching structure to minimize noise
injection into the analog inputs. The source impedance driving
these inputs must be ≤ 10 kΩ. NOTE: $B addresses an on–chip
test voltage of (V + V )/2, and produces an output of $80
ref
AG
if the converter is functioning properly. However, a 1 LSB
deviation from $80 occurs in the presence of sufficient system
Dout (Pin 16)
Serial data output of the A/D conversion result. The 8–bit
serial data stream begins with the most significant bit and is
noise (external to the chip) on V , V , V or V
.
DD SS ref AG
shifted out on the high–to–low transition of SCLK. D
is a
out
is
POWER AND REFERENCE PINS
VSS and VDD (Pins 10 and 20)
Device supply pins. V is normally connected to digital
three–state output as controlled by CS. However, D
forced into a high–impedance state after the eighth SCLK,
independent of the state of CS. See Figures 9, 10, 11, or 12.
out
SS
is connected to a positive digital supply voltage.
ground; V
DD
V
– V variations over the range of 4.5 to 5.5 volts do not
DD
SS
D
(Pin 17)
in
Serial data input. The 4–bit serial data stream begins with the
affect the A/D accuracy. Excessive inductance in the V
or
DD
V
lines as on automatic test equipment, may cause A/D off-
SS
sets > / LSB.
most significant address bit of the analog mux and is shifted in
on the low–to–high transition of SCLK.
1
2
V
and V (Pins 13 and 14)
ref
AG
SCLK (Pin 18)
Analog reference voltage pins which determine the lower and
Serial data clock. THe serial data register is completely stat-
ic, allowing SCLK rates down to DC in a continuos or inter-
mittent mode. SCLK need not be synchronous to the A/D CLK
(ML145040) or the internal clock (ML145041). Eight SCLK
cycles are required for each simultaneous data transfer, the
low–to–high transition shifting in the new address and the
high–to–low transition shifting out the previous conversion
result. The address is acquired during the first four SCLK
cycles, with the interval produced by the remaining four cycles
being used to begin charging the on–chip sample–and–hold
capacitors. After the eighth SCLK, the SCLK input is inhibited
(on–chip) until the conversion is complete.
upper boundary of the A/D conversion. Analog input voltages ≥
V
ref
produce an output of $FF and input voltages ≤ V
pro-
AG
duce an output of $00. CAUTION: THe analog input voltage
must be ≥ V and ≤ V . The A/D conversion result is ratio-
SS
ref AG
DD
metric to V – V
as shown by the formula:
V
and V
AG
should be as noise–free as possible to avoid
ref
degradation of the A/D conversion. Noise on either of these
pins will couple 1:1 to the analog input signal i.e. a 20 mV
A/D CLK (Pin 18, ML145040 only)
change in V can cause a 20 mV error in the conversion
ref
result. Ideally V and V
should be single-point connected
to the voltage supply driving the system’s transducers.
ref AG
A/D clock input. This pin clocks the dynamic A/D conver-
sion sequence, and may be asynchronous and unrelated to
SCLK. The signal must be free running, and may be obtained
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ML145040, ML145041
LANSDALE Semiconductor, Inc.
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ML145040, ML145041
LANSDALE Semiconductor, Inc.
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DESCRIPTION
may be direcly interfaced to these ADCs, eliminating the need
for buffer amplifiers. Separate lines connect the V and V
ref
AG
This example application of the ML145040/ML145041
ADCs interfaces three controllers to a microprocessor and
processes data in real–time for a video game. The standard joy-
stick X–axis (left/right) and Y–axis (up/down) controls as well
as engine thrust controls are accommodated
Figure 13 illustrates how the ML145040/ML145041 is used
as a cost–effective means to simplify this type of circuit
design. Utilizing one ADC, three controllers are interfaced to a
CMOS or NMOS microprocessor with a serial peripheral inter-
face (SP) port. Processors with National Semiconductor’s
MICROWIRE serial port may also be used. Full duplex opera-
tion optimizes throughput for this system.
pins on the ADC with the controllers to provide isolation from
system noise.
Although not indicated in Figure 13, the V and controller
ref
ouput lines may need to be shielded, depending on their length
and electrical environment. This should be verified during pro-
totyping with an oscilloscope. If shielding is required, a twist-
ed pair or foil–shielded wire (not coax) is appropriate for this
low frequency application. One wire of the pair of the shield
must be V
.
AG
A reference circuit voltage of 5 volts is used for this applica-
tion. The reference circuitry may be as simple as tying V to
AG
system ground and V to the system’s positive supply. (See
ref
Figure 14.) However, the system power supply noise may
require that a seperate supply be used for the voltage reference.
DIGITAL DESIGN CONSIDERATIONS
This supply must provide source current for V as well as
ref
Motorola’s MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may be
used if power consumption is not critical. A V
current for the controller potentionmeters.
A bypass capacitor across the V and V
mended. These pins are adjacent on the ADC package which
facilitates mounting the capacitor very close to the ADC.
pins is recom-
ref
AG
to V 0.1
DD
SS
µF bypass capacitor should be closely mounted to the ADC.
Both the ML145040 and ML145041 will accommodate all
the analog system inputs. The ML145040, when used with a 2
MHz MCU, takes 24 µs to sample the analog input, perform
the conversion, and transfer the serial data at 1 MHz.
Thirty–two A/D Clock cycles (2 MHz at input pin 19) must be
provided and counted by the MCU after the eighth SCLK
before reading the ADC results. The ML145041 has the
end–of–conversion (EOC) signal (at output pin 19) to define
when data is ready, but has a slower 40 µs cycle time.
However, the 40 µs is constant for serial data rates of 1 MHz
independent of the MCU clock frequency. Therefore, the
ML145041 may be used with CMOS MCU operating at the
reduced clock rates to minimize power consumption without
sacrificing ADS cycle times, with EOC being used to generate
an interrupt. The ML145041 may also be used with MCU’s
which do not provide a system clock.)
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straightforward. The
nine analog inputs, AN0 through AN8, are scanned by read-
ing the analog value of the previously addressed channel into
the MCU and sending the address of the next channel to to be
read to the ADC, simultaneously. All nine inputs may be
scanned in a minimum of 216 µs (ML145040) or 360 µs
(ML145041).
If the design in realized using the ML145040, 32 A/D clock
cycles (at pin 19) must be counted by the MCU to allow time
for A/D conversion. The designer utilizing the ML145041 has
the end–of–conversion signal (at pin 19) to define the conver-
sion interval. EOC may be used to generated an interrupt,
which is serviced by reading the serial data from the ADC. The
software flow should then process and format the data, and
transfer the information to the video circuitry for updating the
display.
ANALOG DESIGN CONSIDERATIONS
Controllers with output impedances of less than 10 kilohms
Page 9 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Page 10 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145040RP, ML145041RP)
CASE 738-03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
0
B
1
C
L
INCHES
MIN MAX
1.070 25.66
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
-T-
SEATING
PLANE
K
M
0.050 BSC
1.27 BSC
1.27
0.050
0.070
1.77
F
E
N
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
0°
D 20 PL
M
M
0.25 (0.010)
T
B
0°
15°
15°
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T
A
Page 11 of 12
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Issue A
ML145040, ML145041
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SOG 20W = -6P
(ML145040-6P, ML145041-6P)
CASE 751D-04
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
20
11
-B-
P 10 PL
M
M
0.010 (0.25)
B
1
1
0
D 20 PL
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
B
A
DIM
A
B
C
D
F
G
J
MIN
12.65
7.40
MAX
12.95
7.60
MIN
MAX
0.499
0.292
0.093
0.014
0.020
0.510
0.299
0.104
0.019
0.035
F
2.35
0.35
0.50
2.65
0.49
0.90
R X 45°
1.27 BSC
0.050 BSC
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
K
M
P
C
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
-T-
R
M
SEATING
PLANE
G 18 PL
K
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue A
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